JPS62293679A - Field-effect semiconductor device and manufacture thereof - Google Patents

Abstract

PURPOSE:To make it possible to form a very low resistance ohmic contact without heat treatment of alloy after evaporation, by using InGaAs for an ohmic-contact forming semiconductor layer. CONSTITUTION:On a GaAs semi-insulating substrate 1, the following layers are sequentially formed: an n-GaAs layer 2 having a thickness of 500 Angstrom and a carrier concentration of 1X10<18>/cm<3>; an n-AlGaAs layer 3 having a thickness of 5 Angstrom and a carrier concentration of 1X10<18>/cm<3>; and an n<+>-InGaAs layer 4 having a thickness of 2,000 Angstrom and a carrier concentration of 1X10<19>/cm<3>. Then a gate electrode undergoes selective etching using CCl2F2, with a resist pattern 5 as a mask, and a window is provided. The etching is stopped at the AlGaAs 3. Then, a source electrode S, ohmic contact of a drain electrode D and a gate electrode G are formed simultaneously using Cr/Au by mask alignment of one time.

Description

[Detailed Description of the Invention] Detailed Description of the Invention [Summary] A field-effect semiconductor device based on forming gate, source, and drain electrodes in one process by using InGaAs non-blowing ohmic contacts. and its manufacturing method, which enables high speed and low power consumption.

[Industrial application field]

The present invention relates to a self-line type GILA8 field effect semiconductor device i (FET), and particularly reduces its parasitic resistance.
The present invention relates to an element structure that enables high speed and low power consumption, and a manufacturing method thereof.

[Conventional technology]

Recently, development of compound semiconductor devices has become active, and in particular, GaA1 MESFET (metal-semiconductor field effect transistor) is attracting attention as the next transistor after Sl.

FIG. 2 shows a cross-sectional configuration of essential parts of a conventional GaAs MESFET. In the figure, 21 is a semi-insulating SI-G
It is an aAs substrate with an n-GaAs layer 2 as an active layer on it.
4 are formed, and furthermore, high concentration n-GRAIL layers 22 and 23 in the source and drain regions are formed, and a source electrode S, a drain electrode, and a gate electrode G are formed, respectively. However, in this structure, since the n-GaAs layers 22 and 25 are not formed in cell 7 alignment with respect to the gate electrode, the gate G and the n+-GaAs layer 2
There is a problem in that parasitic resistance occurs between 2 and 25, increasing the source resistance. Further, since the n-GaAs layer of relatively low resistance of the active layer 24 is exposed between the gate, source, and drain, there is a drawback that the uniformity of the threshold value vth is deteriorated due to the effect of the surface depletion layer.

Therefore, as a conventional method to improve this drawback, as shown in FIG. There is a method in which an n+ layer is formed by ion implantation and mirror annealing is performed to form source and drain electrode regions. This self-line type GaAg MESFIEET is
Since the layer has a high concentration of , the resistance is reduced, and the influence of the surface depletion layer can be avoided, thereby making it possible to prevent fluctuations in the threshold value. As a result, this self-line type GaAs Mg5FET can have small parasitic resistance and capacitance, and is advantageous for high speed and low power consumption.

[Problem that the invention seeks to solve]

However, the improved cell 7 aligned GaA
The s MESFET has a problem in that the resistance of the gate becomes high because the resistance of the source electrode WSl used for aligning the cell 7 is high. Therefore, the present invention aims to provide a cell 7-aligned Gs+Aa Mg5FET that reduces gate resistance and is easy to process.

[Means for solving problems]

In order to solve the above-mentioned problems, the present invention has developed a cell 7 aligned type GaA@ which is based on forming gate, source and drain electrodes in one process by using InGaAs non-alloy ohmic contacts.
MESFET is provided.

[Effect]

InGaAs is non-alloyed and can form extremely good ohmic contact with metal electrodes.

Therefore, in the present invention, focusing on this, the source,
By using 1nGaAs for the drain electrode part,
The same metal is used for the formation of the gate electrode and the source and drain metal electrodes, making it possible to form them in the same process. Since it is a non-alloy, there is no heat treatment after forming the gate electrode, so there is no fluctuation in threshold value, and the distance between the source, drain, and gate electrodes can be accurately defined, which improves manufacturing yield. , it is possible to achieve high speed and low power consumption of the device.

〔Example〕

FIG. 1 shows a cross-sectional view of the manufacturing process of an element according to an embodiment of the present invention.The present invention will be explained in more detail below using this cross-sectional view.

Refer to FIG. 1(A) First, the following layers are sequentially formed on a GaAs semi-insulating substrate 1. Referring to FIG.

2...n-G 凰A8 layer thickness soo
X=α34-n when expressed as a I-X A s
+-InGaAs layer thickness 2000 A Carrier concentration I x 10''/crAIn, Gt
y = a, s when l-, Am. Refer to FIG. 1B. Thereafter, the gate electrode portion is selectively etched at cct, y using the resist pattern 5 as a mask to open a window. Etching is stopped at AtGiAa3.

Refer to Figure 1 (C) Next, add Cr/A u in one scan,
A source electrode S, an ohmic contact for drain electric polishing, and a gate electrode G are formed at the same time.

For example, Cr (chromium) is deposited to a thickness of 500^ by E-gun deposition (electron gun deposition), Au is deposited to a thickness of 3000^ by ordinary deposition using resistance heating, and then the butter is deposited. It is only necessary to form each electrode by etching. In this case, unlike conventional AuG/Au, an extremely low resistance ohmic contact can be formed without heat treatment of the alloy after deposition, so the gate electrode does not undergo heat treatment and the threshold value No variation in vth occurs.

With respect to n+-InGaAs, Cr/Au is non-alloy and can form an extremely low-resistance ohmic contact, and can form a contact resistance as low as 1×10'''' to 10-80-.

As mentioned above, gate is created by matching the mask once.

A FET in which the source and drain electrodes are formed in a self-aligned manner can be manufactured, and the process can be simplified. Further, the distance between the gate electrode G and the n+-InGaAs layer 4 constituting the source and drain electrodes can be formed close to each other by about 0.1 μm using a high-precision stepper.

In the above embodiments, Cr/Au is used as the metal of the source, drain electrode, and gate electrode, but the present invention is not limited to this, and other metal materials may be used, such as TiPtAu, Au, At, etc. can be used, and it is possible to use a material for the gate that has a lower resistance (about 1/100) than WSL, which is conventionally used for the self-line type.

〔Effect of the invention〕

As described above, according to the present invention, by using InGaAs for the semiconductor layer for forming an ohmic contact, an ohmic contact with extremely low resistance can be formed without heat treatment of the alloy after vapor deposition. Gate with just one mask adjustment.

An FgT in which the source and drain electrodes are formed in a self-aligned manner can be manufactured, and the process can be simplified. Further, since the gate electrode is not subjected to alloy heat treatment, the threshold value vth does not vary. Furthermore, it is possible to employ a gate electrode material having a lower resistance than that of the conventional cell 7-aligned type GaAs MESFεT.

[Brief explanation of the drawing]

1A to 1C are cross-sectional views of the device manufacturing process according to the embodiment of the present invention, FIG. 2 is a cross-sectional view of the device of Conventional Example 1, and FIG. 5 is a cross-sectional view of the device of Conventional Example 2. 1...GaAg semi-abundant group, tentative 'l--n-GIAB 11 3 =-n-ALGaAs layer 4/n+-InGaA@ layer 5...Resist pattern S...Source electrode p...・Drain electrode G...Gate electrode

Claims (2)

[Claims] (1) A field effect semiconductor device having an active layer of GaAs of one conductivity type, which has source and drain contact regions made of a high concentration InGaAs layer of one conductivity type that is lattice matched with GaAs on the active layer. and I constituting each contact region.
A field effect semiconductor device comprising electrodes made of the same metal material formed on an nGaAs layer and a GaAs active layer. (2) forming a single conductivity type GaAs layer as an active layer on the substrate;
A high concentration InGaAs layer of one conductivity type is formed on the GaAs layer, a gate region portion of the InGaAs layer is removed, and then the same metal material is deposited on the gate region and the InGaAs layer to form the source and drain. 1. A method for manufacturing a field effect semiconductor device, comprising the step of simultaneously forming an electrode and a gate electrode in a non-alloy manner.