JPH06310536A - Field-effect transistor and its manufacture - Google Patents

Abstract

PURPOSE:To provide a high-speed FET whose output current is satisfactorily large and a FET whose channel electron mobility is high and saturation electron velocity is high. CONSTITUTION:A buffer layer 2, a first channel layer 3, a first spacer layer 4, a second channel layer 5, a second spacer layer 6, a third channel layer 7 and a cap layer 8 are formed by crystallization on a semi-insulating GaAs semiconductor substrate 1 one by one. A drain region 9 and a source region 10 are formed thereafter, and a gate electrode 11 is formed in Schottky contact with the cap layer 8. A drain electrode 12 and a source electrode 13 are formed in ohmic contact with the drain region 9 and the source region 10.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a structure of a field effect transistor (FET) which operates at a very high speed and a manufacturing method thereof.

[0002]

2. Description of the Related Art Conventionally, there is an FET having a so-called pulse-doped structure in an active layer in which a current channel is formed as an FET which realizes an ultra-high speed operation. In this pulse-doped FET, the impurity profile of the active layer is in an undoped state up to a predetermined depth from the substrate surface. However, when reaching a predetermined depth from the surface of the substrate, the impurity concentration changes in a pulse shape or a step shape to a high concentration, and further returns to an undoped state at a deep substrate position. An example of such a pulse-doped structure FET is, for example, US Pat. No. 4,163,984 or the following document 759.
Shown on the page.

1986 IEEE IEDM “A 760mS / mm N + SELF-AL
IGNED ENHANCEMENT MODE DOPED-CHANNEL MIS-LIKE FET
(DMT) ”However, in such a pulse-doped structure FET, it is not possible to sufficiently secure the amount of electrons forming the current channel. Therefore, in a separate patent application by the present applicant (Japanese Patent Laid-Open No. 4-245646),
An FET having a pulse-doped structure in which two active layers are provided has been proposed. According to such a FET, the active layer has two layers.
Since the layers are provided, the amount of electrons forming the current channel is increased and high output is achieved.

[0004]

However, in a conventional FET having a structure in which two active layers are provided, if the long gate effect occurs due to the surface depletion layer on the drain electrode side, the effective gate length increases and The surface depletion layer depletes the active layer provided on the surface side of the substrate. When the active layer is depleted, channel electrons are prevented from traveling and the total amount of electrons forming the current channel is reduced. As a result, a high current output may not be obtained in the FET having the conventional structure.

In the conventional pulse-doped structure FET as shown in the above-mentioned US patent, the electrons forming the channel travel in the active layer having a high impurity concentration in the low electric field region. Therefore, the electrons were greatly affected by the impurity scattering, and the electron mobility decreased in the low electric field region. As a result, the high frequency operation characteristics of the device were not sufficiently improved. Further, the transconductance g _m, which represents the amount of change in drain current with respect to the change in gate voltage, could not be maintained at a constant value over a constant change in gate voltage.

[0006]

The present invention has been made in order to solve such a problem, and in an FET using a semiconductor layer thinned with a high concentration of impurities as a channel layer, the above-mentioned channel is used. The layer is characterized in that three or more semiconductor layers are formed with an undoped layer interposed therebetween.

Further, in an FET having a channel layer of a semiconductor layer thinned by containing impurities at a high concentration, the channel layer is formed of a plurality of semiconductor layers with an undoped layer sandwiched therebetween. A doping layer is formed above the semiconductor layer located on the surface side of the substrate with an undoped layer sandwiched between them. The doping concentration and thickness of the doping layer are set such that the surface depletion layer does not spread to the channel layer. It is characterized in that it is formed to a thickness of.

Further, in an FET using as a channel layer a semiconductor layer thinned by containing impurities at a high concentration, a plurality of the semiconductor layers forming the channel layer are formed, and these semiconductor layers are provided between these semiconductor layers. The intermediate concentration layer containing impurities at a lower concentration than the impurity concentration of 1. is formed.

The intermediate concentration layer is formed by diffusing the impurities of each semiconductor layer into the undoped layer by heat treatment, and is also formed by crystal growth in which the impurity concentration is controlled. is there.

[0010]

The extension of the surface depletion layer from the substrate surface to the deep portion is blocked by the semiconductor layer located closest to the substrate surface side. The semiconductor layers forming the channel layer are formed in three or more layers with the undoped layer sandwiched therebetween, and a plurality of semiconductor layers are provided in the semiconductor substrate deeper than the semiconductor layer located closest to the substrate surface side. Therefore, even if the semiconductor layer located closest to the substrate surface side is depleted, a sufficient amount of electrons forming the current channel is secured.

Further, when a doping layer is formed with a predetermined impurity concentration and a predetermined thickness on the channel layer located closest to the substrate surface, the surface depletion layer extends from the substrate surface to the deep portion. It is blocked by this doping layer provided on top of the layer. Since a plurality of semiconductor layers forming the channel layer are provided below the doping layer, the amount of electrons forming the current channel is sufficiently secured.

Further, in the FET in which the intermediate concentration layer is formed between the plurality of semiconductor layers, since the intermediate concentration layer contains impurities at a low concentration, channel electrons are also generated by the impurities present in the intermediate concentration layer. Is generated. Therefore,
The electrons forming the current channel are distributed in the intermediate concentration layer between the semiconductor layers even in the low electric field region, and travel in the intermediate concentration layer having a lower impurity concentration than the semiconductor layer.

When the intermediate concentration layer is formed by heat treatment, impurities are contained in a low concentration in each layer sandwiching the plurality of semiconductor layers on the outermost side, and channel electrons are included in both outermost layers. Will also be distributed. Therefore, the channel electrons travel in both outermost layers having a low impurity concentration in addition to the intermediate concentration layer.

[0014]

FIG. 1 is a process sectional view showing a method of manufacturing an FET according to a first embodiment of the present invention. This manufacturing method will be described below.

MB is formed on the semi-insulating GaAs semiconductor substrate 1.
Each semiconductor layer described below is sequentially deposited using a crystal growth technique such as an E (molecular beam epitaxy) method or an OMVPE (organic metal vapor phase epitaxial) method. First, GaA
s Undoped GaAs buffer layer 2 on semiconductor substrate 1
Are crystal-grown. When the buffer layer 2 is formed by the OMVPE method, the supply ratio of each of the group III raw material Ga and the group V raw material As is controlled to set the background conductivity type to p ⁻ -type undoped. The impurity concentration is suppressed to a low impurity concentration of 5 × 10 ¹⁶ [cm ⁻³ ] or less.

Next, Si-doped GaA is formed on the buffer layer 2.
The s layer is crystal-grown to form the first channel layer 3 as the first semiconductor layer. This first channel layer 3 is n
Si ions as a type impurity are contained in a high concentration of about 3 × 10 ¹⁸ [cm ⁻³ ] and the thickness is reduced to 80 Å. Subsequently, the first spacer layer 4 made of undoped GaAs is crystal-grown on the first channel layer 3 to a thickness of 50Å. The background conductivity of the first spacer layer 4 is n ⁻ type when formed by the OMVPE method, and the impurity concentration thereof is suppressed to a low impurity concentration of 5 × 10 ¹⁵ [cm ⁻³ ] or less. . The first spacer layer 4
Has a p ^- type conductivity when formed by the MBE method.

Further, on this first spacer layer 4, a second channel layer 5 as a second semiconductor layer, a second spacer layer 6, and a third channel layer 7 as a third semiconductor layer.
And the cap layer 8 are sequentially crystal-grown (FIG. 1A).
reference). These second and third channel layers 5 and 7 are made of Si-doped GaA having the same impurity concentration as that of the first channel layer 3.
The second channel layer 5 is formed to have a thickness of 70Å, and the third channel layer 7 is formed to have a thickness of 80Å.
The second spacer layer 6 is formed of the same undoped GaAs as the first spacer layer 4 and has the same thickness. The cap layer 8 is formed of the same undoped GaAs as the first and second spacer layers 4 and 6, but the thickness thereof, that is, the depth from the substrate surface to the third channel layer 7 is 400 Å. It is formed.

Next, the source and
A drain region pattern is formed on the substrate surface, and high-concentration Si ions are selectively ion-implanted using this pattern as a mask. By this selective ion implantation, the n ⁺ type drain region 9 and the source region 10 are formed. Next, the gate electrode 11 is formed by using a vapor deposition technique, a lithography technique, an etching technique, etc. (see FIG. 2B). The gate electrode 11 is formed at a position away from the drain region 9.

Finally, the same vapor deposition technique, lithography technique, etc. are used to form the drain region 9 and the source region 10.
A drain electrode 12 and a source electrode 13 which are in ohmic contact with the are formed. By this electrode formation, a Schottky contact type FET (MESFET) is completed (see FIG. 2C).

The impurity profile under the gate electrode 11 in this embodiment has the structure shown in the graph of FIG. The horizontal axis of the graph represents the depth d [μm] from the substrate surface, and the vertical axis represents the concentration N _D [cm ⁻³ ] of the n-type Si impurity. In this impurity profile, the impurity concentration is locally increased in a pulse shape. The pulse-like portion on the substrate surface side has a profile corresponding to the third channel layer 7 containing a high concentration of impurities, and the pulse-like portion adjacent thereto has the second channel layer 5 also containing a high concentration of impurities,
Further, the pulse-like portion in the deep portion of the substrate has a profile corresponding to the first channel layer 3.

In the FET according to the present embodiment, even if a surface depletion layer is generated due to the interface state of the substrate surface on the drain electrode 12 side, the extension of the surface depletion layer to the deepest part of the substrate is the most. Is blocked by the third channel layer 7 located on the surface side of the. In addition, the third channel layer 7
The second and first channel layers 5, 3 are provided at the deeper substrate position. Therefore, even if the electrons traveling in the third channel layer 7 are blocked by the surface depletion layer, the amount of channel electrons is sufficiently secured by the impurities present in the second and first channel layers 5 and 3 at a high concentration. To be done.

That is, when a low electric field is applied between the drain and the source, a part of a large amount of electrons generated in each of the plurality of channel layers 5 and 3 is partially undoped in the second and the second undoped layers having excellent electron transport characteristics. There is a high probability that they exist in each of the spacer layers 6 and 4 of No. 1 and the buffer layer 2. Therefore, many electrons travel at high speed between the drain and the source without being affected by the impurity scattering. Further, when a high electric field is applied between the drain and the source, more electrons forming a channel obtain energy, and each undoped spacer having excellent electron transporting properties sandwiching each of the plurality of channel layers 5, 3 is provided. Jump out to layers 6, 4 and buffer layer 2. Therefore, again, a large amount of electrons travel between the drain and the source without being affected by the impurity scattering. As a result, as compared with the conventional FET in which only two channel layers are formed, the ratio of carriers existing in each of the spacer layers 6 and 4 having excellent electron transport characteristics and the buffer layer 2 is increased, and the output current is increased on the surface. It is kept sufficiently high without being affected by the depletion layer. Therefore, the problem that the output is lowered unlike the conventional case does not occur.

Next, the pulse-doped structure FET according to the present embodiment in which the channel layer is formed by providing three semiconductor layers thinned by containing impurities at a high concentration, and only one semiconductor layer is formed in the channel layer. The following is a comparison of the characteristics with the conventional pulse-doped structure FET which is not formed.

Here, the conventional pulse-doped structure FET has the sectional structure shown in FIG. That is, an undoped GaAs buffer layer 22 having a p ⁻ type background conductivity is formed on the semi-insulating GaAs semiconductor substrate 21, and a channel layer 23 containing a high concentration of Si impurities is formed on the buffer layer 22. ing. The Si impurity concentration of this channel layer 23 is 3 × 10 ¹⁸ [cm ⁻³ ] and its thickness is 230 Å. Furthermore, a cap layer 24 made of undoped GaAs having a background conductivity of n ⁻ type is formed on the channel layer 23 with a thickness of 400 Å. Further, an n ⁺ type drain region 25 and a source region 26 are formed with the channel layer 23 sandwiched therebetween, and the gate electrode 27 makes Schottky contact with the cap layer 24 and makes ohmic contact with the drain and source regions 25, 26. Drain and source electrodes 28 and 29 are formed.

The graph shown in FIG. 4 shows the characteristics of the FET having the gate length of 0.7 μm and the gate width of 20 μm according to the present embodiment, and the graph shown in FIG. 5 shows the conventional gate length of 0.7 μm and the gate shown in FIG. The characteristics of the FET having a width of 20 μm are shown. The horizontal axis of each graph shows the gate voltage V _G [V], which is 0.5000 [V] / div. Is graduated. The vertical axis of each graph is the drain current I _D [mA]
And the transconductance g _m [mS] is shown.
The vertical axis shown on the left of each graph shows the drain current I _D corresponding to the characteristic line A, which is 1.000 [mA] / di.
v. Is graduated. The vertical axis shown on the right of each graph shows the mutual conductance g _m corresponding to the characteristic line B, which is 25.00 [mS] / div. Is graduated.

The characteristic line A in each graph is the gate voltage V
The change of the drain current I _D with respect to the change of _G is shown, and the characteristic line B shows the change of the mutual conductance g _m with respect to the change of the gate voltage V _G. From the characteristic lines A of these graphs, the drain current I _D when the gate voltage V _G is 0 [V] is the FET according to this embodiment shown in FIG.
Is about 7.7 [mA], whereas conventional F shown in FIG.
It is understood that there is only about 6.7 [mA] in ET.
That is, in the FET according to this embodiment, a high current output is obtained, and a high output FET is provided.

From the characteristic line B of each graph, the mutual conductance g _m when the gate voltage V _G is 0 [V] is shown.
Is about 161 [m in the FET according to the present embodiment shown in FIG.
S], the conventional FET shown in FIG.
It is understood that there is only [mS]. That is, a high g _m is obtained in the FET according to this embodiment. Moreover, in the FET according to this embodiment, the g _m value is kept constant over a wider range with respect to the change in the gate voltage V _G. Accordingly, in the FET of this embodiment has improved V _G -g _m characteristic, good FET of the high-frequency characteristics can be provided.

In the description of the above embodiment, the first
Further, the third channel layers 3 and 7 are formed to have a thickness of 80 Å and the second channel layer 5 is formed to have a thickness of 70 Å, but each of these channel layers may be formed to a thickness within a range of about 50 to 150 Å. . Further, the first and second spacer layers 4 and 6 are formed to have a thickness of 50 Å. This thickness is about the spread of the electron wave function, that is, the thickness within the range of about 50 to 200 Å. It may be formed in any size. Also, the cap layer 8
Was formed to a thickness of 400 Å, it may be formed to a thickness within the range of about 300 to 500 Å. Even when each semiconductor layer is formed to have these thicknesses, the same effect as that of the above-described embodiment can be obtained.

Further, in the above description of the embodiment, the impurity concentration of each of the first, second and third channel layers 3, 5 and 7 is set to 3 × 10 ¹⁸ [cm ⁻³ ], but 1 × 10. ¹⁸
Each channel layer may be formed with an impurity concentration in the range of up to 5 × 10 ¹⁸ [cm ⁻³ ], and in this case, the same effect as that of the above-described embodiment can be obtained.

In the above description of the embodiment, the case where three semiconductor layers forming the channel layer are formed has been described. However, the number of layers is not limited to this, and if three or more layers are formed. Of course, also in this case, the same effect as that of the above-described embodiment can be obtained.

Further, although the channel layers 3, 5 and 7 are formed at equal intervals in the description of the above embodiment, only the formation position of the third channel layer 7 closest to the substrate surface from the substrate surface is changed. Thus, the influence of the surface depletion layer on the deep portion of the substrate may be removed. Also in this case, the same effect as that of the above-described embodiment is obtained.

FIG. 6 shows a FET according to the second embodiment of the present invention.
It is a cross-sectional view showing the structure of.

On the semi-insulating GaAs semiconductor substrate 31,
An undoped GaAs buffer layer 32 having a background conductivity set to p ⁻ type is crystal-grown. On this buffer layer 32, a first channel layer 33 serving as a first semiconductor layer, a first spacer layer 34, a second channel layer 34 serving as a second semiconductor layer, and a second spacer layer 36 are crystallized. Is growing. The first channel layer 33 and the second channel layer 35 are formed of GaAs that is heavily doped with Si ions, which are n-type impurities, and the impurity concentration is as high as 4 × 10 ¹⁸ [cm ⁻³ ]. It is set to concentration. The impurity concentration of the channel layers 33 and 35 is set in the range of 1 × 10 ^{18 to} 5 × 10 ¹⁸ [cm ⁻³ ]. In addition, the first and second channel layers 33,
The thickness of 35 is thinned to 80Å. Each of the first and second spacer layers 34 and 36 is made of undoped GaAs having a background conductivity of n ⁻ type, and the impurity concentration thereof is set to 1 × 10 ¹⁵ [cm ⁻³ ] or less. The thickness of the first spacer layer 34 is set to 50Å, and the thickness of the second spacer layer 36 is set to 150Å.

A doping layer 37 containing n-type Si ions as an impurity is formed on the second spacer 36.
The impurity concentration and the thickness of the doping layer 37 are such that the surface depletion layer does not spread to the first and second channel layers 33 and 35, and the predetermined impurity concentration and the predetermined thickness, for example, the impurity concentration is 4 × 10. It has a thickness of 50 Å at ¹⁸ [cm ^-3 ]. The impurity concentration of the doping layer 37 is set in the range of 1 × 10 ^{18 to} 5 × 10 ¹⁸ [cm ⁻³ ] and the thickness thereof is formed to be several 10 to 100 Å. Further, a cap layer 38 is formed on the doping layer 37. The cap layer 38 is made of undoped GaAs having a background conductivity of n ⁻ type, and its impurity concentration is 1 × 10 ¹⁵ [cm ^−3. ] It is set below.

Further, an n ⁺ type drain region 39 and a source region 40, which are heavily doped with Si ions, are formed so as to overlap the respective channel layers 33, 35 and the doping layer 37. The gate electrode 41 is formed in ohmic contact with the cap layer 38, and the drain electrode 42 and the source electrode 43 are formed in ohmic contact with the drain region 39 and the source region 40.

In the FET according to the second embodiment, a surface depletion layer is generated due to the interface state of the substrate surface on the side of the drain electrode 42, and even if the surface depletion layer tries to extend to the deep portion of the substrate, The extension is blocked because the doping layer 37 is formed to have a predetermined impurity concentration and thickness as described above. In addition, at the substrate position deeper than the doping layer 37, the second and first channel layers 35, 3 are formed.
3 is provided. Therefore, the amount of electrons forming the current channel is sufficiently secured by the impurities present in the second and first channel layers 35 and 33, and the second and excellent electron transporting characteristics sandwiching the channel layers 35 and 33 are provided. First
The probability that carriers exist in each of the spacer layers 36 and 34 is high. Therefore, also in this embodiment, the output current is maintained sufficiently high without being affected by the surface depletion layer. Further, since the doping layer 37 is depleted by the surface depletion layer, the insulation property between the gate and the drain is not lowered, and the drain breakdown voltage is improved.

Although the semiconductor substrates 1 and 31 are made of GaAs in the description of the above embodiments,
For example, InP and In are not limited to this.
A semiconductor substrate such as GaAs may be used. Although Si is used as the n-type impurity, it may be Se, S, or the like. Even if the FET is formed by using such a material, the same effect as that of each of the above-described embodiments can be obtained.

In the above description of the embodiments, the case where two semiconductor layers forming the channel layer are formed has been described, but the number of layers is not limited to this, and three or more layers may be formed. Of course, also in this case, the same effect as that of the above-described embodiment can be obtained.

FIG. 7 shows an FET according to the third embodiment of the present invention.
9 is a cross-sectional view showing the structure of FIG. 8, and this FET is manufactured according to the process cross-sectional view shown in FIG. This manufacturing method will be described below.

On the semi-insulating GaAs semiconductor substrate 51, M
Each semiconductor layer described below is sequentially deposited using a crystal growth technique such as a BE (Molecular Beam Epitaxy) method or an OMVPE (Organic Metal Vapor Phase Epitaxial) method. First, Ga
The GaAs buffer layer 52 is crystal-grown on the As semiconductor substrate 51 (see FIG. 8A). The buffer layer 52 contains a p-type impurity in the order of 1 × 10 ¹⁶ [cm ⁻³ ] but can be suppressed to a low impurity concentration of 1 × 10 ¹⁷ [cm ⁻³ ] or less at the highest.

Next, Si-doped Ga is formed on the buffer layer 52.
The As layer is crystal-grown to form the first channel layer 53 as the first semiconductor layer. This first channel layer 5
3 is 3-5 × 10 ¹⁸ [cm] of Si ions which are n-type impurities
^-3 ] or 1 to 5 x 10 ¹⁸ [cm ^-3 ] in a high concentration, and the thickness is reduced to 50 to 100Å. Subsequently, an undoped intermediate concentration layer 54 is crystal-grown to a thickness of about 100 to 500 Å on the first channel layer 53 (see FIG. 2B). Since the intermediate concentration layer 54 is formed undoped, the impurity concentration is still extremely low.

Next, a Si-doped GaAs layer is crystal-grown on the intermediate concentration layer 54 to form a second channel layer 55 as a second semiconductor layer. The second channel layer 55 contains Si impurities in a high concentration as high as that of the first channel layer 53, and the thickness thereof is also the first channel layer 53.
It is as thin as Then, an undoped GaAs layer is crystal-grown on the second channel layer 55 to form a cap layer 56. The impurity concentration of the cap layer 56 is set to be as low as that of the buffer layer 52 (see FIG. 7C).

Next, the source and
A drain region pattern is formed on the substrate surface, and high-concentration Si ions are selectively ion-implanted using this pattern as a mask. By this selective ion implantation, an n ⁺ type drain region 58 and a source region 59 are formed. Next, the epitaxial wafer having such a laminated structure is annealed at 800 to 900 ° C. for 1 to 10 seconds. After that, the gate electrode 57 is formed by using the vapor deposition technique, the lithography technique, the etching technique and the like (see FIG. 3D). The gate electrode 57 is the drain region 5
It is formed at a position away from 8.

Finally, the same vapor deposition technique or lithographic technique is used, and the drain region 58 and the source region 5 are
A drain electrode 60 and a source electrode 61 which are in ohmic contact with the electrode 9 are formed. By this electrode formation, the Schottky contact type FET (MESFET) having the structure shown in FIG. 7 is completed.

In this embodiment, since the above-mentioned annealing treatment is performed after crystal growth of the layers 52 to 56,
The impurity profile below the gate electrode 57 where the current channel is formed has the configuration shown in the graph of FIG.
The horizontal axis of the graph represents the depth d [Angstrom] from the substrate surface, and the vertical axis represents the concentration N _D [cm] of the n-type Si impurity.
^-3 ]. Further, the impurity profile A shown by the solid line shows the profile after the annealing treatment, and the impurity profile B shown by the dotted line shows the profile before the annealing treatment. In the profile B before annealing, the pulse-shaped impurity concentration is high, and the pulse-shaped portion on the substrate surface side corresponds to the second channel layer 55 containing impurities in a high concentration, and the pulse-shaped portion on the deep side of the substrate. Also corresponds to the first channel layer 53 containing impurities at a high concentration. By performing annealing treatment on the laminated structure having such an impurity profile, each channel layer 5
Si ions contained in high concentration in 3, 55 diffuse into the buffer layer 52, the intermediate concentration layer 54, and the cap layer 56 sandwiching the channel layers 53, 55. Therefore, the impurity profile shape under the gate electrode becomes a mountain shape slightly deviated from the stepwise pulse shape, and the impurity profile A shown in the figure.
become.

That is, the undoped intermediate-concentration layer 54 formed between the channel layers 53 and 55.
Will contain impurities at a concentration of about 1 × 10 ¹⁷ [cm ⁻³ ]. The impurity concentration of the intermediate concentration layer 54 is 3 to 5 × 10 ¹⁸ [cm ⁻³ ] or 1 to 5 × 10 ¹⁸ [c ³ ] of the impurity concentration of the first channel layer 53 and the second channel layer 55.
m ^-3 ]. In addition, each channel layer 5
Impurities contained in the respective channel layers 53, 55 are diffused also into the buffer layer 52 and the cap layer 56 sandwiching the outermost layers 3, 55, and the respective channel layers 53, 55 are also in contact with the channel layers of these outermost layers. The impurities are contained at a concentration lower than the impurity concentration of.

Therefore, in the MESFET according to this embodiment having such a structure, the channel layers 53 and 55 are formed.
Since the buffer layer 52, the intermediate concentration layer 54, and the cap layer 56 sandwiching the layer 5 contain impurities at a low concentration, each of these layers 5
Channel electrons are also generated by Si impurities existing at 2, 54 and 56. Therefore, the electrons that form the current channel are generated in each channel layer 5 in the low electric field region, that is, in the source side where the electric field lower than that in the drain side is formed.
It is distributed in each layer 52, 54 and 56 sandwiching 3, 55.
For this reason, the channel electrons also travel in these layers 52, 54 and 56, which have a lower impurity concentration than the channel layers 53 and 55, and the influence of impurity scattering is reduced. As a result, the electron mobility in the low electric field region on the source side is improved.

On the side of the drain where a high electric field is formed, the electrons traveling in the channel layers 53 and 55 obtain energy from the high electric field and are present in a higher energy level. Therefore, the channel electrons jump out from the channel layers 53 and 55 containing impurities at a high concentration, and the buffer layer 5 having a low impurity concentration sandwiching the channel layers 53 and 55.
2. Traveling through the intermediate concentration layer 54 and the cap layer 56. For this reason, even in the high electric field region on the drain side, the influence of channel scattering from the impurity scattering is small, and the electron saturation speed does not decrease.

Therefore, according to the FET of this embodiment,
The electron mobility is high over the entire channel from the source side to the drain side. Also, the electron saturation speed does not deteriorate.
Therefore, the high frequency characteristics of the element are improved. In addition, FET
The transconductance g _{m of the above} is maintained at a constant value over a constant change of the gate voltage, and the change of the mutual conductance g _m with respect to the change of the gate voltage shows a flat characteristic.

In the description of the third embodiment, the intermediate concentration layer 54 is formed by diffusing the impurities in the channel layers 53 and 55 into the undoped semiconductor layer by the annealing process. The intermediate concentration layer 54 may be formed as described above. That is, it is also possible to form an intermediate concentration layer containing an appropriate amount of impurities by controlling the concentration of impurities contained in the raw material when crystal-growing each semiconductor layer deposited on the semiconductor substrate 51. Further, it is also possible to form the layers corresponding to the buffer layer and the cap layer by appropriately containing impurities as in the above embodiment.
With such a manufacturing method and structure, the same effect as that of the above-described embodiment can be obtained, the mobility of channel electrons is increased, and the electron saturation speed is also maintained high.

In the description of the third embodiment, the semiconductor substrate 51 is made of GaAs, but the invention is not limited to this. For example, InP or InG.
A semiconductor substrate such as aAs may be used. Although Si is used as the n-type impurity, it may be Se, S, or the like. Even if the FET is formed by using such a material, the same effect as that of the above-mentioned embodiment can be obtained.

In the description of each of the above embodiments, the gate electrodes 11, 41, 57 are the drain electrodes 12, 42,
Although the FET has been described in which it is formed away from 60 and the withstand voltage characteristic between the gate and the drain is improved, the present invention is not limited to this. That is, an FET having a structure in which the gate electrode is formed in the center between the drain and the source,
Each of the above embodiments may be applied to an FET or the like having a structure in which the gate electrode is formed in the recess, and the same effect as each of the above embodiments can be obtained.

[0053]

As described above, according to the present invention, the extension of the surface depletion layer from the substrate surface to the deep portion is blocked by the semiconductor layer located closest to the substrate surface. Alternatively, it is blocked by a doping layer provided on the channel layer. Further, a plurality of semiconductor layers are provided on the semiconductor substrate that is deeper than the semiconductor layer or the doping layer located closest to the substrate surface side. Therefore, the amount of electrons forming the current channel is sufficiently secured by the plurality of semiconductor layers forming the channel layer. Therefore, the output current is maintained sufficiently high without being affected by the surface depletion layer, and a high-output and high-speed operation FET is provided.

Further, since the intermediate concentration layer between the plurality of semiconductor layers contains impurities at a low concentration, channel electrons are also generated by the impurities present in the intermediate concentration layer. Therefore, the electrons forming the current channel are distributed in the intermediate concentration layer between the semiconductor layers even in the low electric field region, and travel in the intermediate concentration layer having a lower impurity concentration than the semiconductor layer forming the channel. Therefore, the mobility of channel electrons in the low electric field region is high, the electron saturation speed is also kept high, and the high frequency characteristics of the device are improved. Further, the mutual conductance g _{m is} also maintained at a constant value over a constant gate voltage change.

When heat treatment is applied to form the intermediate concentration layer, impurities are contained in a low concentration in each layer sandwiching the plurality of semiconductor layers on the outermost side, and channel electrons are contained in both outermost layers. Will also be distributed. Therefore, the channel electrons travel in both outermost layers having a low impurity concentration in addition to the intermediate concentration layer. Therefore, the mobility of channel electrons in the low electric field region is further increased, and the high frequency characteristics of the device are further improved.

[Brief description of drawings]

FIG. 1 is a process sectional view showing a manufacturing process of an FET according to a first embodiment of the present invention.

FIG. 2 is a graph showing an impurity profile under the gate electrode of the FET according to the first embodiment.

FIG. 3 is a cross-sectional view showing a conventional FET having a single channel structure, which is compared with the FET according to the first embodiment to show the effectiveness of the FET.

FIG. 4 is a graph showing characteristics of the FET according to the first embodiment shown in FIG.

FIG. 5 is a graph showing characteristics of the conventional FET shown in FIG.

FIG. 6 is a sectional view showing a structure of an FET according to a second embodiment of the present invention.

FIG. 7 is a sectional view showing the structure of an FET according to a third embodiment of the present invention.

FIG. 8 is a process cross-sectional view showing the method of manufacturing the FET according to the third embodiment shown in FIG.

FIG. 9 is a graph showing an impurity profile under the gate electrode of the FET according to the third embodiment.

[Explanation of symbols]

1, 31, 51 ... Semi-insulating GaAs semiconductor substrate, 2, 3
2, 52 ... Buffer layer, 3, 33, 53 ... First channel layer (semiconductor layer), 4, 34 ... First spacer layer, 5,
35, 55 ... Second channel layer (semiconductor layer), 6, 36
... Second spacer layer, 7 ... Third channel layer (semiconductor layer), 8,38,56 ... Cap layer, 9,39,58 ...
Drain region, 10, 40, 59 ... Source region, 11,
41, 57 ... Gate electrode, 12, 42, 60 ... Drain electrode, 13, 43, 61 ... Source electrode, 54 ... Intermediate concentration layer.

 ─────────────────────────────────────────────────── ─── Continuation of the front page (72) Inventor Shigeru Nakajima 1 Taya-cho, Sakae-ku, Yokohama-shi, Kanagawa Sumitomo Electric Industries, Ltd. Yokohama Works (72) Noboru Kuwata, No. 1 Taya-cho, Sakae-ku, Yokohama-shi, Kanagawa Sumitomo Denki Kogyo Co., Ltd. Yokohama Works (72) Inventor Kenji Otobe 1 Taya-cho, Sakae-ku, Yokohama, Kanagawa Sumitomo Denki Kogyo Co., Ltd. Yokohama Works

Claims (7)

[Claims] 1. A field effect transistor comprising a semiconductor layer thinned by containing impurities at a high concentration as a channel layer, wherein the channel layer is formed of three or more semiconductor layers with an undoped layer sandwiched therebetween. Field effect transistor characterized by. 2. A field effect transistor comprising a semiconductor layer thinned by containing impurities at a high concentration as a channel layer, wherein a plurality of said semiconductor layers are formed with an undoped layer sandwiched between said channel layers. A doping layer is formed on top of the semiconductor layer located closest to the substrate surface with an undoped layer in between, and the impurity concentration and thickness of this doping layer are determined so that the surface depletion layer does not spread to the channel layer. And a field effect transistor having a predetermined thickness. 3. A field effect transistor having a channel layer of a semiconductor layer thinned by containing impurities at a high concentration, wherein a plurality of the semiconductor layers forming the channel layer are formed, and these semiconductor layers are provided between these semiconductor layers. A field-effect transistor characterized in that an intermediate concentration layer containing impurities at a lower concentration than that of each semiconductor layer is formed. 4. The field effect transistor according to claim 3, wherein the intermediate concentration layer is formed by diffusing impurities of the respective semiconductor layers forming the channel layer into an undoped layer by heat treatment. 5. The field effect transistor according to claim 3, wherein the intermediate concentration layer is formed by crystal growth with controlled impurity concentration. 6. A step of forming an undoped layer, a step of forming a thin semiconductor layer containing impurities at a high concentration on the undoped layer, a step of forming the undoped layer and the semiconductor layer Forming the channel layer by repeating the forming step to form a plurality of the semiconductor layers, and performing heat treatment after these steps to diffuse impurities contained in the semiconductor layers into the undoped layers to form the intermediate concentration. A method of manufacturing a field effect transistor, comprising: forming a layer; and manufacturing the field effect transistor according to claim 4. 7. A step of forming a thin semiconductor layer containing a high concentration of impurities, and a low concentration of impurities as compared with the impurity concentration of the semiconductor layer by crystal growth with a controlled impurity concentration. 6. A step of forming an intermediate concentration layer, a step of forming the semiconductor layer and a step of forming the channel layer by repeating the step of forming the semiconductor layer and the step of forming the intermediate concentration layer, A method of manufacturing a field effect transistor, comprising manufacturing the field effect transistor according to claim 1.