JPH0992660A - Field-effect transistor and manufacturing method - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a Schottky junction field-effect transistor with a good gate breakdown voltage. SOLUTION: A non-doped GaAs layer 12 as a buffer layer, a first n-type conductive GaAs layer 13 as a channel layer, a non-doped AlGaAs layer 14 for improving gate breakdown voltage, and source and drain regions 15a and 15b made of n-type conductive GaAs layer are formed on a GaAs semi-insulation substrate 11. A source electrode 18 is formed selectively on the source region 15a, while a drain electrode 19 is formed selectively on the drain region 15b. These electrodes 18 and 19 are put in ohmic contact. In addition, an AlGaAs region 14a including aluminum oxide is formed near an interface of the Schottky junction of a gate electrode 20 on the non-doped AlGaAs layer 14.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a field effect transistor having a high gate breakdown voltage and a method for manufacturing the same.

[0002]

2. Description of the Related Art Generally, when an oxide film is formed on a compound semiconductor substrate using GaAs, it is difficult to form a MOS structure because an interface level is formed at the boundary between the formed oxide film and the semiconductor substrate. Such a compound semiconductor substrate is used as a Schottky junction field effect transistor in which on / off of current is controlled by a Schottky junction type gate electrode.

A conventional Schottky junction field effect transistor will be described below with reference to the drawings.

FIG. 21 is a sectional view of a conventional GaAs Schottky junction field effect transistor. In FIG. 21, 101 is a semi-insulating substrate made of GaAs, 102 is a non-doped buffer layer made of GaAs, 103 is an n-type channel layer, 105 is an n ⁺ source region having a higher impurity concentration than the n-type channel layer 103, and 106 is n ⁺ drain region having an impurity concentration higher than that of the n-type channel layer 103, 10
Reference numeral 7 designates a source electrode serving as a carrier for supplying electrons serving as carriers.
Reference numeral 08 denotes a drain electrode serving as a carrier extraction port, 11
Reference numeral 0 is a gate electrode for applying a voltage for controlling carriers flowing in the n-type channel layer 103, and the gate electrode 1
Reference numeral 10 is in Schottky junction with the n-type channel layer 103 to form a depletion layer in the channel.

In the Schottky junction field effect transistor, an appropriate voltage is applied to the gate electrode 110 and the spread of the depletion layer is changed to change the width of the n-type channel layer 10.
The current flowing through 3 is controlled.

[0006]

However, the conventional Schottky junction field effect transistor has a problem that the gate breakdown voltage is lower than that of the MOS field effect transistor.

Since the MOS field effect transistor is insulated by having an insulating film between the gate electrode and the semiconductor substrate on which the gate electrode is formed, the current leaking from the gate electrode is extremely small. In the Schottky junction field effect transistor, it is considered that the leak current increases depending on the carrier density and temperature at the junction interface because the gate electrode is not insulated from the substrate.

For example, when impact ions are generated in the vicinity of the gate electrode 110, a large amount of generated carriers are injected into the gate electrode 110, so that the gate leak current increases. In addition to this, factors such as tunnel current may be considered.

An object of the present invention is to solve the above conventional problems and improve the gate breakdown voltage characteristics.

[0010]

In order to achieve the above object, the present invention is to form a region containing a metal oxide serving as an insulator in the vicinity of a gate electrode junction.

Specifically, a solution means taken by the invention of claim 1 is a field effect transistor having a channel region, a source region and a drain region formed in a semiconductor substrate and having a gate electrode which forms a Schottky junction with the semiconductor substrate. A region containing a metal oxide is formed in a portion in the vicinity of the gate electrode in at least one region of the channel region, the source region and the drain region.

With the above structure, even if a high voltage is applied to the gate electrode, the interface between the gate electrode and the channel region, the interface between the channel region and the source region, the interface between the channel region and the drain region, and the source electrode Since a region containing a metal oxide, which is an insulator, is formed in the vicinity of at least one of the interface with the source region and the interface between the drain electrode and the drain region, carrier density in the vicinity of the gate electrode is increased. Hard to do.

According to a second aspect of the present invention, in the structure of the first aspect, a first carrier supply layer is formed on the semiconductor substrate, and a conductive layer is formed on the first carrier supply layer. A second carrier supply layer is formed on the conductive layer,
The gate electrode is formed on the second carrier supply layer by a Schottky junction, and the region containing the metal oxide is formed in a portion of the second carrier supply layer near the gate electrode. The configuration is as follows.

According to a third aspect of the invention, in the structure of the second aspect, the region containing the metal oxide is also formed in the first carrier supply layer.

According to the above structure, in addition to the effect produced by the structure of claim 4, since the interface between the channel region and the first carrier supply layer contains the metal oxide as an insulator, Carriers can be contained in the channel region so that they do not diffuse below the semiconductor substrate.

According to a fourth aspect of the present invention, there is provided a field effect transistor having a channel region formed in a semiconductor substrate, a semiconductor layer or a non-doped layer formed on the channel region, and having a gate electrode which forms a Schottky junction with the semiconductor substrate. As a premise, a region containing a metal oxide is formed in a portion of the semiconductor layer or the non-doped layer near the gate electrode.

With the above structure, even if a high voltage is applied to the gate electrode, a region containing a metal oxide, which is an insulator, is formed in the vicinity of the interface between the gate electrode and the semiconductor layer or non-doped layer that makes a Schottky junction therewith. Since it is formed, it is difficult for the carrier density at the interface between the gate electrode and the channel region to increase.

According to a fifth aspect of the present invention, in the structure of the fourth aspect, a conductive layer is formed on the semiconductor substrate, a non-doped layer is formed on the conductive layer, and the gate electrode is formed on the non-doped layer. And a region containing the metal oxide is formed in a portion near the gate electrode in the non-doped layer.

The invention of claim 6 is the structure of claims 1 to 5, wherein the content of the metal oxide is more than 0% and not more than 10%.

According to the above structure, the concentration of the metal oxide formed in the vicinity of the gate electrode is more than 0% and 10% or less, so that the insulating property of the metal oxide is sufficiently retained and carrier is used. It does not reduce the mobility of certain electrons.

According to a seventh aspect of the present invention, there is provided a method of manufacturing a field effect transistor, including a conductive layer forming step of forming a conductive layer on a semiconductor substrate, and a step of forming a semiconductor layer containing a metal on the conductive layer. Forming a region containing a metal oxide by selectively injecting oxygen into a portion of the semiconductor layer in the vicinity of the gate electrode formation region, and forming a gate electrode on the semiconductor layer And a gate electrode forming step.

With the above structure, even if a high voltage is applied to the gate electrode, a region containing a metal oxide, which is an insulator, is formed in the vicinity of the interface between the gate electrode and the channel region. The carrier density at the interface with and becomes difficult to increase.

According to an eighth aspect of the present invention, there is provided a method of manufacturing a field effect transistor, including a first carrier supply layer forming step of forming a first carrier supply layer containing metal on a semiconductor substrate.
A conductive layer forming step of forming a conductive layer on the first carrier supply layer, and a second carrier supply layer forming step of forming a second carrier supply layer containing a metal on the conductive layer,
A metal oxide containing region forming step of forming a region containing a metal oxide by selectively injecting oxygen into a portion of the second carrier supplying layer in the vicinity of the gate electrode forming region; and the second carrier supplying layer. And a gate electrode forming step of forming a gate electrode on the above. With the above structure, even in the double hetero field effect transistor, an insulator is formed near the interface between the gate electrode and the second carrier supply layer containing a metal that makes a Schottky junction when a high voltage is applied to the electrode. Since the region containing the metal oxide is formed, the carrier density in the vicinity of the gate electrode is unlikely to increase.

According to a ninth aspect of the present invention, there is provided a method of manufacturing a field effect transistor, including a first carrier supply layer forming step of forming a first carrier supply layer containing a metal on a semiconductor substrate.
A conductive layer forming step of forming a conductive layer on the first carrier supply layer, and a second carrier supply layer forming step of forming a second carrier supply layer containing a metal on the conductive layer,
Metal oxide-containing region that forms a region containing a metal oxide by selectively injecting oxygen into portions of the first carrier supply layer and the second carrier supply layer that sandwich the channel region formed in the conductive layer The structure includes a region forming step and a gate electrode forming step of selectively forming a gate electrode on the region containing the metal oxide in the second carrier supply layer.

With the above structure, also in the double hetero type field effect transistor, when the high voltage is applied to the electrode, the interface between the gate electrode and the second carrier supply layer containing a metal that forms a Schottky junction, Since a region containing a metal oxide, which is an insulator, is formed in the vicinity of the interface between the channel region and the source region and the interface between the channel region and the drain region, it is difficult for the carrier density near the gate electrode to increase. In addition, since a region containing a metal oxide, which is an insulator, is formed at the interface between the channel region and the first carrier supply layer, carriers in the channel region are prevented from diffusing below the semiconductor substrate. Can be contained.

According to a tenth aspect of the present invention, there is provided a method of manufacturing a field effect transistor, comprising: a conductive layer forming step of forming a conductive layer on a semiconductor substrate; and a selective oxygen in a portion of the conductive layer near a gate electrode forming region. And a metal oxide-containing region forming step of forming a region containing a metal oxide by injecting a metal, and a gate electrode forming step of forming a gate electrode on the conductive layer. is there.

With the above structure, also in the planar field effect transistor, when a high voltage is applied to the electrodes, the interface between the gate electrode and the channel region, the interface between the channel region and the source region, and the channel region and the drain are formed. Since a metal oxide that is an insulator is included near the interface with the region, the interface between one end of the source electrode and the source region, and the interface between one end of the drain electrode and the drain region, the carrier density near the gate electrode is It becomes difficult to rise.

According to the invention of claim 11, in the structure of claims 7 to 10, the step of forming the metal oxide-containing region includes a step of containing the metal oxide in an amount of more than 0% and 10% or less. To do.

With the above structure, the concentration of the metal oxide formed in the vicinity of the gate electrode is set to more than 0% and 10% or less, so that the insulating property of the metal oxide is sufficiently maintained and the carrier is maintained. Therefore, the mobility of electrons is not reduced.

[0030]

BEST MODE FOR CARRYING OUT THE INVENTION

(First Embodiment) A first embodiment of the present invention will be described below with reference to the drawings.

FIG. 1 is a sectional view of a field effect transistor according to the first embodiment of the present invention. In FIG. 1, 11
Is a GaAs semi-insulating substrate, 12 is a non-doped GaAs layer serving as a buffer layer for lattice matching with the GaAs semi-insulating substrate 11, 13 is a first n-conductivity type GaAs layer serving as a channel region, and 14 is a gate breakdown voltage. Non-doped AlGaAs layer for improving, 14a is non-doped AlGa
A containing aluminum oxide formed in the As layer 14
1 GaAs region, 15a is a source region made of the second n-conductivity type GaAs layer, 15b is a drain region made of the second n-conductivity type GaAs layer, 18 is a source electrode serving as an electron source serving as a carrier, and 19 is a carrier A drain electrode 20 serving as a take-out port is a Schottky junction gate electrode for applying a voltage for controlling carriers flowing in the channel layer.

The characteristics of the operation of the field effect transistor configured as described above will be described below. Since the AlGaAs region containing aluminum oxide as an insulator is formed below the Schottky junction interface in the gate electrode 20, even if the voltage between the gate-drain electrode or the gate-source electrode is increased, the gate electrode 20 Since it is difficult to increase the carrier density in the vicinity of the junction interface in, the gate leak current is suppressed, and a good gate breakdown voltage can be realized.

FIG. 2 is a sectional view of a field effect transistor according to a first modification of the first embodiment of the present invention. 2, the same members as those shown in FIG. 1 are designated by the same reference numerals, and only new members will be described. 16 is a source region made of an n-conductivity type GaAs layer formed by ion implantation, Reference numeral 17 is a drain region made of an n-conductivity type GaAs layer formed by ion implantation.

As shown in FIG. 1, the source region 15a and the drain region 15b are formed by mesa etching in the first embodiment. However, even if they are formed by ion implantation as shown in FIG. 1 shows the same features as the first embodiment.

(Second Embodiment) A second embodiment of the present invention will be described below with reference to the drawings.

FIG. 3 is a sectional view of a field effect transistor according to the second embodiment of the present invention. In FIG. 3, FIG.
Explaining only the members newly added to the above, 21 is a first n-conductivity type AlGaAs layer serving as a carrier supply layer, 22
Is an n-conductivity type InGaAs layer serving as a channel region, 23 is a second n-conductivity type AlGaAs layer serving as a carrier supply layer,
Reference numeral 23a is AlG containing aluminum oxide formed at the interface between the gate electrode 20 that is Schottky-junctioned and the second n-conductivity type AlGaAs layer that serves as a carrier supply layer.
It is an aAs region.

The characteristics of the operation of the field effect transistor configured as described above will be described below. The field-effect transistor shown in FIG. 3 has a channel region having a double hetero structure, and like the field-effect transistor shown in the first embodiment, an insulator is formed below the Schottky junction interface in the gate electrode 20. Al containing aluminum oxide
Since the GaAs region 23c is formed, even if the voltage between the gate-drain electrode or the gate-source electrode is increased, the carrier density in the vicinity of the junction interface in the gate electrode 20 is unlikely to increase, so that the gate leak current is suppressed. As a result, a good gate breakdown voltage can be realized.

Although the source region 15a and the drain region 15b are formed by mesa etching in the second embodiment, they are formed by the ion implantation method as in the first modification of the first embodiment. May be.

(Third Embodiment) A third embodiment of the present invention will be described below with reference to the drawings.

FIG. 4 is a sectional view of a field effect transistor according to the third embodiment of the present invention. In FIG. 4, FIG.
To explain only the members newly added to, 31a is n
A source region made of a conductive AlGaAs layer, 31b is n
A drain region 31c made of a conductive AlGaAs layer is an AlGaAs region containing aluminum oxide formed near the gate electrode in the non-doped AlGaAs layer 14, the source region 31a and the drain region 31b.

The field effect transistor shown in FIG.
The member in which the source region 31a and the drain region 31b are formed is different from the field effect transistor shown in FIG. Since oxides are easily formed in the AlGaAs shown in FIG. 4, the AlGaAs region 31 containing aluminum oxide is used.
c is not limited to the interface between the gate electrode 20 and the channel region,
Interface between source region 31a and channel region, interface between source region 31a and source electrode 18, drain region 31b
It is also formed at the interface between the channel region and the channel region and at the interface between the drain region 31b and the drain electrode 19.

The characteristics of GaAs forming the source and drain regions shown in FIG. 1 are high in reliability because the material is not likely to change because it is hard to be oxidized. Further, it has a feature that the mobility of carriers is higher than that of AlGaAs.

The operating characteristics of the field effect transistor configured as described above will be described below.

As shown in FIG. 4, an insulator made of aluminum oxide is included in the semiconductor between the gate electrode 20 and the source electrode 18 and between the gate electrode 20 and the drain electrode 19. Even when a high voltage is applied between the source electrodes, the carrier density in these portions is unlikely to increase, and the gate leak current is suppressed, so that a good gate breakdown voltage can be realized.

AlGaA containing aluminum oxide
The s region 31c is formed both between the gate electrode 20 and the source electrode 18 and between the gate electrode 20 and the drain electrode 19, but the gate electrode 20 and the source electrode 1
If the breakdown voltage between the electrodes 8 is sufficient, it may be formed only partially between the gate electrode 20 and the drain electrode 19, or may be locally formed at a place where the electric field is concentrated and the impact ionization phenomenon is likely to occur.

In the first and third embodiments, in order to improve the gate breakdown voltage, AlGaAs under the gate electrode is used.
Is non-doped, it may be of n conductivity type. In this case, characteristics such as transconductance are improved although the gate breakdown voltage is slightly inferior.

In addition, the source region 31a and the drain region 3
1b is formed by mesa type etching,
You may form by the ion implantation method as shown in FIG.

(Fourth Embodiment) A fourth embodiment of the present invention will be described below with reference to the drawings.

FIG. 5 is a sectional view of a field effect transistor according to the fourth embodiment of the present invention. In FIG. 5, FIG.
To explain only the members newly added to, 31a is n
A source region made of a conductive AlGaAs layer, 31b is n
A drain region 31c made of a conductive AlGaAs layer, and 31c is an AlGaAs region containing aluminum oxide formed near the gate electrode in the n conductive AlGaAs layer 23, the source region 31a and the drain region 31b.

The field effect transistor shown in FIG.
6 is different from the field effect transistor shown in FIG. 3 only in the member in which the source region 31a and the drain region 31b are formed, and both have a double hetero structure. As described in the third embodiment, the source region 31a and the drain region 3 formed of AlGaAs.
Since 1b easily forms an oxide, an AlGaAs region 31c containing aluminum oxide is formed in a portion where a high electric field is generated.
Can be selectively formed. Therefore, even when a high voltage is applied between the gate-drain electrodes or between the gate-source electrodes, the carrier density in the region containing aluminum oxide, which is an insulator, is more difficult to increase,
Since the gate leak current is further suppressed, a better gate breakdown voltage can be realized.

(Fifth Embodiment) Hereinafter, a fifth embodiment of the present invention will be described with reference to the drawings.

FIG. 6 is a sectional view of a field effect transistor according to the fifth embodiment of the present invention. In FIG. 6, FIG.
Explaining only the members newly added to, the reference numeral 21a indicates the first n-conductivity-type AlGaAs layer 21 serving as a carrier supply layer.
AlGa containing aluminum oxide selectively formed in
An As region 23c is an AlGaAs region containing aluminum oxide selectively formed in the second n-conductivity type AlGaAs layer 23 serving as a carrier supply layer.

The characteristics of the operation of the field effect transistor configured as described above will be described below in comparison with the operation of the field effect transistor shown in FIG. Since the AlGaAs region 23c containing aluminum oxide serving as an insulator is formed not only at the Schottky junction interface in the gate electrode 20 but also at the interface between the source region 18 and the drain region 19 and the channel region, even if the gate voltage is increased. Since the carrier density in the vicinity of the gate electrode 20 is less likely to increase, the gate leak current can be further suppressed, and a better gate breakdown voltage can be realized.

Further, since the n-conductivity type InGaAs layer 22 having a large carrier mobility serving as a channel region is sandwiched by the AlGaAs regions 21a and 23c containing aluminum oxide, electrons serving as carriers are confined in the channel. The current path is not pushed to the GaAs semi-insulating substrate 11 side, and the short channel effect can be prevented. Therefore, it is possible to prevent a decrease in threshold voltage and a decrease in transconductance, which are caused by the electrons acting as carriers being pushed to the substrate side when the short channel effect occurs and the channel becomes thicker.

(Sixth Embodiment) A sixth embodiment of the present invention will be described below with reference to the drawings.

FIG. 7 is a sectional view in order of steps showing the first half of the method for manufacturing a field effect transistor according to the sixth embodiment of the present invention, and FIG. 8 is also a field effect according to the sixth embodiment of the present invention. FIG. 9 is a step-by-step cross-sectional view showing the latter half of the method for manufacturing a transistor.

First, as shown in FIG. 7A, GaAs
A non-doped GaAs layer 12 serving as a buffer layer, a first n-conductivity type GaAs layer 13 serving as a channel, a non-doped AlGaAs layer 14 for increasing the gate breakdown voltage, a source region and a drain region are formed on the semi-insulating substrate 11 by a molecular beam epitaxy method. The second n-conductivity type GaAs layer 15 is grown in order.

Next, as shown in FIG. 7B, mesa-type etching is performed on the upper layer from the non-doped GaAs layer 12 to separate the elements, and the source electrode 18 and the drain electrode 19 are formed into a second layer. Is selectively formed on the n-conductivity type GaAs layer 15 to make ohmic contact. Then, a second n-conductivity type G is formed at a predetermined position to form a gate electrode.
Recess etching is performed on the aAs layer 15 to form a source region 15a and a drain region 15b.

Next, as shown in FIG. 8A, the non-doped AlGaAs layer 1 for Schottky junction of the gate electrode.
After masking a photoresist with a photoresist at a predetermined position above 4, ion implantation of oxygen is performed, and then heat treatment is performed to form a region 14a containing aluminum oxide which is an insulator.

Next, as shown in FIG. 8B, a region 1 containing the aluminum oxide of the non-doped AlGaAs layer 14 is formed.
The gate electrode 20 is formed on 4a by a Schottky junction.

The field effect transistor obtained in this embodiment has the same structure as the field effect transistor shown in the first embodiment, and therefore exhibits the same operating characteristics as the field effect transistor shown in FIG. By forming the region 14a containing aluminum oxide, which is an insulator, at the interface between the gate electrode 20 and the non-doped AlGaAs layer 14 which are in contact with each other, the carrier density in the vicinity of the interface is less likely to increase, so that the gate leak current is suppressed. Therefore, the gate breakdown voltage can be increased.

(Seventh Embodiment) A seventh embodiment of the present invention will be described below with reference to the drawings.

FIGS. 9A to 9C are sectional views in order of steps, showing the first half of the method for manufacturing a field effect transistor according to the seventh embodiment of the present invention, and FIGS. 10A and 10B also show the field effect according to the seventh embodiment of the present invention. FIG. 9 is a step-by-step cross-sectional view showing the latter half of the method for manufacturing a transistor.

First, as shown in FIG. 9A, GaAs
On the semi-insulating substrate 11, a non-doped GaAs layer 12 serving as a buffer layer by a molecular beam epitaxy method, a first n-conductivity type AlGaAs layer 21 serving as a carrier supply layer, an n-conductivity type InGaAs layer 22 serving as a channel, a carrier supply layer. The second n-conductivity type AlGaAs layer 23, which will become the n-conductivity type, and the n-conductivity type GaAs layer 24, which will become the source region and the drain region, are sequentially grown.

Next, as shown in FIG. 9B, mesa-type etching is performed on the upper layer from the non-doped GaAs layer 12 to separate the elements, and the source electrode 18 and the drain electrode 19 are n-conductive. It is selectively formed on the type GaAs layer 24 to make ohmic contact. After that, recess etching is performed on the n-conductivity type GaAs layer 24 at a predetermined position where the gate electrode is to be formed, and the source region 24a is formed.
And the drain region 24b is formed.

Next, as shown in FIG. 10A, a second n-conductivity type AlGaA for Schottky junction of the gate electrode is formed.
Oxygen is ion-implanted at a predetermined position on the s layer 23 using a photoresist as a mask, and then heat treatment is performed to form a region 23c containing aluminum oxide which is an insulator.

Next, as shown in FIG. 10B, the gate electrode 20 is formed by Schottky junction on the region 23c containing the aluminum oxide of the second n-conductivity type AlGaAs layer 23.

The field effect transistor obtained in this embodiment has the same structure as the field effect transistor obtained in the second embodiment shown in FIG. By forming the region 23c containing aluminum oxide, which is an insulator, at the interface between the existing gate electrode 20 and the second n-conductivity type AlGaAs layer 23, the carrier density in the vicinity of the interface becomes difficult to increase, so that the gate leakage occurs. Since the current can be suppressed, the gate breakdown voltage can be increased.

An eighth embodiment of the present invention will be described below with reference to the drawings.

FIG. 11 is a sectional view in order of steps showing the first half of the method for manufacturing a field effect transistor according to the eighth embodiment of the present invention, and FIG. 12 is also the field effect according to the eighth embodiment of the present invention. FIG. 9 is a step-by-step cross-sectional view showing the latter half of the method for manufacturing a transistor.

First, as shown in FIG. 11A, GaA
A non-doped GaAs layer 12 serving as a buffer layer, an n-conductivity type GaAs layer 24 serving as a channel, and an n-conductivity type AlGaAs layer 31 serving as a source region and a drain region are sequentially grown on the semi-insulating substrate 11 by molecular beam epitaxy. Let

Next, as shown in FIG. 11B, mesa-type etching is performed on the upper layer from the non-doped GaAs layer 12 to separate the elements, and the source electrode 18 and the drain electrode 19 are n-conductive. An ohmic contact is formed by selectively forming on the AlGaAs layer 31. Then, n-conductivity type AlG is formed at a predetermined position to form a gate electrode.
Recess etching is performed on the aAs layer 31 to form a source region 31a and a drain region 31b.

Next, as shown in FIG. 11C, the n-conductivity type AlGaAs layer 3 for Schottky junction of the gate electrode.
1 and a resist mask 3 having a pattern for exposing a predetermined portion on the drain region 31b near the channel.
5 is deposited on the non-doped GaAs layer 12, oxygen is ion-implanted, and then the resist mask 35 is removed.

Next, as shown in FIG. 12A, heat treatment is performed to form a region 31c containing aluminum oxide, which is an insulator.
To form

Next, as shown in FIG. 12B, a region 3 of the n-conductivity type AlGaAs layer 31 containing aluminum oxide.
The gate electrode 20 is formed on 1c by a Schottky junction.

A feature of this embodiment is that an insulator is formed at the interface between the gate electrode 20 and the channel region, which is in Schottky junction, the interface between the channel region and the drain region 31b, and the interface between the drain electrode 19 and the drain region 31b. By forming the region 31c containing a certain aluminum oxide, the carrier density in the vicinity of the interface is less likely to increase, so that the gate leak current can be further suppressed and the gate breakdown voltage can be further increased.

AlGaA containing aluminum oxide
Although the location where the s region 31c is formed is set between the lower portion of the gate electrode 20 and between the gate electrode 20 and the drain electrode 19, even in the location where the impact ionization phenomenon easily occurs,
If the breakdown voltage between the source electrode 18 and the gate electrode 20 is poor, the AlGaAs region 31c containing aluminum oxide may be formed between the source electrode 18 and the gate electrode 20.

A first modification of the eighth embodiment of the present invention will be described below with reference to the drawings.

FIG. 13 is a process step sectional view showing the first half of the method for manufacturing a field effect transistor according to the first modification of the eighth embodiment of the present invention, and FIG. 14 is the same as the eighth embodiment of the present invention.
FIG. 9A is a step-by-step cross-sectional view showing the latter half of the method for manufacturing the field effect transistor according to the first modification example of the embodiment.

The difference between the eighth embodiment and the first modification is that
As shown in FIG. 14A, oxygen is ion-implanted using the source electrode 18 and the drain electrode 19 formed in FIG. 13B as masks without forming the resist mask 35 shown in FIG. 11C. After that, heat treatment is performed to form a region 50 containing aluminum oxide.

A feature of this embodiment is that the source electrode 18
The region 50 containing aluminum oxide is formed in a self-aligning manner using the drain electrode 19 as a mask, and the step of forming and removing a mask pattern of photoresist can be omitted.

(Ninth Embodiment) A ninth embodiment of the present invention will be described below with reference to the drawings.

FIG. 15 is a sectional view in order of steps showing the first half of the method for manufacturing a field effect transistor according to the ninth embodiment of the present invention, and FIG. 16 is also a field effect according to the ninth embodiment of the present invention. FIG. 9 is a step-by-step cross-sectional view showing the latter half of the method for manufacturing a transistor.

First, as shown in FIG. 15A, GaA
On the s semi-insulating substrate 11, a non-doped GaAs layer 12 serving as a buffer layer by a molecular beam epitaxy method, a first n-conductivity type AlGaAs layer 21 serving as a carrier supply layer, an n-conductivity type InGaAs layer 22 serving as a channel, a source and The second n-conductivity type AlGaAs layer 23 to be the drain region is sequentially crystal-grown.

Next, as shown in FIG. 15B, mesa-type etching is performed on the upper layer from the non-doped GaAs layer 12 to separate the elements, and the source electrode 18 and the drain electrode 19 are n-conductive. It is selectively formed on the type GaAs layer 24 to make ohmic contact. Then, a second n-conductivity type AlG is formed at a predetermined position to form a gate electrode.
Recess etching is performed on the aAs layer 23 to form a source region 23a and a drain region 23b.

Next, as shown in FIG. 15C, a second n-conductivity type AlGaA for forming a Schottky junction on the gate electrode.
A resist mask 35 having a pattern for exposing a predetermined portion on the s layer 23 and the drain region 23b near the channel is deposited on the non-doped GaAs layer 12, oxygen is ion-implanted, and then the resist mask 35 is formed. Remove.

Next, as shown in FIG. 16A, a heat treatment is performed to form a region 23 containing aluminum oxide which is an insulator.
form c.

Next, as shown in FIG. 16B, the gate electrode 20 is formed by the Schottky junction on the region 23c containing the aluminum oxide of the second n-conductivity type AlGaAs layer 23.

As a feature of this embodiment, also in the field effect transistor having the channel of the double hetero structure, the source region 23a and the drain region 23b are made of AlG.
When it is formed of aAs, not only the junction portion of the gate electrode, but also the drain region 23b near the channel where a high electric field is likely to occur, the region 23 containing aluminum oxide easily
c can be formed, and the carrier density at the interface between the gate electrode 20 and the channel region and the interface between the channel region and the drain region 23b is less likely to increase, so that the gate leakage current can be further suppressed and the gate breakdown voltage can be further improved. Can be increased.

In the step shown in FIG. 15C,
By changing the mask pattern of the resist mask 35 so that the source region 23a near the channel is also exposed, the region 23c containing aluminum oxide can be formed at the interface between the channel region and the source region 23a.

A first modification of the ninth embodiment of the present invention will be described below with reference to the drawings.

FIG. 17 is a process step sectional view showing the first half of the method for manufacturing a field effect transistor according to the first modification of the ninth embodiment of the present invention, and FIG. 18 is the same as the ninth embodiment of the present invention.
FIG. 9A is a step-by-step cross-sectional view showing the latter half of the method for manufacturing the field effect transistor according to the first modification example of the embodiment.

The difference between the ninth embodiment and the first modification is that
As shown in FIG. 18A, without forming the resist mask 35 shown in FIG. 15C, oxygen is ion-implanted using the source electrode 18 and the drain electrode 19 formed in FIG. 17B as masks. After that, heat treatment is performed to form a region 50 containing aluminum oxide.

The feature of the first modification is that, like the first modification of the eighth embodiment, the region 50 containing aluminum oxide is formed in a self-aligned manner using the source electrode 18 and the drain electrode 19 as a mask. Therefore, the step of forming and removing the mask pattern of the photoresist can be omitted.

(Tenth Embodiment) The first embodiment of the present invention will be described below.
Embodiment 0 will be described with reference to the drawings.

FIG. 19 is a sectional view in order of the steps, showing a method for manufacturing a field effect transistor according to the tenth embodiment of the present invention.

First, as shown in FIG. 19A, GaA
s Si ions are implanted into the semi-insulating substrate 11 using a photoresist as a mask by ion implantation and an annealing treatment is performed to form an n-conductivity type channel layer 41, an n ⁺ conductivity type source region 42, and an n ⁺ conductivity type drain. A region 43 is formed.

Next, the source electrode 18 is selectively formed on the source region 42, and the drain electrode 19 is selectively formed on the drain region 43.

Next, as shown in FIG. 19B, oxygen and aluminum are ion-implanted between the source electrode 18 and the drain electrode 19 using a photoresist as a mask, and heat treatment is performed to obtain n ⁺ conductivity. Source region 42, n of the mold
A region 50 containing aluminum oxide is formed in the ⁺ conductivity type drain region 43 and the channel region.

Next, as shown in FIG. 19C, the gate electrode 20 is selectively formed at a predetermined position by the Schottky junction.

Aluminum oxide is formed at the position where the gate electrode 20 is formed by the Schottky junction, between the position where the gate electrode 20 is formed and the drain electrode 19, and where the gate electrode 20 is formed and the source electrode 18. However, it may be in a place where breakdown easily occurs and carrier density easily increases.

As a feature of this embodiment, also in the planar type field effect transistor in which the GaAs semi-insulating substrate 11 is doped with impurities, oxygen and aluminum, which easily forms an oxide, are ion-implanted in the vicinity of the gate electrode 20. By heat treatment, the region 50 containing aluminum oxide having an insulating property can be formed.

Therefore, even if a high voltage is applied to the gate electrode 20, the carrier density in this portion is unlikely to increase, and the gate leak current is suppressed, so that a good gate breakdown voltage can be realized.

(Eleventh Embodiment) The first embodiment of the present invention will be described below.
One embodiment will be described with reference to the drawings.

20A to 20C are sectional views in order of the processes, showing the method for manufacturing the field effect transistor according to the eleventh embodiment of the present invention.

First, on the GaAs semi-insulating substrate 11, a non-doped GaAs layer 12 serving as a buffer layer, a first n-conductivity type AlGaAs layer 21 serving as a carrier supply layer, an n-conductivity type InGaAs layer 22 serving as a channel, and carrier supply. The second n-conductivity type AlGaAs layer 23 to be the layer and the n-conductivity type GaAs layer 24 to be the source and drain regions are crystal-grown in order.

Next, as shown in FIG. 20B, an oxide film 36 is applied to the surface of the n-conductivity type GaAs layer 24, and is masked by a resist mask 35 to form a first lower layer of the channel.
N-conductivity type AlGaAs layer 21 and second upper layer of the channel
After ion-implanting oxygen into the n-conductivity type AlGaAs layer 23, heat treatment is performed. At this time, the first n-conductivity type AlGaAs layer 21 and the second n-conductivity type AlG into which oxygen is injected.
Regions 21a and 23c containing aluminum oxide are formed in the aAs layer 23, respectively. However, at this time
The carriers in the channel made of GaAs are not lost by the oxygen injection and the heat treatment.

Next, as shown in FIG. 20C, after removing the resist mask 35 and the insulating film 36, mesa-type etching is performed on the layer above the non-doped GaAs layer 12 to separate the elements. Then, the source electrode 18 and the drain electrode 19 are selectively formed on the n-conductivity type GaAs layer 24 to make ohmic contact. next,
After recess etching is performed on the n-type GaAs layer 24 to form the source region 24a and the drain region 24b, the gate electrode 20 is formed by a Schottky junction at a predetermined position between the source region 24a and the drain region 24b. .

Since the field effect transistor obtained in this embodiment has the same structure as the field effect transistor obtained in the fifth embodiment shown in FIG. 6, the gate breakdown voltage is improved and the short channel effect is prevented. it can.

Although the source region 24a and the drain region 24b are formed by mesa etching, they may be formed by ion implantation.

(Twelfth Embodiment) The first embodiment of the present invention will be described below.
The second embodiment will be described.

In all the above embodiments, the composition of aluminum to gallium in the AlGaAs semiconductor forming the channel region is limited as follows.

When the chemical formula is represented by Al _x Ga _1-x As,
The range of 0 <x ≦ 0.1 is the best.

When the composition ratio of aluminum is about 1%, aluminum oxide can be formed as a sufficient insulator, so that the gate breakdown voltage can be improved and the short channel effect can be prevented. . Moreover, since the electron mobility of AlGaAs does not decrease as the composition of aluminum decreases, the gate breakdown voltage can be improved without deteriorating the characteristics of the transistor.

[0115]

As described above, according to the field effect transistor according to the invention of claim 1 or 4, since a region containing a metal oxide as an insulator is formed in the vicinity of the gate electrode, a high electric field is generated. Since the carrier density in the region where it is likely to occur is unlikely to increase, the gate leak current is suppressed and the gate breakdown voltage is improved.

According to the field effect transistor of the second aspect of the present invention, even in the structure having the double hetero type channel structure, the region containing the metal oxide as the insulator is formed in the vicinity of the gate electrode. Therefore, the carrier density in the region where a high electric field is likely to occur is unlikely to increase, so that the gate leak current is suppressed and the gate breakdown voltage is improved.

According to the field effect transistor of the third aspect of the invention, the effect of the field effect transistor of the second aspect of the invention can be obtained, and carriers in the channel region are prevented from diffusing toward the semiconductor substrate. Since the carriers are confined in the channel region, the short channel effect is suppressed, so that it is possible to prevent the threshold voltage and the transconductance from being lowered due to the channel becoming thick when the short channel effect occurs.

According to the field effect transistor of the fifth aspect of the present invention, even if the field effect transistor has a non-doped layer for increasing the gate breakdown voltage, a region containing a metal oxide as an insulator is formed near the gate electrode. As a result, the carrier density in the region where a high electric field is likely to occur is less likely to increase, so that the gate leak current is further suppressed and the gate breakdown voltage is further improved.

According to the field effect transistor of the sixth aspect of the present invention, the effect of the field effect transistor of the first to fifth aspects of the invention can be obtained, and the insulating property of the metal oxide is sufficiently retained. Moreover, since the mobility of carriers does not decrease, the performance of the transistor is not impaired.

According to the method of manufacturing a field effect transistor according to the invention of claim 7, since the region containing the metal oxide as the insulator is formed in the vicinity of the gate electrode, the carrier density in the region where a high electric field is likely to occur increases. Since it is difficult, the gate leak current can be suppressed and the gate breakdown voltage can be improved.

According to the method of manufacturing a field effect transistor according to the eighth aspect of the present invention, even in the structure having the double hetero channel structure, a region containing a metal oxide as an insulator is provided in the vicinity of the gate electrode. Therefore, since the carrier density in the region where a high electric field is likely to occur is unlikely to increase, the gate leak current can be suppressed and the gate breakdown voltage can be improved.

According to the method of manufacturing the field effect transistor of the invention of claim 9, the effect of the method of manufacturing the field effect transistor of the invention of claim 8 can be obtained and, in addition, carriers are confined in the channel. Since the occurrence of the channel effect is suppressed, it is possible to prevent a decrease in the threshold voltage and obtain good transconductance.
According to the field-effect transistor manufacturing method of the tenth aspect of the present invention, even in a planar field-effect transistor, a region containing a metal oxide, which is an insulator, is formed in the vicinity of the gate electrode, so that a high electric field is generated Since the carrier density in the easy region does not easily increase, the gate leak current is suppressed and the gate breakdown voltage is improved.

According to the method of manufacturing a field effect transistor of the eleventh aspect of the invention, the effects of the field effect transistor of the seventh aspect of the invention can be obtained, and the insulating property of the metal oxide is sufficiently retained. In addition, since the carrier mobility is not lowered, the performance of the transistor is not impaired.

[Brief description of drawings]

FIG. 1 is a cross-sectional view of a field effect transistor according to a first embodiment of the present invention.

FIG. 2 is a cross-sectional view of a field effect transistor according to a first modification example of the first embodiment of the present invention.

FIG. 3 is a sectional view of a field effect transistor according to a second embodiment of the present invention.

FIG. 4 is a sectional view of a field effect transistor according to a third embodiment of the present invention.

FIG. 5 is a sectional view of a field effect transistor according to a fourth embodiment of the present invention.

FIG. 6 is a sectional view of a field effect transistor according to a fifth embodiment of the present invention.

7A to 7D are sectional views in order of the processes, showing the first half of a method for manufacturing a field effect transistor according to a sixth embodiment of the present invention.

FIG. 8 is a step-by-step cross-sectional view showing the latter half of the method for manufacturing a field effect transistor according to the sixth embodiment of the present invention.

9A to 9C are sectional views in order of the processes, showing the first half of a method for manufacturing a field-effect transistor according to a seventh embodiment of the present invention.

FIG. 10 is a step-by-step cross-sectional view showing the latter half of the method for manufacturing a field effect transistor according to the seventh embodiment of the present invention.

FIG. 11 is a step-by-step cross-sectional view showing the first half of the method for manufacturing a field effect transistor according to the eighth embodiment of the present invention.

FIG. 12 is a step-by-step cross-sectional view showing the latter half of the method for manufacturing a field effect transistor according to the eighth embodiment of the present invention.

FIG. 13 is a step-by-step cross-sectional view showing the first half of the method for manufacturing the field effect transistor according to the first modification of the eighth embodiment of the present invention.

FIG. 14 is a step-by-step cross-sectional view showing the latter half of the method for manufacturing a field effect transistor according to the first modification of the eighth embodiment of the present invention.

FIG. 15 is a step-by-step cross-sectional view showing the first half of the method for manufacturing a field effect transistor according to the ninth embodiment of the present invention.

FIG. 16 is a step-by-step cross-sectional view showing the latter half of the method for manufacturing a field effect transistor according to the ninth embodiment of the present invention.

FIG. 17 is a step-by-step cross-sectional view showing the first half of the method for manufacturing the field effect transistor according to the first modification of the ninth embodiment of the present invention.

FIG. 18 is a step-by-step cross-sectional view showing the latter half of the method for manufacturing a field effect transistor according to the first modification of the ninth embodiment of the present invention.

FIG. 19 is a step-by-step cross-sectional view showing the method of manufacturing the field effect transistor according to the tenth embodiment of the present invention.

FIG. 20 is a step-by-step cross-sectional view showing the method of manufacturing the field effect transistor according to the eleventh embodiment of the present invention.

FIG. 21 is a sectional view of a conventional GaAs Schottky junction field effect transistor.

[Description of Reference Signs] 11 GaAs semi-insulating substrate 12 non-doped GaAs layer 13 first n-conductivity type GaAs layer 14 non-doped AlGaAs layer 14a AlGaAs region containing aluminum oxide 15 second n-conductivity type GaAs layer 15a source region 15b drain region 16 source region 17 drain region 18 source electrode 19 drain electrode 20 gate electrode 21 first n-conductivity type AlGaAs layer 22 n-conductivity type InGaAs layer 23 second n-conductivity type AlGaAs layer 23a source region 23b drain region 23c including aluminum oxide AlGaAs region 24 n conductive type GaAs layer 24a source region 24b drain region 25 resist mask 31 n conductive type AlGaAs layer 31a source region 31b drain region 31c aluminum oxide A GaAs region 35 resist mask 36 insulating film 41 n conductivity type channel layer 42 n ⁺ conductivity type source region 43 n ⁺ conductivity type drain region 50 AlGaAs region 101 including an aluminum oxide semi-insulating substrate 102 undoped buffer layer 103 n-type channel layer 105 n ⁺ source region 106 n ⁺ drain region 107 source electrode 108 drain electrode 110 gate electrode

Claims (11)

[Claims] 1. A field effect transistor having a channel region, a source region and a drain region formed on a semiconductor substrate and having a gate electrode that forms a Schottky junction with the semiconductor substrate, wherein: A field effect transistor, wherein a region containing a metal oxide is formed in a portion of the at least one region near the gate electrode. 2. A first carrier supply layer is formed on the semiconductor substrate, a conductive layer is formed on the first carrier supply layer, and a second carrier supply layer is formed on the conductive layer. And the gate electrode is formed on the second carrier supply layer by a Schottky junction, and the region containing the metal oxide is a portion of the second carrier supply layer in the vicinity of the gate electrode. The field effect transistor according to claim 1, wherein the field effect transistor is formed in 3. The region containing the metal oxide is the first
The field effect transistor according to claim 2, wherein the field effect transistor is also formed in the carrier supply layer. 4. A channel region is formed in a semiconductor substrate,
A field effect transistor having a semiconductor layer or a non-doped layer formed on the channel region and having a gate electrode that forms a Schottky junction with the semiconductor substrate, wherein a metal is provided in a portion of the semiconductor layer or the non-doped layer near the gate electrode. A field effect transistor, wherein a region containing an oxide is formed. 5. A conductive layer is formed on the semiconductor substrate, a non-doped layer is formed on the conductive layer, and the gate electrode is formed on the non-doped layer by Schottky junction. The field effect transistor according to claim 4, wherein the region containing an oxide is formed in a portion of the non-doped layer near the gate electrode. 6. The field effect transistor according to claim 1, wherein the content of the metal oxide is more than 0% and 10% or less. 7. A conductive layer forming step of forming a conductive layer on a semiconductor substrate, a step of forming a semiconductor layer containing a metal on the conductive layer, and a step of forming a conductive layer on the conductive layer in the vicinity of a gate electrode forming region. A metal oxide containing region forming step of forming a region containing a metal oxide by selectively implanting oxygen, and a gate electrode forming step of forming a gate electrode on the semiconductor layer are provided. And a method for manufacturing a field effect transistor. 8. A first carrier supply layer forming step of forming a first carrier supply layer containing a metal on a semiconductor substrate, and a conductive layer forming step of forming a conductive layer on the first carrier supply layer. A second carrier supply layer forming step of forming a second carrier supply layer containing a metal on the conductive layer, and oxygen is selectively applied to a portion of the second carrier supply layer in the vicinity of the gate electrode forming region. A metal oxide containing region forming step of forming a region containing a metal oxide by injecting, and a gate electrode forming step of forming a gate electrode on the second carrier supply layer. Of manufacturing a field effect transistor having the same. 9. A first carrier supply layer forming step of forming a first carrier supply layer containing a metal on a semiconductor substrate, and a conductive layer forming step of forming a conductive layer on the first carrier supply layer. A second carrier supply layer forming step of forming a second carrier supply layer containing a metal on the conductive layer; and forming a second carrier supply layer on the conductive layer in the first carrier supply layer and the second carrier supply layer. A metal oxide containing region forming step of forming a region containing a metal oxide by selectively injecting oxygen into a portion sandwiching the channel region, and a region containing a metal oxide in the second carrier supply layer. And a gate electrode forming step of selectively forming a gate electrode thereon. 10. A conductive layer forming step of forming a conductive layer on a semiconductor substrate, and a region containing a metal oxide by selectively implanting oxygen and metal into a portion of the conductive layer in the vicinity of a gate electrode forming region. And a gate electrode forming step of forming a gate electrode on the conductive layer. A method of manufacturing a field effect transistor, comprising: 11. The metal oxide containing region forming step,
The method for producing a field effect transistor according to claim 7, further comprising a step of containing the metal oxide in an amount of more than 0% and 10% or less.