KR920002026B1 - Metal layer connecting method using multi-layer photolithographic technics - Google Patents

Metal layer connecting method using multi-layer photolithographic technics Download PDF

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KR920002026B1
KR920002026B1 KR1019880009160A KR880009160A KR920002026B1 KR 920002026 B1 KR920002026 B1 KR 920002026B1 KR 1019880009160 A KR1019880009160 A KR 1019880009160A KR 880009160 A KR880009160 A KR 880009160A KR 920002026 B1 KR920002026 B1 KR 920002026B1
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photoresist
layer
metal
conductor
window
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KR1019880009160A
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Korean (ko)
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KR900002409A (en
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박한수
홍정인
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삼성반도체통신 주식회사
강진구
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/283—Deposition of conductive or insulating materials for electrodes conducting electric current

Abstract

The method comprises the steps of forming a conductor (2), an undoped conductor (3), a nonconductor (4) with uneven surface and a conductor (5) on a substrate (1) sequently, coating a photoresist (6) onto the conductor and nonconductor layers (5,4) to form a first window of the photoresist on the bent portion of the nonconductor (4), etching the exposed nonconductor portion to remove the photoresist (6), coating a second photo resist (11) thereon forming a second window on the etched portion, applying a metal (12) on the whole surface of substrate and removing the second photoresist (11), thereby connecting the metal layer to other portions.

Description

다층사진공정을 이용한 금속층 연결방법Metal layer connection method using multilayer photo process

제1도는 종래의 금속층 연결방법을 나타낸 공정순서도.1 is a process flow chart showing a conventional metal layer connection method.

제2도는 이 발명의 금속층 연결방법을 나타낸 공정순서도이다.2 is a process flowchart showing the metal layer connection method of the present invention.

* 도면의 주요부분에 대한 부호의 설명* Explanation of symbols for main parts of the drawings

1 : 실리콘기판 2,3 : 도체1: Silicon substrate 2, 3: Conductor

4 : 부도체 4a,4b,4c : 두께4: insulator 4a, 4b, 4c: thickness

5 : 도체 6,11 : 포토리지스트5: conductor 6,11: photoresist

8 : 계곡 10 : 경사면8: valley 10: slope

12 : 금속12: metal

이 발명은 반도체 제조공정중 사진공정에 관한 것으로 특히, 다층 포토리지스트 및 리프트오프 공정을 사용할때 금속층을 연결시키는 방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a photographic process in a semiconductor manufacturing process, and more particularly to a method of joining a metal layer when using a multilayer photoresist and liftoff process.

반도체 공정이 진행되어 여러가지층과 패턴이 형성됨에 따라 실리콘기판위에 자연히 굴곡이 생기게 되는것으로 초고밀도 집적회로인 경우 그 굴곡의 단차가 더욱 심해진다.As the semiconductor process progresses and various layers and patterns are formed, the bending naturally occurs on the silicon substrate. In the case of an ultra-high density integrated circuit, the step difference of the bending becomes more severe.

따라서 금속중착공정을 하기전에 식각을 행하게 되면 굴곡의 차에 의하여 과도식각 및 가소식각이 발생되는 원인이 되므로 금속증착시 연결부위가 끊어지게되는 단점이 생기는 것이었다. 이를 제1도의 종래의 금속층 연결방법으로 설명하면, 제1a도에 도시한 바와같이 실리콘기판(1)상에 도핑된 도체(2) 및 도핑안된 도체(3)를 형성시키고, 그위에 두께가 다른 부도체(4)층을 일반적인 사진공정으로 형성시킨다. 그리고 이부도체(4)층위에 도체층(5)을 형성시키게 되나, 부도체(4)층이 두께(4a), (4b), (4c)가 서로 상이하여 후에 연결되는 금속(7)층이 끊어지는 원인이 된다. 즉, 제1b도에 도시된 바와같이 원한는 부분만 금속층을 형성하기위하여 포토리지스트(6)층을 마스크로하여 식각공정을 행하면 실리콘기판(1)위의 부도체(4)층만 식각되고 도체(2)위의 부도체(4)층은 식각이 안되는 부분식각 현상이 제1c도와 같이 생기게 되어 그위에 금속(7)층을 증착시키더라도 실리콘기판(1)과 도체(2)를 연결시킬 수가 있게 된다. 이 현상을 제거하기 위해 도체(2)위에 부도체(4)층을 중심으로 식각을 시키게 되면 이때에는 과도식각이 발생되어 기판상에 계곡(8)이 발생되므로 중착되는 금속(7)층은 제1d도와 같이 끊어지게 된다. 여기서 제1e도는 제1d도를 리프트오프공정을 수행하여 필요없는 부분을 제거한 상태를 도시하고 있고 제1e도는 이상태를 위에서 본 도면이다. 이 도면에서 알 수 있듯이 계곡(8)에 의하여 금속(7)층이 연결되지 못하게 된다.Therefore, if the etching is performed before the metal deposition process, excessive etching and plastic etching are caused by the difference in bending, so that the connection part is broken when the metal is deposited. Referring to the conventional metal layer connection method of FIG. 1, as shown in FIG. 1A, a doped conductor 2 and an undoped conductor 3 are formed on a silicon substrate 1, and the thicknesses thereof are different. The insulator 4 layer is formed by a general photographic process. Then, the conductor layer 5 is formed on the second conductor 4 layer, but the layer 4 of the non-conductor 4 is different from each other by the thicknesses 4a, 4b, and 4c, so that the metal 7 layers to be connected later are broken. It causes losing. That is, as shown in FIG. 1B, when the etching process is performed using the photoresist layer 6 as a mask to form only the desired portion of the metal layer, only the non-conductor 4 layer on the silicon substrate 1 is etched and the conductor 2 The non-etched partial etching phenomenon on the non-etched layer 4 is generated as shown in FIG. 1C, so that the silicon substrate 1 and the conductor 2 can be connected even when the metal 7 layer is deposited thereon. In order to eliminate this phenomenon, when the etching is performed around the insulator (4) layer on the conductor (2) at this time, the excessive etching occurs and the valleys (8) are generated on the substrate. You will break with the tiles. Here, FIG. 1E shows a state in which unnecessary parts are removed by performing a lift-off process on FIG. 1D, and FIG. 1E shows this state from above. As can be seen in this figure, the metal layer 7 is not connected by the valleys 8.

이 발명의 목적은 기판상에 굴곡의 차에 의하여 부분식각 및 과도식각이 발생되더라도 포토리지스트공정과, 리프트오프공정으로 금속층을 연결시킬 수 있는 방법을 제공하고자 하는 것이다.An object of the present invention is to provide a method for connecting a metal layer through a photoresist process and a lift-off process even if partial etching and transient etching occur due to a difference in bending on a substrate.

이 발명의 또다른 목적은 두번의 사진공정을 통해 과도식각시 발생되는 끊어짐 현상(계곡현상)을 우회하여 연결시킬 수 있는 방법을 제공하는데 있다.Still another object of the present invention is to provide a method of bypassing the breaking phenomenon (valley phenomenon) generated during excessive etching through two photographic processes.

이 발명의 특징은 반도체 소자사이를 금속으로 연결시키는 일반적인 공정에서 부도체층을 사진식각하는 공정후, 습식 식각하여 부도체층에 경사면을 형성시키는 공정과 포토리지스트를 사용하는 2차 사진공정과, 금속을 도포시키는 공정을 통하여 반도체 소자간에 금속이 우회되어 연결되게 한 것에 있다.The present invention is characterized in that after the process of photoetching the insulator layer in the general process of connecting the semiconductor elements with metal, the process of wet etching to form the inclined surface on the insulator layer, the second photo process using the photoresist, and the metal The metal is bypassed and connected between the semiconductor elements through a process of coating the film.

이하, 이 발명의 실시예를 첨부도면에 따라서 상세히 설명하면 다음과 같다.Hereinafter, an embodiment of the present invention will be described in detail with reference to the accompanying drawings.

제2도는 이 발명의 금속층 연결방법을 나타낸 공정순서도로서 (a) ∼ (c)는 제1도의 방법과 동일하다. 즉, 실리콘기판(1)상에 도핑된 도체(2) 및 도핑안된 도체(3)를 형성시키고 그위에 두께가 다른 부도체(4)층을 일반적인 사진공정으로 형성시킨다. 그리고 이 부도체(4)층 위에 도체(5)층을 형성시키게 되는 것으로 부도체(4)층에서 굴곡이 심한 두께(4a), (4b), (4c)의 차를 갖게 된다. 그후 제2b도에 도시된 바와 같이 창이 형성된 포토리지스트(6)층을 마스크로하여 식각공정을 행하면 제2c도와 같이 도체(2)위의 부도체(4)층은 식각되지 않은 부분식각이 생기게 된다. 제2c도의 패턴을 이용하여 계속적인 습식식각을 행하면 도체(2)위의 두께(5b)를 갖고 형성된 부도체(4)가 과도식각이 되어 경사면(10)이 제2d도와 같이 형성시키는 것으로 이때에 과도식각에 의하여 계곡(8)이 생기게 된다.2 is a process flowchart showing the metal layer connection method of the present invention, wherein (a) to (c) are the same as those in FIG. That is, the doped conductors 2 and the undoped conductors 3 are formed on the silicon substrate 1, and the non-conductor layers 4 having different thicknesses are formed thereon by a general photographic process. By forming the conductor 5 layer on the insulator 4 layer, the insulator 4 layer has a difference in thickness (4a), (4b), and (4c) with significant bending. Then, as shown in FIG. 2B, if the etching process is performed using the photoresist layer 6 having a window as a mask, the non-etched layer 4 on the conductor 2 as shown in FIG. 2C causes unetched partial etching. . When the continuous wet etching is performed using the pattern of FIG. 2c, the non-conductor 4 formed with the thickness 5b on the conductor 2 is overetched to form the inclined surface 10 as shown in FIG. 2d. Etching results in a valley 8.

다음 공정으로 제2e도에 도시한 바와 같이 2차 사진공정을 통하여 도포된 포토리지스트(11)의 창을 포토리지스트(6)의 창이 형성되었던 영역에 형성한다. 이때 제2g도와 같이 포토리지스트(11)의 창의 패턴크기는 포토리지스트(6)의 창의 패턴크기보다 크게 형성된다. 이후 증착(evaporation)또는 스퍼터링(sputtering)공정을 통하여 폴리실리콘, TiW, Ti, W중 하나의 금속(12)을 도포한다. 그후 포토리지스트(11)층을 제거하면 제2f도와 같이 실리콘기판(1)과 도체(2)사이에 계곡(8)이 형성되지만 제2g도 및 제2h도와 같이 금속(12)은 우회되어 연결하게 된다. 즉, 제2g도는 제2f도보다 뒤쪽 중심축으로 절단시킨 단면도이고 제2h도는 위에서 본 평면도로서 금속(7)은 계곡(8)에 의하여 서로 절단된 상태를 유지하지만 부도체(4)에 경사면(10)을 준후 2차 사진공정에 의하여 더 넓은 지역에 금속(12)을 증착시켜 금속이 우회하여 연결하게 된다. 여기서 경사면(10)을 준 것은 증착시 스텝커버리지를 향상시키기 위한 것이다.Next, as shown in FIG. 2E, the window of the photoresist 11 applied through the second photographing process is formed in the region where the window of the photoresist 6 was formed. At this time, the pattern size of the window of the photoresist 11 is larger than the pattern size of the window of the photoresist 6 as shown in FIG. 2G. Thereafter, one metal 12 of polysilicon, TiW, Ti, or W is coated through evaporation or sputtering. After removing the layer of photoresist 11, a valley 8 is formed between the silicon substrate 1 and the conductor 2 as shown in FIG. 2F, but the metal 12 is bypassed and connected as shown in FIGS. 2G and 2H. Done. That is, FIG. 2g is a cross-sectional view cut along the central axis behind FIG. 2f, and FIG. 2h is a plan view viewed from above, while the metals 7 are kept in a state of being cut from each other by the valleys 8, but the inclined surface 10 on the insulator 4 is shown. ) And then the metal 12 is deposited in a wider area by the secondary photographic process to connect the metal bypasses. The inclined surface 10 is provided to improve step coverage during deposition.

이상에서와 같이 이 발명은 리프트오프 공정을 이용하여 반도체 소자내에 금속을 연결시킬 경우 2번의 사진공정을 통해 중착되는 금속면이 더욱 큰 면적으로 도포함으로써 금속면을 우회시켜 연결시킬 수 있는 것으로, 반도체 제조공정시 원하는 소자들간에 금속을 통하여 연결시킬때 생기는 끊어짐 현상을 제거시킬 수 있어 수율을 향상시킬 수 있으며 반도체 소자의 고집적화가 용이한 장점이 있는 것이다.As described above, in the present invention, when the metal is connected to the semiconductor device using the lift-off process, the metal surface, which is deposited through the two photolithography processes, can be applied to a larger area, thereby connecting the metal surface by bypass. In the manufacturing process, it is possible to remove the breakage phenomenon when connecting through the metal between the desired elements can improve the yield and there is an advantage that the high integration of the semiconductor device is easy.

Claims (2)

실리콘 기판(1)위에 도체(2) 및 도핑안된 도체(3)를 형성시키고 그위에 두께가 서로 다른 부도체층(4)을 형성시킨 후 부도체층(4)의 소정영역에 도체층(5)을 형성시키는 일반적인 공정과, 도체층(5)과 부도체층(4)의 상부에 포토리지스트(6)를 도포한 후 두께차에 의한 굴곡이 형성된 영역에 포토리지스트의 제1창을 형성하는 1차 사진공정과, 상기 창을 통하여 노출된 영역의 부도체층(4)을 식각한 후 금속을 도포시키는 공정들로써 반도체소자 사이의 금속이 연결되는 방법에 있어서, 상기 포토리지스트(6)의 제1창을 통하여 부도체층(4)을 식각한 후 상기 포토리지스트(6)을 제거하는 공정과, 상기 형태의 기판상에 포토리지스트(11)를 도포한 후 제2창을 상기 식각된 영역상에 형성하는 사진공정과, 금속(12)을 전면에 도포시키는 공정과, 상기 포토리지스트(11)를 제거하는 공정을 포함하여 이루어지는 다층사진공정을 이용한 금속층 연결방법.After the conductors 2 and the undoped conductors 3 are formed on the silicon substrate 1, the non-conductor layers 4 having different thicknesses are formed thereon, and then the conductor layer 5 is formed in a predetermined region of the non-conductor layer 4. 1 to form a first window of the photoresist in a region in which a curvature due to a thickness difference is formed after applying the photoresist 6 to the upper part of the conductor layer 5 and the non-conductor layer 4. In the method of connecting the metals between the semiconductor devices by the difference photographing process and the process of etching the non-conductive layer 4 of the region exposed through the window and then applying a metal, the first of the photoresist 6 Removing the photoresist 6 after etching the insulator layer 4 through the window; applying the photoresist 11 onto the substrate of the form; A photo process to be formed on the surface, a process of applying the metal 12 to the entire surface, and the photoresist 11 Metal layer connection method using a multilayer photographic process comprising a step of removing. 제1항에 있어서, 포토리지스트(11)의 제2창은 포토리지스트(6)의 제1창의 패턴 크기보다 큰 패턴이 형성되게 하는 다층 사진공정을 이용한 금속층 연결방법.The method of claim 1, wherein the second window of the photoresist (11) has a pattern larger than the pattern size of the first window of the photoresist (6).
KR1019880009160A 1988-07-21 1988-07-21 Metal layer connecting method using multi-layer photolithographic technics KR920002026B1 (en)

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