GB2194386A - Solder bonded integrated circuit devices - Google Patents

Solder bonded integrated circuit devices Download PDF

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Publication number
GB2194386A
GB2194386A GB08620287A GB8620287A GB2194386A GB 2194386 A GB2194386 A GB 2194386A GB 08620287 A GB08620287 A GB 08620287A GB 8620287 A GB8620287 A GB 8620287A GB 2194386 A GB2194386 A GB 2194386A
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United Kingdom
Prior art keywords
solder
integrated circuit
area
metallisation
photoresist material
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Granted
Application number
GB08620287A
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GB2194386B (en
GB8620287D0 (en
Inventor
David John Pedder
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Plessey Co Ltd
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Plessey Co Ltd
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Priority to GB8620287A priority Critical patent/GB2194386B/en
Publication of GB8620287D0 publication Critical patent/GB8620287D0/en
Publication of GB2194386A publication Critical patent/GB2194386A/en
Application granted granted Critical
Publication of GB2194386B publication Critical patent/GB2194386B/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

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Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/11—Manufacturing methods
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76897—Formation of self-aligned vias or contact plugs, i.e. involving a lithographically uncritical step
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/11—Manufacturing methods
    • H01L2224/1147—Manufacturing methods using a lift-off mask
    • H01L2224/11472—Profile of the lift-off mask
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13099—Material
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01006—Carbon [C]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01022—Titanium [Ti]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01024—Chromium [Cr]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01027—Cobalt [Co]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01029—Copper [Cu]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01033—Arsenic [As]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01078—Platinum [Pt]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01079—Gold [Au]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01082—Lead [Pb]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/013—Alloys
    • H01L2924/0132—Binary Alloys
    • H01L2924/01322—Eutectic Alloys, i.e. obtained by a liquid transforming into two solid phases
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/013—Alloys
    • H01L2924/014—Solder alloys
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/12—Passive devices, e.g. 2 terminal devices
    • H01L2924/1203—Rectifying Diode
    • H01L2924/12033—Gunn diode
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/14—Integrated circuits
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/10—Apparatus or processes for manufacturing printed circuits in which conductive material is applied to the insulating support in such a manner as to form the desired conductive pattern
    • H05K3/14—Apparatus or processes for manufacturing printed circuits in which conductive material is applied to the insulating support in such a manner as to form the desired conductive pattern using spraying techniques to apply the conductive material, e.g. vapour evaporation
    • H05K3/143—Masks therefor

Abstract

A method of manufacturing a solder bonded integrated circuit device comprising providing a substrate surface, pressure bonding an area of a dry film photoresist material 2 to said surface, exposing a selected area of the photoresist material 2 to light and developing to provide an opening for receiving a metallisation area. A metal film 6, 7 is vacuum deposited and unwanted areas 6 of this film are then removed by a solvent washing stage. A solder mass is applied to the resulting metallisation area, the volume deposited may be such as to give a good solder bump and bond height. The technique may be applied to flip chip solder bonding. <IMAGE>

Description

SPECIFICATION Solder bonded integrated circuit devices This invention relates to solder bonded integrated circuit devices.
In the manufacture of solder bonded integrated circuits and related devices using a flip chip technique, it is known to employ a variety of multilayer thin film metallisation materials that are wettable by molten solder.
Some of these metallisation materials are cobalt/copper/gold, nickel/gold, and titanium/platinum/gold and suitable solder compositions are the eutectic composition tin/lead alloy or a 95 weight percent lead/five percent tin solder composition. The method uses a defined area of a solderable metallisation material on an otherwise non-solderable silicon dioxide or polyimide dielectric surface of an integrated circuit chip, together with the application of a defined volume of solder onto each area of metallisation. This combination provides a 'controlled collapse' solder bond between the flip chip device and a corresponding defined solderable metallisation area on the substrate to which the chip is bonded.
The geometry of this 'controlled collapse' bond is defined by the surface tension of the liquid solder volume during bond formation, the mass of the flip chip device acting on each solder bond, and by the geometry of the wettable metallisation area and the volume of solder applied to each bond site. The various layers in the thin film metallisation zones are calculated to provide, in seguence: adhesion to the bond site surface (which may require, for example, a titanium or chromium metal layer), solderability without excessive or complete dissolution of the film material into the molten solder during bonding (for example, a nickel, platinum or a chromium/copper metal alloy layer) and corrosion and tarnish prevention with complete solder solubility (a gold layer).The solder composition employed is selected for its wetting behaviour and its melting temperature range, the 95 weight percent lead/five percent tin solder composition (melting point about 312 C.) being widely employed in flip chip solder bonding of silicon integrated circuit devices.
In the past, it has been proposed that the localised, defined, wettable metallisation areas should be provided by a thermal deposition process, such as filament or electron beam evaporation, the deposit takin place through an etched metal foil mask or stencil which is placed on and registered with the appropriate location on the chip or wafer to be metallised.
A similar or identical mask is employed for the solder deposition stage. This metal foil mask technique, however, is limited to the provision of relatively coarsely-defined solder and wettable metallisation areas (that is, having a surface area greater than about 100 micrometres diameter). The mask technique is also of limited accuracy, both with regard to solder bond diameter control (within a single solder run and from one solder run to another as masks are changed) and in accuracy of alignment to the contact points on the chip surface. A risk of contamination and/or damage to the chip surface is also present by the need for physical contact between the mask and chip surfaces.
The present invention was devised to provide a lithographic method for the definition of solderable metallisation and solder areas which can overcome some of the disadvantages of the metal foil mask technique.
According to the invention, there is provided a method of manufacturing a solder bonded integrated circuit device, the method comprising the steps of providing a substrate surface upon which a defined metallisation area for subsequent soldering is required, pressure bonding an area of a dry film photoresist material to said surface, exposing a selected. area of the photoresist material to a light source and then developing the exposed material to provide a defined opening on the substrate surface to receive the required metallisation area.
The substrate surface and photoresist material may then be coated with a vacuum deposited metal film, and then washed with a solvent to remove the remaining photoresist material and any unwanted portions of the deposited metal film. Solder masses may then be deposited on the resulting defined metallisation areas supported on the substrate surface.
The invention also comprises a solder bonded integrated circuit device when manufactured by the method of the invention.
By way of example, a particular embodiment of the invention will now be described with reference to the accompanying drawing, in which: Figure 1 shows in cross-section part of an integrated circuit device having a substrate body coated with a dry film photoresist material; Figure 2 shows the same part after coating with a vapour deposited metal film; and, Figure 3 shows the same part after washing off the remaining photoresist material.
As depicted in Figure 1, a substrate body 1, which is intended to form part of an integrated circuit device, has been provided with a surface coating of a dry film resist material 2. The resist material is originally provided in the form of a photosensitive polymer film, typically between 18 and 100 micrometres in thickness. The photosensitive layer is sandwiched between two protective polymer layers each typically 25 micrometres in thickness.
In order to attach the resist material to the substrate body, one of the protective layers is removed and the dry film is then bonded to the body to be metallised with the solderable metallisation area or with solder itself. The bonding is effected using a hot-roll laminate machine or a vacuum laminater and a combi nation of raised temperature and pressure conditions. These may be, for example, a temperature of 1 200C and a pressure of one bar. Some examples of suitable commercially available dry film resist materials include the negative working, organic solvent developed materials sold under the trade names of Ris ton (RTM), Type I (Du Pont) and Laminar GB (Thiokol).
In order to form a pattern for exposing the photoresist material, a photomask is placed over the dry film coated substrate body and the dry film is exposed in a suitable ultraviolet photoalignment machine, those typically em ployed in semiconductor wafer processing for contact exposure being particularly suitable.
The second polymer protection layer is then removed from the resist surface and the dry film on the substrate 1 is developed in a sta bailed 1.1.1 -trichloroethane solvent bath us ing a spray method.
The use of the negative masking dry film resist material, together with the correct expo sure and development conditions, results in the production of an undercut resist mask pro file-which is ideal for 'float-off' metal deposi tion for bath-solderable metallisation, solder deposition and related processes. Any photo resist residues or the formation of any slight foot at the base of the developed apertures may be effectively removed by an oxygen oplasma ashing r similar step.
Figure 1 shows this stage of the metallisation process where the resist material 2 has been removed from one place to form the aperture 3 which may have a width from about forty micrometres upwards. The side walls 4 of the aperture 3 are seen to be slightly undercut and this provision allows the final metal deposit intended to be formed on the substrate body to be kept accurately to the required dimensions.
The solderable metallisation or solder layer or the alternative metal deposit is next deposi ted from a distant point-deposition source (such as a heated fila#ment, an evaporation boat or an electron or ion beam source) which is positioned approximately normally to the plane of the masked wafer body.
The undercut resist profile of the patterned dry film prevents the aperture side walls from being coated with metal. The view of Figure 2 shows the resist material 2 on the substrate 1 with a deposited metal layer 6 on the surface of the material 2 and a separate portion 7 of the metal lying in contact with the substrate 1 at the bottom of the aperture 3.
The dry film resist material is next removed from the substrate body by solvent dissolution and this simultaneously removes the metal film portion which had been deposited on the surface of the dry film itself. The substrate body is thus left with the accurately defined metallisation area 7 lying on the former patterned aperture area.
Figure 3 shows the substrate body 1 with the metallisation area 7 after the dry film liftoff operation had been carried out.
The use of a dry film lift-off process allows the required metallisation and other deposit areas to be defined with an accuracy of about forty micrometers diameter (but the accuracy usually being not less than about 0.8 of the thickness of the dry film material employed).
The edge accuracy can be about plus or minus two micrometres or better, and the deposit thickness accuracy can approach that of the dry film mask material employed (that is, up to several tens of micrometres). The technique is therefore particularly appropriate to flip chip solder bonding technology where a substantial solder thickness is required. The dry film materials cited are also compatible with the sputter or ion beam cleaning processes that may be required later to ensure good ohmic contact to metallisation areas on the integrated circuit to which solder bonds are being added, prior to the deposition of the solderable metallisation material.
In applying this technique to flip chip solder bonding, a single masking stage may be employed for both solderable metallisation and solder application, resulting in thenformation of identical application areas. Alternatively, two masking operations may be employed, with different wettable metal and solder application areas, to provide controlled dewetting of the solder from the non wettable areas onto the wettable metal areas as a further means of increasing solder bump and bond height.
The foregoing description of an embodiment of the invention has been given by way of example only and a number of modifications may be made without departing from the scope of the invention as defined in the appended claims. For instance, it is not essential that the step of depositing the metal film layer should result in only a single metal being deposited. A multilayer metal film could alternatively be deposited in a single vacuum deposition pump down process, if this was required.
With a suitable change in the type of dry film photoresist material, the steps of developing the exposed layer could be effected in an aqueous rather than in an organic solvent bath.
CLAIMS 1. A method of manufacturing a solder bonded integrated circuit device, the method comprising the steps of providing a substrate surface upon which a defined metallisation area for subsequent soldering is required, pressure bonding an area of a dry film photoresist material to said surface, exposing a selected area of the photoresist material to a light source and then developing the exposed material to provide a defined opening on the substrate surface to receive the required metallisation area.
2. A method as claimed in Claim 1, including the further step of coating the said substrate surface and photoresist material with a vacuum deposited metal film, and then washing with a solvent to remove the remaining photoresist material and any unwanted portions of the deposited metal film.
3. A method as claimed in Claim 2, including the further step of depositing solder masses on the defined metallisation areas supported on the substrate surface.
4. A method of manufacturing a solder bonded integrated circuit device substantially as hereinbefore described with reference to the accompanying drawing.
5. A solder bonded integrated circuit device when manufactured by a method as claimed in any one of Claims 1 to 4.
6. A solder bonded integrated circuit device substantially as hereinbefore described with reference to the accompanying drawing.

Claims (1)

  1. Amendments to the claims have been filed, and have the following effect: Claims 1, 3, 4, 5 and 6 above have been deleted or textually amended.
    New or textually amended claims have been filed as follows:
    1. A method of manufacturing a solder bonded integrated circuit or a related device, the method comprising the steps of providing a substrate surface upon which a defined metallisation area for subsequent soldering is required, pressur, bonding an area of a dry film photoresist material to said surface, exposing a selected area of the photoresist material to a light source and then developing the exposed material to provide a defined opening with an undercut profile on the substrate surface to receive the required metallisation area.
    3. A method as claimed in Claim 2, in which the deposited metal film has a thickness up to that of the dry film photoresist material.
    4. A method as claimed in Claim 2 or 3, including the further step of depositing solder masses on the defined metallisation areas supported on the substrate surface.
    5. A method of manufacturing a solder bonded integrated circuit or a related device subseantially as hereinbefore described with reference to the accompanying drawing.
    6. A solder bonded integrated circuit or a related device when manufactured by a method as claimed in any one of Claims 1 to 5.
    7. A solder bonded integrated circuit or a related device substantially as hereinbefore described with reference to the accompanying drawing.
GB8620287A 1986-08-20 1986-08-20 Solder bonded integrated circuit devices Expired - Fee Related GB2194386B (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
GB8620287A GB2194386B (en) 1986-08-20 1986-08-20 Solder bonded integrated circuit devices

Applications Claiming Priority (1)

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GB8620287A GB2194386B (en) 1986-08-20 1986-08-20 Solder bonded integrated circuit devices

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GB8620287D0 GB8620287D0 (en) 1986-10-01
GB2194386A true GB2194386A (en) 1988-03-02
GB2194386B GB2194386B (en) 1990-07-18

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Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0331598A2 (en) * 1988-03-04 1989-09-06 International Business Machines Corporation A method for producing a plurality of layers of metallurgy
EP0598555A1 (en) * 1992-11-17 1994-05-25 AT&T Corp. Process for forming input/output bumps
EP0655779A1 (en) * 1993-11-26 1995-05-31 Delco Electronics Corporation Method of forming solder bumps on an integrated circuit flip chip
US20120318855A1 (en) * 2011-06-20 2012-12-20 International Business Machines Corporation Ims (injection molded solder) with two resist layers for forming solder bumps on substrates

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
GB1394062A (en) * 1971-10-08 1975-05-14 Lucas Electrical Co Ltd Semi-conductor devices
GB2059679A (en) * 1979-09-19 1981-04-23 Gen Electric Method of making composite bodies

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
GB1394062A (en) * 1971-10-08 1975-05-14 Lucas Electrical Co Ltd Semi-conductor devices
GB2059679A (en) * 1979-09-19 1981-04-23 Gen Electric Method of making composite bodies

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0331598A2 (en) * 1988-03-04 1989-09-06 International Business Machines Corporation A method for producing a plurality of layers of metallurgy
EP0331598A3 (en) * 1988-03-04 1991-04-10 International Business Machines Corporation A method for producing a plurality of layers of metallurgy
EP0598555A1 (en) * 1992-11-17 1994-05-25 AT&T Corp. Process for forming input/output bumps
EP0655779A1 (en) * 1993-11-26 1995-05-31 Delco Electronics Corporation Method of forming solder bumps on an integrated circuit flip chip
US20120318855A1 (en) * 2011-06-20 2012-12-20 International Business Machines Corporation Ims (injection molded solder) with two resist layers for forming solder bumps on substrates
US8921221B2 (en) * 2011-06-20 2014-12-30 International Business Machines Corporation IMS (injection molded solder) with two resist layers forming solder bumps on substrates

Also Published As

Publication number Publication date
GB2194386B (en) 1990-07-18
GB8620287D0 (en) 1986-10-01

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732 Registration of transactions, instruments or events in the register (sect. 32/1977)
PCNP Patent ceased through non-payment of renewal fee

Effective date: 19930820