JP4477213B2 - Circuit board and circuit board manufacturing method - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a circuit board and a method for manufacturing the circuit board.
[0002]
[Prior art]
Generally, flip chip mounting of a semiconductor chip on a circuit board is performed by the following method. First, in the mounting apparatus, the position of the electrode pad of the chucked semiconductor chip is captured by a camera, and image processing is performed to obtain the position coordinates of the semiconductor chip. At the same time, the alignment mark on the circuit board is captured by another camera, and the same image processing is performed to obtain the position coordinates of the circuit pattern formed on the circuit board. Thereafter, the position and orientation of the semiconductor chip are corrected based on the obtained position coordinates of the semiconductor chip and the position coordinates of the circuit pattern, and the semiconductor chip is mounted at the design position on the circuit pattern. When the semiconductor chip is flip-chip mounted on the circuit board, metal bumps, which are bonding materials, are formed on the circuit pattern and on the electrode pads of the semiconductor chip.
[0003]
As described above, in this method, the position coordinates of the circuit pattern are obtained using alignment marks. For these alignment marks and circuit patterns, a resist pattern is formed on the copper foil using a single photomask having a pattern corresponding to both, and the copper foil is etched using the resist pattern as an etching mask. It is formed by. Therefore, the accuracy of the relative position between the alignment mark and the circuit pattern is extremely high, and the positional deviation amount is only 2 μm or less. Therefore, it is possible to obtain the position coordinates of the circuit pattern with high accuracy.
[0004]
However, high positional accuracy has not been realized for metal bumps. Therefore, a connection failure may occur between the electrode pad of the semiconductor chip and the circuit pattern of the circuit board. This will be described with reference to FIG.
[0005]
FIG. 5 is a plan view schematically showing a part of a conventional circuit board 100. Since the metal bump 103 is not formed in the same process as the alignment mark or the circuit pattern 102, a relatively large positional deviation occurs between the position of the actually formed metal bump 103 and the design position 104.
[0006]
For example, when a metal bump 103 is formed by forming a resist pattern on the circuit pattern 102, printing a solder paste in the opening, and heating and melting the paste, the deviation of the metal bump 103 from the design position 104 is In addition to the accuracy of each photomask used to form the circuit pattern 102 and the metal bump 103, the alignment accuracy between the photomask used to form the metal bump 103 and the circuit pattern 102 affects. As a result, the positional deviation amount of the position of the metal bump 103 from the design position 104 may reach about 20 μm.
[0007]
As described above, when the semiconductor chip is mounted at the design position of the circuit board 100 when the displacement amount of the metal bump 103 is large, the alignment between the electrode pad of the semiconductor chip and the metal bump 103 becomes incomplete. The connection between the electrode pad and the circuit pattern 102 of the circuit board 100 becomes unstable. For this reason, according to the prior art, a connection failure occurs between the electrode pad of the semiconductor chip and the circuit pattern of the circuit board.
[0008]
Such a connection failure can be avoided, for example, by increasing the diameter of the metal bump corresponding to the assumed positional deviation amount of the metal bump. However, in this case, it is difficult to narrow the pitch between the metal bumps. Therefore, there arises a problem that it becomes impossible to flip-chip mount a semiconductor chip having a narrow electrode pad pitch.
[0009]
[Problems to be solved by the invention]
The present invention has been made in view of the above circumstances, and an object thereof is to enable flip chip mounting with high reliability.
It is another object of the present invention to enable flip chip mounting of a semiconductor chip having a narrow electrode pad pitch with high reliability.
Another object of the present invention is to provide a circuit board capable of flip-chip mounting a semiconductor chip with high reliability and a method for manufacturing the circuit board.
In addition, an object of the present invention is to provide a circuit board capable of flip-chip mounting a semiconductor chip having a narrow electrode pad pitch with high reliability, and a manufacturing method thereof.
[0010]
[Means for Solving the Problems]
In order to solve the above problems, the present invention provides a circuit board for flip-chip mounting a semiconductor chip provided with an electrode pad on one main surface, and is formed on one main surface of the insulating substrate and the insulating substrate. a circuit pattern made of a matte solder plating, the electrode pad and the circuit pattern and the bonding metal bumps formed on the circuit pattern so as to bond the said matte constituting the bonding bump An alignment mark made of the same matte solder plating as the solder plating , formed on one main surface of the insulating substrate and used for alignment when the semiconductor chip is flip-chip mounted on the circuit board, and the circuit pattern It is made of the same material as the constituent material, has a higher reflectance than the alignment mark, and the insulating substrate and the alignment marker. Providing a circuit board, characterized by comprising a metal pattern constituting the background of the alignment mark extends around the alignment mark with the.
[0011]
The present invention also provides an insulating substrate, a circuit pattern formed on one main surface of the insulating substrate, an electrode pad provided on one main surface of a semiconductor chip, and the circuit pattern for bonding the circuit pattern. A method of manufacturing a circuit board, comprising: a metal bump for bonding formed on a pattern; and an alignment mark formed on one main surface of the insulating substrate and used for alignment when the semiconductor chip is flip-chip mounted. A resist is formed on a metal layer provided on one main surface of the insulating substrate by a photolithography technique using a single photomask having a pattern corresponding to both the bonding metal bump and the alignment mark. forming a pattern, the resist pattern wherein the bonding metal bumps and said alignment by an electrolytic plating method using a A step of simultaneously forming both over click, after the step of forming the metal bumps and the alignment mark the junction, and patterned to form the circuit pattern using a photolithography and etching said metal layer A method for manufacturing a circuit board comprising the steps of:
[0012]
As described above, in the present invention, the bonding metal bump and the alignment mark are simultaneously formed using a single photomask. The alignment accuracy is not involved in the relative position between the metal bump formed by such a method and the alignment mark, and therefore the error is extremely small. Therefore, according to the present invention, the alignment of the electrode pads of the semiconductor chip and the metal bumps can be performed with high accuracy, and connection failure can be prevented. That is, according to the present invention, it is possible to avoid a connection failure without increasing the diameter of the metal bump, so that it is possible to flip-chip mount a semiconductor chip having a narrow electrode pad pitch with high reliability.
[0013]
When the bonding metal bump and the alignment mark are simultaneously formed using a single photomask, the bonding metal bump and the alignment mark are usually made of the same material. In other words, it can be said that the material constituting the bonding metal bump and the material constituting the alignment mark are the same as a remarkable feature found when the method of the present invention is applied.
[0014]
In the present invention, the bonding metal bump and the alignment mark can be formed by using, for example, an electrolytic plating method. Moreover, as a material which comprises them, gold | metal | money and solder can be mentioned, for example.
[0015]
In the present invention, usually, a metal pattern made of the same material as that constituting the circuit pattern is interposed between the insulating substrate and the alignment mark. When the contrast between the alignment mark and the insulating substrate is insufficient, this metal pattern is formed to extend around the alignment mark and used as the background of the alignment mark, thereby providing sufficient contrast. Can be realized.
[0016]
In the present invention, the resist pattern used for forming the bonding metal bump and the alignment mark is usually formed on a metal layer provided on one main surface of the insulating substrate. That is, the step of forming the circuit pattern by patterning the metal layer is usually performed after the step of forming the bonding metal bump and the alignment mark. In this case, even if the position of the circuit pattern is slightly deviated from the design position, the etching of the metal layer immediately below the metal bump hardly proceeds, so that no connection failure occurs between the metal bump and the circuit pattern. Therefore, the semiconductor chip can be flip-chip mounted with higher reliability.
[0017]
DETAILED DESCRIPTION OF THE INVENTION
Hereinafter, the present invention will be described in more detail with reference to the drawings. In the drawings, the same or similar members are denoted by the same reference numerals, and redundant description is omitted.
1 to 3 schematically show a manufacturing process of a circuit board according to the first embodiment of the present invention, and FIGS. 1 (a) and 1 (c), FIGS. 2 (d) to (f), 3 (g) and 3 (h) are plan views schematically showing a circuit board manufacturing process according to the first embodiment of the present invention, and FIG. 1 (b) is a structure shown in FIG. 1 (a). It is sectional drawing along the AA of. In the first embodiment, the circuit board 10 shown in FIG. 3H is manufactured by the following method.
[0018]
First, as shown in FIGS. 1A and 1B, a metal layer 12 is formed on one main surface of an insulating substrate 11 such as a glass epoxy layer having a structure in which a polyimide film or glass cloth is impregnated with epoxy. A material having a copper foil is prepared. Next, a negative photosensitive dry film 13 having a thickness of 50 μm is laminated on the copper foil 12.
[0019]
Next, as shown in FIG.1 (c), this photosensitive dry film 13 is exposed through the photomask which light-shields the area | region which forms the metal bump and alignment mark. Here, an ultra-high pressure mercury lamp was used as the exposure light source, and the irradiation amount was 160 mJ / cm ² . Further, the photosensitive dry film 13 is developed using a Na ₂ CO ₃ aqueous solution having a liquid temperature of 30 ° C. and a concentration of 1% by mass as a developing solution, so that openings 14 are formed in regions corresponding to the metal bumps and alignment marks. And a pattern plating resist pattern 16 having 15.
[0020]
Thereafter, as shown in FIG. 2D, using the resist pattern 16 as a mask, the exposed portion of the copper foil 12 is electroplated with solder to form a solder bump 17 having a height of 10 μm as a bonding metal bump. At the same time, a cross-shaped alignment mark 18 made of solder is formed. In this electroplating, an AS513 bath (trade name: manufactured by Ishihara Pharmaceutical Co., Ltd.) was used as a solder plating solution.
[0021]
Next, as shown in FIG. 2E, the resist pattern 16 is stripped using a 3% NaOH aqueous solution having a liquid temperature of 45 ° C. as the stripping solution. Next, as shown in FIG. 2 (f), a photosensitive dry film 19 is laminated on the copper foil 12. Further, the photosensitive dry film 19 is exposed through a photomask that shields light from areas other than the area 20 where the circuit pattern is formed. As an exposure light source, parallel light from an ultrahigh pressure mercury lamp was used, and an irradiation amount was set to 100 mJ / cm ² .
[0022]
Thereafter, as shown in FIG. 3 (g), the photosensitive dry film 19 is developed using a Na ₂ CO ₃ aqueous solution having a liquid temperature of 30 ° C. and a concentration of 1% by mass as a developer to obtain a circuit pattern. An etching resist pattern 21 in which only the corresponding region 20 is left and the other regions are opened is obtained.
[0023]
Next, as shown in FIG. 3H, using the resist pattern 21 as an etching mask, the exposed portion of the copper foil 12 is etched with an alkaline etchant to form a circuit pattern 22. Next, the resist pattern 21 is stripped using a 3% NaOH aqueous solution having a liquid temperature of 45 ° C. as the stripping solution. As described above, the circuit board 10 shown in FIG.
[0024]
Next, a second embodiment of the present invention will be described. In the first embodiment described above, the background of the alignment mark 18 is configured on the surface of the insulating substrate 11, but when the alignment mark 18 is formed by matte solder plating, the contrast between them becomes insufficient, Image recognition may be difficult. The second embodiment described below is useful in such a case.
[0025]
FIG. 4 is a plan view schematically showing a circuit board according to the second embodiment of the present invention. The circuit board 10 according to the second embodiment shown in FIG. 4 has substantially the same structure as the circuit board 10 according to the first embodiment shown in FIG. The difference is that a metal pattern 23 interposed between the marks 18 is provided so as to extend around the alignment marks 18. That is, in the second embodiment, unlike the first embodiment, the surface of the metal pattern 23 constitutes the background of the alignment mark 18. When the reflectance of the alignment mark 18 is low, a high contrast can be obtained and the image can be easily recognized by configuring the background with the metal pattern 23 having a high reflectance.
[0026]
The circuit board 10 shown in FIG. 4 can be manufactured by the following method, for example. First, the steps described in the first embodiment with reference to FIGS. 1A to 1C and FIGS. 2D and 2E are performed.
[0027]
Next, the same process as described in the first embodiment with reference to FIG. However, in this embodiment, a photomask designed to expose not only the region 20 where the circuit pattern 22 is formed but also the region where the metal pattern 23 is formed is used.
[0028]
Thereafter, development similar to that described above is performed to obtain an etching resist pattern in which only the regions corresponding to the circuit pattern 22 and the metal pattern 23 are left and the other regions are opened. Furthermore, the circuit board 10 shown in FIG. 4 is obtained by carrying out the steps described with reference to FIGS. 3G and 3H in the first embodiment.
[0029]
In the methods according to the first and second embodiments described above, the solder bumps 17 and the alignment marks 18 are simultaneously formed using a single photomask as described above. Therefore, the amount of positional deviation of the solder bump 17 with respect to the alignment mark 18 is as small as about 2 μm, and extremely high relative positional accuracy can be realized. Therefore, assuming that a semiconductor chip in which metal bumps having a diameter α are formed on the electrode pads is mounted on the circuit board 10, the misalignment of the solder bumps 17 with respect to the alignment marks 18 is compensated to avoid poor connection. For this, the diameter of the solder bump 17 may be α + 4 μm.
[0030]
On the other hand, in the prior art, since the solder bump and the alignment mark are formed in separate steps, the relative positional accuracy of the photomask is used to form each of the dimensional accuracy and the solder bump. The alignment accuracy of the photomask used in the process is affected. As a result, the positional deviation amount of the solder bump with respect to the alignment mark reaches about 20 μm. Therefore, in the prior art, assuming that a semiconductor chip having a metal bump having a diameter α formed on an electrode pad is mounted on a circuit board, the positional deviation of the solder bump with respect to the alignment mark is compensated to avoid poor connection. For this purpose, the solder bump diameter must be α + 40 μm.
[0031]
As described above, according to the methods according to the first and second embodiments of the present invention, the diameter of the solder bump 17 can be made extremely small as compared with the prior art while preventing connection failure. Therefore, according to the method according to the first and second embodiments, the pitch between the metal bumps can be reduced, and a semiconductor chip with a narrower electrode pad pitch can be flip-chip with high reliability without causing an electrical short circuit. It can be implemented.
[0032]
In the first and second embodiments described above, the cross-shaped alignment mark 18 is formed, but the alignment mark 18 may have another shape as long as the mounting apparatus can recognize it. For example, the alignment mark 18 may have a shape generally used as an alignment mark, such as a round shape or a ring shape.
[0033]
【The invention's effect】
As described above, in the present invention, the bonding metal bump and the alignment mark are formed simultaneously using a single photomask. The alignment accuracy is not involved in the relative position between the metal bump formed by such a method and the alignment mark, and therefore the error is extremely small. Therefore, according to the present invention, the alignment of the electrode pads of the semiconductor chip and the metal bumps can be performed with high accuracy, and connection failure can be prevented. Therefore, according to the present invention, poor connection can be avoided without increasing the diameter of the metal bump, and a semiconductor chip with a narrow electrode pad pitch can be flip-chip mounted with high reliability. That is, according to the present invention, a circuit board capable of flip-chip mounting a semiconductor chip having a narrow electrode pad pitch with high reliability and a manufacturing method thereof are provided.
[Brief description of the drawings]
FIGS. 1A and 1C are plan views schematically showing a manufacturing process of a circuit board according to a first embodiment of the present invention, and FIG. 1B is taken along line AA in FIG. Sectional drawing.
FIGS. 2D to 2F are plan views schematically showing a circuit board manufacturing process according to the first embodiment of the present invention. FIGS.
FIGS. 3G and 3H are plan views schematically showing a circuit board manufacturing process according to the first embodiment of the present invention. FIGS.
FIG. 4 is a plan view schematically showing a circuit board according to a second embodiment of the present invention.
FIG. 5 is a plan view schematically showing a part of a conventional circuit board.
[Explanation of symbols]
10, 100 ... circuit board; 11 ... insulating substrate; 12 ... metal layer;
13, 19 ... photosensitive dry film; 14, 15 ... opening;
16, 21 ... resist pattern; 17, 103 ... metal bump;
18 ... Alignment mark; 20 ... Area; 22, 102 ... Circuit pattern;
23 ... Metal pattern; 104 ... Design position

Claims (3)

An insulating substrate, a circuit pattern formed on one main surface of the insulating substrate, and an electrode pad provided on one main surface of a semiconductor chip and the circuit pattern are formed on the circuit pattern so as to be bonded to each other. A method of manufacturing a circuit board comprising: a bonding metal bump; and an alignment mark formed on one main surface of the insulating substrate and used for alignment when flip-chip mounting the semiconductor chip,
A resist pattern is formed on a metal layer provided on one main surface of the insulating substrate by a photolithography technique using a single photomask having a pattern corresponding to both the bonding metal bump and the alignment mark. And a process of
Simultaneously forming both the bonding metal bump and the alignment mark by an electrolytic plating method using the resist pattern ;
After the step of forming the bonding metal bump and the alignment mark, the step of patterning the metal layer using a photolithography technique and an etching technique to form the circuit pattern. A method of manufacturing a circuit board. The circuit board further includes a metal pattern made of the same material as that constituting the circuit pattern between the insulating substrate and the alignment mark, and the metal pattern is compared with the alignment mark. The reflectance is higher and extends around the alignment mark to constitute the background of the alignment mark;
The bonding metal bump and the alignment mark are formed by matte solder plating,
The metal layer is patterned so that the metal pattern is formed in addition to the circuit pattern.
The method for manufacturing a circuit board according to claim 1. A circuit board for flip-chip mounting a semiconductor chip provided with an electrode pad on one main surface,
An insulating substrate;
A circuit pattern formed on one main surface of the insulating substrate;
Metal bumps for bonding formed on the circuit pattern in order to bond the electrode pad and the circuit pattern , made of matte solder plating ,
It is made of the same matte solder plating as the matte solder plating constituting the bonding bump, and is formed when one of the main surfaces of the insulating substrate is flip-chip mounted on the circuit board. Alignment marks used for alignment ,
It is made of the same material as that constituting the circuit pattern, has a higher reflectance than the alignment mark, and extends around the alignment mark between the insulating substrate and the alignment mark. circuit board, characterized by comprising the <br/> metal pattern constituting the background of the alignment mark.

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