JP2000277898A - Board for mounting of ball grid array package - Google Patents

Board for mounting of ball grid array package

Info

Publication number
JP2000277898A
JP2000277898A JP7906299A JP7906299A JP2000277898A JP 2000277898 A JP2000277898 A JP 2000277898A JP 7906299 A JP7906299 A JP 7906299A JP 7906299 A JP7906299 A JP 7906299A JP 2000277898 A JP2000277898 A JP 2000277898A
Authority
JP
Japan
Prior art keywords
solder
diameter
board
pad
connection
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP7906299A
Other languages
Japanese (ja)
Inventor
Takeshi Nakagawa
剛 中川
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Nippon Avionics Co Ltd
Original Assignee
Nippon Avionics Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Nippon Avionics Co Ltd filed Critical Nippon Avionics Co Ltd
Priority to JP7906299A priority Critical patent/JP2000277898A/en
Publication of JP2000277898A publication Critical patent/JP2000277898A/en
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001Technical content checked by a classifier
    • H01L2924/0002Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Abstract

PROBLEM TO BE SOLVED: To obtain a board, for the mounting of a BGA package, in which stress is not concentrated in a connection place due to the difference in coefficients of thermal expansion between a BGA package board and a board for the mounting of the package and whose connection reliability is high. SOLUTION: In a board comprising a pad for connection, which is formed so as to correspond to a solder ball on a BGA package, a pad 32 for connection is formed on an insulating board 31 to be in a terrace shape, in such a way that its lower layer is made larger than the diameter of the solder ball and that its upper layer is nearly identical to the diameter of the solder ball. In addition, a first solder resist 35 which comprises an opening 36, whose diameter is nearly equal to the diameter of the lower layer of the pad 32 for connection is formed on the insulating board 31. A second solder resist 37 which comprises an opening 38, whose diameter is nearly equal to the diameter of the solder ball, is formed on it in such a way that both openings are aligned on the same axis. Thereby, this board for the mounting of the BGA package is obtained. A solder ball which is melted inside the openings 36, 38 forms a wedge-shaped solder bump.

Description

【発明の詳細な説明】DETAILED DESCRIPTION OF THE INVENTION

【0001】[0001]

【発明の属する技術分野】本発明は、ボールグリッドア
レイ(以下BGAという)パッケージのソルダボールに
それぞれ対応させて設けた接続用パッドを有する基板に
係り、特にソルダボールの位置決めが正確にできると共
に、ソルダボールとの接続信頼性を向上し得る接続用パ
ッドの構造に関するものである。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a substrate having connection pads provided in correspondence with solder balls of a ball grid array (hereinafter referred to as "BGA") package. The present invention relates to a structure of a connection pad that can improve connection reliability with a solder ball.

【0002】[0002]

【従来の技術】近年、シングルチップモジュールがマル
チチップモジュールへ置き換わるなかで、パッケージは
高密度実装・ハイスピード化が求められ、I/Oピン数
の増加の方向に進んでいる。こうした点に配慮したパッ
ケージとしてBGAパッケージがある。BGAは、半導
体が実装・配線された基板の裏面に1.0〜1.5mm
ピッチ、またはそれ以下のピッチで格子状に入出力用電
極パッドを形成し、その上にはんだによる球形のボール
状端子(以下ソルダボールという)を形成したものであ
る。
2. Description of the Related Art In recent years, as single-chip modules have been replaced with multi-chip modules, high-density packaging and high-speed packaging have been required, and the number of I / O pins has been increasing. There is a BGA package as a package in consideration of these points. BGA is 1.0 to 1.5 mm on the back surface of the substrate on which the semiconductor is mounted and wired.
Input / output electrode pads are formed in a grid pattern at a pitch equal to or less than the pitch, and spherical ball-shaped terminals made of solder (hereinafter referred to as solder balls) are formed thereon.

【0003】このBGAの実装方法としては、樹脂、セ
ラッミック等からなる基板の接続用パッド上にソルダペ
ーストあるいはフラックスを塗布し、その上にBGAパ
ッケージのソルダボールを対向させて載置してリフロー
ソルダリング法により両者を接合している。このような
基板の接続用パッドは、一般にパネルメッキ、パターン
メッキ、蒸着あるいは印刷工法によって形成されてい
る。
As a method of mounting the BGA, a solder paste or a flux is applied to connection pads of a substrate made of a resin, a ceramic, or the like, and solder balls of a BGA package are placed on the connection pads so as to face the reflow solder. Both are joined by a ring method. Such connection pads of the substrate are generally formed by panel plating, pattern plating, vapor deposition, or printing.

【0004】図4は、前記基板のうちパネルメッキ工法
によって作成されたプリント配線板の側面図であり、こ
のプリント配線板10は銅張り積層板をエッチング処理
して接続用パッド(以下、パッドという)1を形成した
後、パッド1を含むパターン間の絶縁を確保するために
レジストフィルム等を用いてソルダレジスト2を形成し
ている。なお3は銅張り積層板のコア材たる樹脂基板で
ある。
FIG. 4 is a side view of a printed wiring board formed by a panel plating method on the substrate. The printed wiring board 10 is obtained by etching a copper clad laminate and connecting pads (hereinafter referred to as pads). After the formation of 1), a solder resist 2 is formed using a resist film or the like in order to secure insulation between patterns including the pad 1. Reference numeral 3 denotes a resin substrate as a core material of the copper-clad laminate.

【0005】図5は前記プリント配線板10へBGAパ
ッケージを搭載した状態の側面図である。この図におい
て21はBGAパッケージ20の基板であって、半導体
チップなどの実装面の裏面側に設けられたプリント配線
板等のマザーボードと接続するためのI/Oパッド22
上にソルダボール23が形成されている。
FIG. 5 is a side view showing a state in which a BGA package is mounted on the printed wiring board 10. As shown in FIG. In this figure, reference numeral 21 denotes a substrate of the BGA package 20, which is an I / O pad 22 for connecting to a motherboard such as a printed wiring board provided on the back side of the mounting surface of a semiconductor chip or the like.
A solder ball 23 is formed thereon.

【0006】BGAパッケージ20はマウンタ等の実装
機を用いて、予めソルダペーストあるいはフラックスを
塗布したプリント配線板10の決められたパッド1上に
接続端子となるソルダボール23を搭載し、その後リフ
ロー加熱によりソルダボール23を溶融させ、プリント
配線板10のパッド1とはんだ付けによって接合する。
[0006] The BGA package 20 uses a mounting machine such as a mounter to mount solder balls 23 serving as connection terminals on predetermined pads 1 of the printed wiring board 10 to which solder paste or flux has been applied in advance, and then performs reflow heating. Melts the solder ball 23 and joins it to the pad 1 of the printed wiring board 10 by soldering.

【0007】図6はこの接合状態を示す側面図であり、
ソルダボール23がパッド1と接合してできたソルダバ
ンプ24は、プリント配線板10のパッド1やソルダレ
ジスト2によって溶融時の広がりが規制され、かつソル
ダバンプ24自体の表面張力によって樽状の形状を呈す
る。
FIG. 6 is a side view showing this joining state.
The solder bumps 24 formed by joining the solder balls 23 to the pads 1 are restricted from spreading during melting by the pads 1 and the solder resist 2 of the printed wiring board 10, and have a barrel-like shape due to the surface tension of the solder bumps 24 themselves. .

【0008】[0008]

【発明が解決しようとする課題】しかしながら、上記の
従来の方法においては、プリント配線板10とBGAパ
ッケージ20の基板は材質の違いにより熱膨張率に差が
あり、両者をはんだ付けにより接続させる時に加えられ
る熱の影響でソルダバンプ24とプリント配線板10の
パッド1およびBGAパッケージ20のI/Oパッド2
2との接続箇所5および25に応力が集中し、これらの
箇所においてクラックが生じ接続の信頼性が悪くなるば
かりか、最終的には電気的な接続を破壊してしまうとい
う問題があった。
However, in the above-mentioned conventional method, the printed wiring board 10 and the substrate of the BGA package 20 have a difference in thermal expansion coefficient due to a difference in material, and when the two are connected by soldering. Due to the effect of the applied heat, the solder bump 24 and the pad 1 of the printed wiring board 10 and the I / O pad 2 of the BGA package 20
Stress is concentrated at the connection points 5 and 25 with the connection 2, and cracks occur at these points, deteriorating the reliability of the connection and eventually breaking the electrical connection.

【0009】本発明は、このような従来の問題を解決す
るためになされたもので、BGA搭載用基板とBGAパ
ッケージ基板に熱膨張率の相違があっても接続信頼性が
低下せず、また基板のI/OパッドとBGAの位置合わ
せの簡単なボールグリッドアレイパッケージ実装用基板
を提供することを目的とする。
The present invention has been made to solve such a conventional problem. Even if the BGA mounting substrate and the BGA package substrate have a difference in the coefficient of thermal expansion, the connection reliability is not reduced. It is an object of the present invention to provide a board for mounting a ball grid array package in which the I / O pads of the board and the BGA can be easily aligned.

【0010】[0010]

【課題を解決するための手段】上記課題を解決するため
に第1の発明は、ボールグリッドアレイパッケージのソ
ルダボールにそれぞれ対応させて設けた接続用パッドを
有する基板において、下層が前記ソルダボールの直径よ
りも大径とされ上層が前記ソルダボールの直径と略同径
とされ前記基板上に段丘状に形成された接続用パッド
と、前記基板上に形成され前記接続用パッドの下層の直
径に略等しい径の開口を有する第1のソルダレジスト
と、前記ソルダボールの直径に略等しい径の開口を形成
し該開口と前記第1のソルダレジストの開口を同軸上に
整列させて前記第1のソルダレジスト上に形成した第2
のソルダレジストとからなることを特徴とする。
According to a first aspect of the present invention, there is provided a substrate having connection pads provided in correspondence with solder balls of a ball grid array package, wherein a lower layer of the solder balls is provided. A connection pad formed on the substrate in a stepped shape with a diameter larger than the diameter and an upper layer having substantially the same diameter as the diameter of the solder ball; and a diameter of a lower layer of the connection pad formed on the substrate. A first solder resist having an opening having a substantially equal diameter, an opening having a diameter substantially equal to the diameter of the solder ball, and the opening being coaxially aligned with the opening of the first solder resist to form the first solder resist; Second formed on solder resist
And a solder resist.

【0011】このように基板を構成すると、第2のソル
ダレジストに形成した開口にソルダボールが嵌合し、ソ
ルダボールと接続用パッドが正確に位置合わせされる。
また、第1および第2のソルダレジストの開口によって
形成された空洞内で溶融されたソルダボールは、段丘状
の接続用パッドに倣って流下し、楔状のソルダバンプを
形成する。
[0011] With this configuration of the substrate, the solder ball fits into the opening formed in the second solder resist, and the solder ball and the connection pad are accurately positioned.
Further, the solder balls melted in the cavities formed by the openings of the first and second solder resists flow down following the step-like connection pads to form wedge-shaped solder bumps.

【0012】また第2の発明は、前記第1のソルダレジ
ストおよび第2のソルダレジストのそれぞれの厚みが、
前記ソルダボールの半径の略2分の1であることを特徴
としている。このため、ソルダボールと接続用パッドが
正確に位置合わせできながら、ソルダボールの溶融によ
って沈下するボールグリッドアレイパッケージが第2の
ソルダレジストに当接せず、所望形状のソルダバンプが
形成される。
According to a second aspect of the present invention, the first solder resist and the second solder resist each have a thickness of:
It is characterized in that the radius is approximately one half of the radius of the solder ball. For this reason, while the solder balls and the connection pads can be accurately positioned, the ball grid array package that sinks due to the melting of the solder balls does not come into contact with the second solder resist, and solder bumps having a desired shape are formed.

【0013】[0013]

【実施の形態】以下、図1乃至図3を参照して本発明の
詳細について説明する。図1乃至図3は、本発明の一実
施形態を示す楔状ソルダバンプ形成工程を示す図であ
る。図1はパッケージ実装用プリント配線板の断面図で
ある。同図において、30はプリント配線板であり、こ
のプリント配線板30にはBGAパッケージのソルダボ
ールにそれぞれ対応させて、2層の段丘状に形成された
接続用パッド32が形成されている。
DESCRIPTION OF THE PREFERRED EMBODIMENTS The details of the present invention will be described below with reference to FIGS. 1 to 3 are views showing a step of forming a wedge-shaped solder bump according to an embodiment of the present invention. FIG. 1 is a sectional view of a printed wiring board for package mounting. In the figure, reference numeral 30 denotes a printed wiring board, on which connection pads 32 formed in two layers of terraces are formed corresponding to the solder balls of the BGA package, respectively.

【0014】この接続用パッド32は、プリント配線板
30の素材たる銅張り積層板の絶縁基板31上の銅箔に
フォトレジストを貼着し、BGAパッケージのソルダボ
ールに対応するそれぞれの位置に、ソルダボールの直径
よりも若干大径の領域を残してそれ以外の領域を遮光す
るフォトマスクを重ねて露光後現像し、接続用パッド3
2の下層のパッド33の部分をフォトレジストで被覆す
る。この状態でエッチング処理することによってパッド
33以外の銅箔を除去し、その後パッド33上のフォト
レジストを剥離することによって作成される。
The connection pads 32 are formed by attaching a photoresist to copper foil on an insulating substrate 31 of a copper-clad laminate, which is a material of the printed wiring board 30, at respective positions corresponding to solder balls of a BGA package. A photomask for shielding a light-shielding area from the other area while leaving an area slightly larger than the diameter of the solder ball is developed after exposure, and the connection pad 3 is formed.
The portion of the pad 33 in the lower layer 2 is covered with a photoresist. In this state, the copper foil other than the pads 33 is removed by etching, and then the photoresist on the pads 33 is peeled off.

【0015】次いで、このようにして形成されたパッド
33を含む絶縁基板31全面にフォトレジストを貼着
し、パッド33に対応する位置にソルダボールの直径と
略同径の領域を遮光するフォトマスクを重ねて露光後現
像し、パッド34となる部分以外の領域をフォトレジス
トで被覆して電解銅メッキして上層のパッド34を形成
し、フォトレジストを剥離することによって作成され
る。
Next, a photoresist is stuck on the entire surface of the insulating substrate 31 including the pads 33 formed in this manner, and a photomask is provided at a position corresponding to the pad 33 to shield a region having substantially the same diameter as the diameter of the solder ball. Are formed by exposing and developing after exposure, a region other than the portion to be the pad 34 is covered with a photoresist, and electrolytic copper plating is performed to form an upper layer pad 34, and the photoresist is peeled off.

【0016】次いで、このようにして2層の段丘状に形
成された接続用パッド32を備えた絶縁基板31上に、
BGAパッケージのソルダボールの半径の略2分の1の
厚さを有し該パッド32の下層パッド33の周囲に所定
の間隙を残して開口36を形成した第1のソルダレジス
ト35を貼着する。更にこの第1のソルダレジスト35
上に第1のソルダレジスト35と同等の厚さを有しBG
Aパッケージのソルダボールの直径に略等しい開口38
を形成した第2のソルダレジスト37を貼着する。
Next, on the insulating substrate 31 provided with the connection pads 32 formed in a two-layered terrace shape in this manner,
A first solder resist 35 having a thickness of approximately one-half the radius of the solder ball of the BGA package and having an opening 36 formed around a lower layer pad 33 of the pad 32 with a predetermined gap left is attached. . Further, the first solder resist 35
BG having the same thickness as the first solder resist 35
Opening 38 approximately equal to the diameter of the solder ball in package A
The second solder resist 37 formed with is formed.

【0017】なお、ソルダレジスト35および37の厚
みが不足する場合は、複数枚重ねあわせて所要の厚みを
持たせてもよい。その際、最下層のソルダレジスト35
と最上層のソルダレジスト37間に挿入するソルダレジ
ストに設ける開口は、パッド32に接触しない範囲で最
下層のソルダレジスト35に設けた開口36の外縁と最
上層のソルダレジスト37に設けた開口38の外縁とを
結ぶ直線上に略々位置するような径とするのがよい。
If the thickness of the solder resists 35 and 37 is insufficient, a plurality of solder resists may be stacked to have a required thickness. At this time, the lowermost solder resist 35
The opening provided in the solder resist inserted between the solder resist 37 of the uppermost layer and the outer edge of the opening 36 provided in the solder resist 35 of the lowermost layer and the opening 38 provided in the solder resist 37 of the uppermost layer as long as it does not contact the pad 32. It is preferable that the diameter is set so as to be located substantially on a straight line connecting the outer edge of the lens.

【0018】これら第1および第2のソルダレジスト3
5および37は、アクリル系ベースにエポキシ樹脂を組
み合わせたドライフィルム型のものが取り扱い上好適で
あり、開口36および38を含む所望のパターンを描画
したポジまたはネガフィルムを密着させ、パターンを紫
外線露光し、有機溶剤あるいは水溶液を用いて現像して
開口36および38を含む不要部位を溶解除去した後熱
硬化させることによって形成される。
The first and second solder resists 3
As for Nos. 5 and 37, a dry film type in which an epoxy resin is combined with an acrylic base is suitable for handling. A positive or negative film on which a desired pattern including openings 36 and 38 is drawn is brought into close contact, and the pattern is exposed to ultraviolet light. Then, it is formed by developing using an organic solvent or an aqueous solution, dissolving and removing unnecessary portions including the openings 36 and 38, and then thermally curing.

【0019】このようにして制作されたプリント配線板
30にBGAパッケージを搭載した状態を図2に示す。
図2はプリント配線板30へBGAパッケージ20を搭
載した状態の側面図であって、BGAパッケージ20は
マウンタ等の実装機を用いて、予めソルダペースあるい
はフラックスを塗布したプリント配線板30の決められ
たパッド32上に接続端子となるソルダボール23を搭
載し、その後リフロー加熱によりソルダボール23を溶
融させ、プリント配線板30のパッド32とはんだ付け
によって接合する。
FIG. 2 shows a state in which the BGA package is mounted on the printed wiring board 30 produced in this manner.
FIG. 2 is a side view showing a state in which the BGA package 20 is mounted on the printed wiring board 30. The BGA package 20 has been determined in advance by using a mounting machine such as a mounter. The solder balls 23 serving as connection terminals are mounted on the pads 32, and then the solder balls 23 are melted by reflow heating, and are joined to the pads 32 of the printed wiring board 30 by soldering.

【0020】図2において、ソルダレジスト35および
37の厚みはBGAパッケージ20のソルダボール23
の半径の略2分の1にそれぞれ形成されている。従っ
て、ソルダレジスト35と37の高さの合計は、ソルダ
ボール23の半径と同等になり、これによりBGAパッ
ケージ20のソルダボール23は、プリント配線板30
上のソルダレジスト35および37とパッド32で形成
された凹部39に嵌合することになる。
In FIG. 2, the thicknesses of the solder resists 35 and 37 are the same as those of the solder balls 23 of the BGA package 20.
Are formed at approximately one-half of the radius of. Accordingly, the sum of the heights of the solder resists 35 and 37 is equal to the radius of the solder ball 23, and the solder ball 23 of the BGA package 20 is
It fits into the concave portion 39 formed by the upper solder resists 35 and 37 and the pad 32.

【0021】図3はこのソルダボール23とパッド32
の接合状態を示す側面図であり、リフロー加熱時にソル
ダボール23はプリント配線板30のソルダレジスト3
5、37とパッド32で形成された凹部39において下
層パッド33の外縁まで引き付けられ、またパッド34
によってソルダバンプ25の中間部位の直径が規制され
て、強制的に楔状のバンプ25を形成することができ
る。
FIG. 3 shows the solder balls 23 and the pads 32.
FIG. 4 is a side view showing a bonding state of the solder resist 23 of the printed wiring board 30 during reflow heating.
In the recess 39 formed by the pads 5 and 37 and the pad 32, the pad 34 is attracted to the outer edge of the lower layer pad 33,
Accordingly, the diameter of the intermediate portion of the solder bump 25 is regulated, and the wedge-shaped bump 25 can be forcibly formed.

【0022】[0022]

【発明の効果】以上説明したように本願の第1の発明た
るボールグリッドアレイパッケージ実装用基板は、ボー
ルグリッドアレイパッケージのソルダボールにそれぞれ
対応させて設けた接続用パッドを有する基板において、
下層が前記ソルダボールの直径よりも大径とされ上層が
前記ソルダボールの直径と略同径とされ前記基板上に段
丘状に形成された接続用パッドと、前記基板上に形成さ
れ前記接続用パッドの下層の直径に略等しい径の開口を
有する第1のソルダレジストと、前記ソルダボールの直
径に略等しい径の開口を形成し該開口と前記第1のソル
ダレジストの開口を同軸上に整列させて前記第1のソル
ダレジスト上に形成した第2のソルダレジストとからな
るので、2層の段丘状に形成されたパッドと第1乃至第
3レジストの開口部によって形成された空間にソルダボ
ールの溶融はんだが流れ込み、プリント配線板とBGA
パッケージ間におけるソルダボールの形状が応力緩衝作
用のある楔状に形成され、ソルダバンプとプリント配線
板のパッドおよびBGAパッケージの電極との接続箇所
に応力が集中せず、プリント配線板とBGAパッケージ
基板に熱膨張率の相違があっても接続信頼性が低下する
ことはない。また、プリント配線板の最上層のソルダレ
ジストの開口部にBGAパッケージのソルダボールが勘
合するため、両者の位置合わせを正確かつ簡単に行うこ
とができる。
As described above, the ball grid array package mounting board according to the first invention of the present application is a board having connection pads provided respectively corresponding to the solder balls of the ball grid array package.
A lower pad having a diameter larger than the diameter of the solder ball, an upper layer having a diameter substantially equal to the diameter of the solder ball, a connection pad formed on the substrate in a stepped shape, and a connection pad formed on the substrate, A first solder resist having an opening having a diameter substantially equal to the diameter of the lower layer of the pad; and an opening having a diameter substantially equal to the diameter of the solder ball, and the opening and the opening of the first solder resist are coaxially aligned. And the second solder resist formed on the first solder resist. Therefore, the solder ball is formed in the space formed by the two-layer step-shaped pads and the openings of the first to third resists. Molten solder flows into the printed circuit board and BGA
The shape of the solder ball between the packages is formed in a wedge shape with a stress buffering function, stress is not concentrated on the connection points between the solder bumps and the pads of the printed wiring board and the electrodes of the BGA package, and heat is applied to the printed wiring board and the BGA package board. Even if there is a difference in the expansion coefficient, the connection reliability does not decrease. Further, since the solder ball of the BGA package fits into the opening of the solder resist in the uppermost layer of the printed wiring board, the positioning of both can be performed accurately and easily.

【0023】また第2の発明は、前記第1のソルダレジ
ストおよび第2のソルダレジストのそれぞれの厚みを、
前記ソルダボールの半径の略2分の1としたので、ソル
ダボールと接続用パッドが正確に位置合わせできなが
ら、ソルダボールの溶融によって沈下するボールグリッ
ドアレイパッケージが第2のソルダレジストに当接せ
ず、所望形状のソルダバンプが形成される。
According to a second aspect of the present invention, the first solder resist and the second solder resist have respective thicknesses of:
Since the radius of the solder ball is set to approximately one-half, the ball grid array package that sinks due to the melting of the solder ball contacts the second solder resist while the solder ball and the connection pad can be accurately positioned. Thus, a solder bump having a desired shape is formed.

【図面の簡単な説明】[Brief description of the drawings]

【図1】図1は、本発明になるボールグリッドアレイパ
ッケージ実装用基板の側断面図である。
FIG. 1 is a side sectional view of a ball grid array package mounting substrate according to the present invention.

【図2】図2は、本発明になるボールグリッドアレイパ
ッケージ実装用基板へボールグリッドアレイパッケージ
を搭載した状態の側断面図である。
FIG. 2 is a side sectional view showing a state where a ball grid array package is mounted on a ball grid array package mounting substrate according to the present invention.

【図3】図3は、本発明におけるソルダボールとパッド
の接合状態を示す側断面図である。
FIG. 3 is a side sectional view showing a bonding state between a solder ball and a pad according to the present invention.

【図4】図4は、従来のボールグリッドアレイパッケー
ジ実装用基板の側断面図である。
FIG. 4 is a side sectional view of a conventional ball grid array package mounting substrate.

【図5】図5は、従来のボールグリッドアレイパッケー
ジ実装用基板へボールグリッドアレイパッケージを搭載
した状態の側断面図である。
FIG. 5 is a side sectional view showing a state where a ball grid array package is mounted on a conventional ball grid array package mounting substrate.

【図6】図6は、従来のソルダボールとパッドとの接合
状態を示す側断面図である。
FIG. 6 is a side cross-sectional view showing a conventional solder ball and pad bonded state.

【符号の説明】[Explanation of symbols]

20 ボールグリッドアレパッケージ 22 I/O電極 23 ソルダボール 25 ソルダバンプ 30 プリント配線板 31 絶縁基板 32 パッド 33 下層パッド 34 上層パッド 35、37 フォトレジスト 36、38 開口 39 凹部 Reference Signs List 20 ball grid array package 22 I / O electrode 23 solder ball 25 solder bump 30 printed wiring board 31 insulating substrate 32 pad 33 lower layer pad 34 upper layer pad 35, 37 photoresist 36, 38 opening 39 recess

Claims (2)

【特許請求の範囲】[Claims] 【請求項1】 ボールグリッドアレイパッケージのソル
ダボールにそれぞれ対応させて設けた接続用パッドを有
する基板において、下層が前記ソルダボールの直径より
も大径とされ上層が前記ソルダボールの直径と略同径と
され前記基板上に段丘状に形成された接続用パッドと、
前記基板上に形成され前記接続用パッドの下層の直径に
略等しい径の開口を有する第1のソルダレジストと、前
記ソルダボールの直径に略等しい径の開口を形成し該開
口と前記第1のソルダレジストの開口を同軸上に整列さ
せて前記第1のソルダレジスト上に形成した第2のソル
ダレジストとからなることを特徴とするボールグリッド
アレイパッケージ実装用基板。
1. A substrate having connection pads provided corresponding to solder balls of a ball grid array package, wherein a lower layer has a diameter larger than the diameter of the solder balls and an upper layer has a diameter substantially equal to the diameter of the solder balls. A connection pad having a diameter and formed in a terrace shape on the substrate;
A first solder resist formed on the substrate and having an opening having a diameter substantially equal to a diameter of a lower layer of the connection pad; and an opening having a diameter substantially equal to a diameter of the solder ball, and forming the opening with the first solder resist. A substrate for mounting a ball grid array package, comprising: a second solder resist formed on the first solder resist by aligning the openings of the solder resist coaxially.
【請求項2】また第2の発明は、前記第1のソルダレジ
ストおよび第2のソルダレジストのそれぞれの厚みが、
前記ソルダボールの半径の略2分の1であることを特徴
とする請求項1記載のボールグリッドアレイパッケージ
実装用基板。
2. The semiconductor device according to claim 1, wherein said first solder resist and said second solder resist have respective thicknesses of:
2. The substrate for mounting a ball grid array package according to claim 1, wherein the radius of the solder ball is approximately one half.
JP7906299A 1999-03-24 1999-03-24 Board for mounting of ball grid array package Pending JP2000277898A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP7906299A JP2000277898A (en) 1999-03-24 1999-03-24 Board for mounting of ball grid array package

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP7906299A JP2000277898A (en) 1999-03-24 1999-03-24 Board for mounting of ball grid array package

Publications (1)

Publication Number Publication Date
JP2000277898A true JP2000277898A (en) 2000-10-06

Family

ID=13679415

Family Applications (1)

Application Number Title Priority Date Filing Date
JP7906299A Pending JP2000277898A (en) 1999-03-24 1999-03-24 Board for mounting of ball grid array package

Country Status (1)

Country Link
JP (1) JP2000277898A (en)

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100575885B1 (en) 2004-05-12 2006-05-03 주식회사 하이닉스반도체 substrate of mounting a semiconductor device for packaging and method of forming the same
US7098407B2 (en) 2003-08-23 2006-08-29 Samsung Electronics Co., Ltd. Non-solder mask defined (NSMD) type wiring substrate for ball grid array (BGA) package and method for manufacturing such a wiring substrate
JP2008311538A (en) * 2007-06-18 2008-12-25 Rohm Co Ltd Circuit board, and semiconductor device
JP2010206038A (en) * 2009-03-05 2010-09-16 Fujitsu Ltd Mounting structure of electronic component, and manufacturing method of substrate for mounting electronic component
CN102458039A (en) * 2010-10-18 2012-05-16 上海嘉捷通电路科技有限公司 Thick copper circuit board
JP2019021752A (en) * 2017-07-14 2019-02-07 富士通株式会社 Wiring board, electronic equipment, method of manufacturing wiring board and method of manufacturing electronic equipment

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7098407B2 (en) 2003-08-23 2006-08-29 Samsung Electronics Co., Ltd. Non-solder mask defined (NSMD) type wiring substrate for ball grid array (BGA) package and method for manufacturing such a wiring substrate
KR100575885B1 (en) 2004-05-12 2006-05-03 주식회사 하이닉스반도체 substrate of mounting a semiconductor device for packaging and method of forming the same
JP2008311538A (en) * 2007-06-18 2008-12-25 Rohm Co Ltd Circuit board, and semiconductor device
JP2010206038A (en) * 2009-03-05 2010-09-16 Fujitsu Ltd Mounting structure of electronic component, and manufacturing method of substrate for mounting electronic component
CN102458039A (en) * 2010-10-18 2012-05-16 上海嘉捷通电路科技有限公司 Thick copper circuit board
JP2019021752A (en) * 2017-07-14 2019-02-07 富士通株式会社 Wiring board, electronic equipment, method of manufacturing wiring board and method of manufacturing electronic equipment

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