KR100575885B1 - substrate of mounting a semiconductor device for packaging and method of forming the same - Google Patents

substrate of mounting a semiconductor device for packaging and method of forming the same Download PDF

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Publication number
KR100575885B1
KR100575885B1 KR1020040033418A KR20040033418A KR100575885B1 KR 100575885 B1 KR100575885 B1 KR 100575885B1 KR 1020040033418 A KR1020040033418 A KR 1020040033418A KR 20040033418 A KR20040033418 A KR 20040033418A KR 100575885 B1 KR100575885 B1 KR 100575885B1
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South Korea
Prior art keywords
solder resist
circuit board
ball
solder
printed circuit
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KR1020040033418A
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Korean (ko)
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KR20050108214A (en
Inventor
하성권
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주식회사 하이닉스반도체
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    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/30—Assembling printed circuits with electric components, e.g. with resistor
    • H05K3/32—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
    • H05K3/34—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by soldering
    • H05K3/341—Surface mounted components
    • H05K3/3431—Leadless components
    • H05K3/3436—Leadless components having an array of bottom contacts, e.g. pad grid array or ball grid array components
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49811—Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads
    • H01L23/49816—Spherical bumps on the substrate for external connection, e.g. ball grid arrays [BGA]
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H05K1/11—Printed elements for providing electric connections to or between printed circuits
    • H05K1/111—Pads for surface mounting, e.g. lay-out
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/30—Assembling printed circuits with electric components, e.g. with resistor
    • H05K3/32—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
    • H05K3/34—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by soldering
    • H05K3/3452—Solder masks

Abstract

반도체 칩 패키지용 회로 기판 및 이의 제조 방법이 개시된다. 인쇄회로기판을 준비한 후, 상기 인쇄회로기판 상에 볼랜드를 형성한다. 그리고, 상기 볼랜드를 갖는 인쇄회로기판 상에 제1솔더 레지스트를 형성한다. 이때, 상기 볼랜드를 노출시키도록 구성한다. 그리고, 상기 제1솔더 레지스트 상에 제2솔더 레지스트를 형성한다. 이때, 상기 제2솔더 레지스트는 상기 볼랜드와 상기 볼랜드를 노출시키는 제1솔더 레지스트의 일부를 노출시키도록 구성한다. 따라서, 상기 볼랜드 상에 솔더볼을 형성하여도 상기 솔더볼이 솔더 레지스트의 측벽에 접촉하는 것을 충분하게 줄일 수 있다.A circuit board for a semiconductor chip package and a method of manufacturing the same are disclosed. After preparing a printed circuit board, a ball land is formed on the printed circuit board. Then, a first solder resist is formed on the printed circuit board having the ball lands. At this time, the borland is configured to expose. Then, a second solder resist is formed on the first solder resist. In this case, the second solder resist is configured to expose the borland and a portion of the first solder resist exposing the borland. Therefore, even if the solder ball is formed on the ball land, the contact of the solder ball to the sidewall of the solder resist can be sufficiently reduced.

Description

반도체 칩 패키지용 회로 기판 및 이의 제조 방법{substrate of mounting a semiconductor device for packaging and method of forming the same}Circuit board for semiconductor chip package and manufacturing method therefor {substrate of mounting a semiconductor device for packaging and method of forming the same}

도 1은 종래의 반도체 칩 패키지용 회로 기판을 개략적으로 나타내는 구성도이다.1 is a configuration diagram schematically showing a circuit board for a conventional semiconductor chip package.

도 2a 내지 도 2c는 본 발명의 일 실시예에 따른 반도체 칩 패키지용 회로 기판의 제조 방법을 나타내는 개략적인 구성도들이다.2A through 2C are schematic diagrams illustrating a method of manufacturing a circuit board for a semiconductor chip package according to an exemplary embodiment of the present invention.

<도면의 주요부분에 대한 부호의 설명><Description of the symbols for the main parts of the drawings>

20 : 인쇄회로기판 22 : 볼랜드20: printed circuit board 22: Borland

24 : 제1솔더 레지스트 26 : 제2솔더 레지스트24: first solder resist 26: second solder resist

28 : 볼랜드28: Borland

본 발명은 반도체 칩 패키지용 회로 기판 및 이의 제조 방법에 관한 것으로서, 보다 상세하게는 볼랜드(ball land)를 노출시키도록 구성된 솔더 레지스트(solder resist)를 갖는 반도체 칩 패키지용 회로 기판 및 이의 제조 방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a circuit board for a semiconductor chip package and a method for manufacturing the same, and more particularly, to a circuit board for a semiconductor chip package having a solder resist configured to expose a ball land, and a method for manufacturing the same. It is about.

최근, 전자 기기는 소형화, 경량화, 고속화, 다기능화 추세에 있고, 이를 실현하기 위한 일환으로 개발된 반도체 칩 패키지의 기술로서 볼 그리드 어레이(ball grid array)가 있다. 상기 볼 그리드 어레이 패키지는 플라스틱 패키지와는 달리 리드 프레임 대신에 인쇄회로기판(PCB)을 사용한다.Recently, electronic devices have become smaller, lighter, faster, and more versatile, and there is a ball grid array as a technology of a semiconductor chip package developed as a part of realizing this. Unlike the plastic package, the ball grid array package uses a printed circuit board (PCB) instead of a lead frame.

도 1을 참조하면, 반도체 칩 패키지용 회로 기판으로서, 인쇄회로기판(10)과, 상기 인쇄회로기판(10) 상에 형성된 볼랜드(12)와, 상기 볼랜드(12)를 노출시키도록 패터닝된 솔더 레지스트(14) 및 상기 볼랜드(12) 상에 형성되는 솔더볼(16)을 포함한다. 이때, 상기 솔더볼(16)은 상기 볼랜드(12)와 결합하는 형태로 형성하는데, 솔더 레지스트(14)의 측벽과도 접촉하는 형태로 형성된다. Referring to FIG. 1, a circuit board for a semiconductor chip package includes a printed circuit board 10, a ball land 12 formed on the printed circuit board 10, and a solder patterned to expose the ball land 12. And a solder ball 16 formed on the resist 14 and the ball land 12. At this time, the solder ball 16 is formed in the form of coupling with the ball land 12, it is formed in the form of contact with the sidewall of the solder resist 14.

이와 같이, 상기 솔더볼(16)의 형성에서 솔더 레지스트(14)의 측벽에도 접촉함으로서 상기 솔더볼(16)을 형성한 후, 온도 사이클과 같은 신뢰성 테스트를 실시할 경우 열팽창 계수 차이에 의해 상기 솔더볼(16)이 손상되는 상황이 빈번하게 발생한다. 그리고, 상기 손상이 발생할 경우 상기 볼랜드(12)와 솔더볼(16)의 결합력이 약화된다.As such, after the solder ball 16 is formed by contacting the sidewalls of the solder resist 14 in the formation of the solder ball 16, when the reliability test such as a temperature cycle is performed, the solder ball 16 may be caused by a difference in thermal expansion coefficient. ) Often occurs. In addition, when the damage occurs, the bonding force between the ball land 12 and the solder ball 16 is weakened.

따라서, 종래의 반도체 칩 패키지용 회로 기판은 볼랜드와 솔더볼의 결합력의 약화로 인한 불량이 빈번하게 발생한다. 특히, 볼랜드와 솔더볼의 결합력의 약화로 전기적 신뢰성이 저하되는 상황이 빈번하게 발생한다.Therefore, in the conventional semiconductor chip package circuit board, defects frequently occur due to a weakening of the bonding force between the ball lands and the solder balls. In particular, a situation in which electrical reliability deteriorates frequently due to a weakening of the bonding force between the borland and the solder ball.

본 발명의 목적은 솔더볼과 접촉되는 부분을 충분하게 감소시킨 솔더 레지스트를 갖는 반도체 칩 패키지용 회로 기판 및 이의 제조 방법을 제공하는데 있다.SUMMARY OF THE INVENTION An object of the present invention is to provide a circuit board for a semiconductor chip package and a method of manufacturing the same, having a solder resist that sufficiently reduces the portion in contact with the solder ball.

상기 목적을 달성하기 위한 본 발명의 반도체 칩 패키지용 회로 기판은,A circuit board for a semiconductor chip package of the present invention for achieving the above object,

인쇄회로기판;Printed circuit board;

상기 인쇄회로기판 상에 형성되는 볼랜드;A ball land formed on the printed circuit board;

상기 볼랜드를 갖는 인쇄회로기판 상에 형성되고, 상기 볼랜드를 노출시키도록 구성된 제1솔더 레지스트; 및A first solder resist formed on the printed circuit board having the ball lands and configured to expose the ball lands; And

상기 제1솔더 레지스트 상에 형성되고, 상기 볼랜드와 상기 볼랜드를 노출시키는 제1솔더 레지스트의 일부를 노출시키도록 페터닝된 제2솔더 레지스트를 포함한다.And a second solder resist formed on the first solder resist and patterned to expose the borland and a portion of the first solder resist that exposes the borland.

상기 볼랜드 상에 형성되는 솔더볼을 더 포함하는 것이 바람직하다.It is preferable to further include a solder ball formed on the ball land.

상기 목적을 달성하기 위한 본 발명의 반도체 칩 패키지용 회로 기판의 제조 방법은,The manufacturing method of the circuit board for semiconductor chip packages of this invention for achieving the said objective is,

인쇄회로기판 상에 볼랜드를 형성하는 단계;Forming a ball land on the printed circuit board;

상기 볼랜드를 갖는 인쇄회로기판 상에 상기 볼랜드를 노출시키도록 제1솔더 레지스트를 형성하는 단계; 및Forming a first solder resist to expose the ball land on a printed circuit board having the ball land; And

상기 볼랜드와 상기 볼랜드를 노출시키는 제1솔더 레지스트의 일부를 노출시키도록 상기 제1솔더 레지스트 상에 제2솔더 레지스트를 형성하는 단계를 포함한다.Forming a second solder resist on the first solder resist to expose the borland and a portion of the first solder resist that exposes the borland.

(실시예)(Example)

이하, 본 발명의 바람직한 실시예를 첨부한 도면에 따라서 더욱 상세히 설명 하기로 한다.Hereinafter, preferred embodiments of the present invention will be described in more detail with reference to the accompanying drawings.

도 2a 내지 도 2c는 본 발명의 일 실시예에 따른 반도체 칩 패키지용 회로 기판의 제조 방법을 나타내는 개략적인 구성도들이다.2A through 2C are schematic diagrams illustrating a method of manufacturing a circuit board for a semiconductor chip package according to an exemplary embodiment of the present invention.

도 2a를 참조하면, 인쇄회로기판(20)를 마련한다. 그리고, 상기 인쇄회로기판(20) 상에 볼랜드(22)를 형성한다. 이때, 상기 볼랜드(22)는 상기 인쇄회로기판(20) 상에 형성된 금속 트레이스 즉, 구리 배선과 전기적으로 연결되는 구조를 갖는다. 그리고, 상기 볼랜드(22)를 갖는 인쇄회로기판(20) 상에 상기 볼랜드(22)를 노출시키도록 패터닝이 이루어진 제1솔더 레지스트(24)를 형성한다.Referring to FIG. 2A, a printed circuit board 20 is provided. Then, the ball land 22 is formed on the printed circuit board 20. At this time, the ball land 22 has a structure that is electrically connected to a metal trace, that is, copper wiring formed on the printed circuit board 20. A first solder resist 24 is formed on the printed circuit board 20 having the ball lands 22 so as to expose the ball lands 22.

도 2b를 참조하면, 상기 제1솔더 레지스트(24) 상에 제2솔더 레지스트(26)를 형성한다. 여기서, 상기 제2솔더 레지스트(26)는 상기 볼랜드(22)를 노출시킴과 아울러 상기 볼랜드(22)를 노출시키는 제1솔더 레지스트(24)의 일부를 노출시키도록 페터닝된다. 이때, 상기 제1솔더 레지스트(24)와 제2솔더 레지스트(26)를 합한 두께는 기존의 단일 구조를 갖는 솔더 레지스트의 두께와 유사하도록 조정하는 것이 바람직하다. Referring to FIG. 2B, a second solder resist 26 is formed on the first solder resist 24. Here, the second solder resist 26 is patterned to expose the borland 22 and to expose a portion of the first solder resist 24 that exposes the borland 22. At this time, the thickness of the sum of the first solder resist 24 and the second solder resist 26 is preferably adjusted to be similar to the thickness of a conventional solder resist having a single structure.

도 2c를 참조하면, 상기 볼랜드(22) 상에 솔더볼(28)을 형성한다. 이와 같이, 상기 볼랜드(22) 상에 솔더볼(28)을 형성하여도 상기 솔더볼(28)이 제1솔더 레지스트(24) 또는 제2솔더 레지스트(26)의 측벽에 접촉하는 면적을 충분하게 줄일 수 있다. 즉, 상기 솔더볼(28)이 접촉하더라도 겨우 제1솔더 레지스트(24)의 측벽에만 접촉하는 것이다.Referring to FIG. 2C, solder balls 28 are formed on the ball lands 22. As such, even when the solder ball 28 is formed on the ball land 22, the area in which the solder ball 28 contacts the sidewalls of the first solder resist 24 or the second solder resist 26 can be sufficiently reduced. have. That is, even if the solder ball 28 contacts, only the sidewalls of the first solder resist 24 are in contact with each other.

이와 같이, 상기 공정을 실시함으로서 인쇄회로기판(20)과, 상기 인쇄회로기 판(20) 상에 형성되는 볼랜드(22)와, 상기 볼랜드(22)를 노출시키도록 패터닝된 제1솔더 레지스트(24) 및 상기 볼랜드(22)와 상기 볼랜드(22)를 노출시키는 제1솔더 레지스트(24)의 일부를 노출시키도록 페터닝된 제2솔더 레지스트(26)를 포함하는 반도체 칩 패키지용 회로 기판을 얻을 수 있다. 그리고, 상기 볼랜드(22) 상에 솔더볼(28)을 형성하여도 솔더 레지스트(24, 26)와 접촉하는 것을 충분하게 줄일 수 있다.As described above, by performing the above process, the printed circuit board 20, the ball land 22 formed on the printed circuit board 20, and the first solder resist patterned to expose the ball land 22 ( 24) and a circuit board for a semiconductor chip package comprising a second solder resist 26 patterned to expose a portion of the first solder resist 24 that exposes the borland 22 and the borland 22. You can get it. In addition, even if the solder ball 28 is formed on the ball land 22, contact with the solder resists 24 and 26 can be sufficiently reduced.

따라서, 본 발명에 의하면 솔더 레지스트와 접촉함으로서 솔더볼이 손상되는 상황을 충분하게 줄일 수 있다. 때문에, 전기적, 기계적 신뢰성의 회복이 가능하다. 그리고, 기존의 공정 라인에서도 충분하게 제조가 가능하기 때문에 생산성에도 지장을 끼치지 않는다.Therefore, according to the present invention, a situation in which the solder ball is damaged by contacting the solder resist can be sufficiently reduced. Therefore, recovery of electrical and mechanical reliability is possible. In addition, since the production can be performed sufficiently in the existing process line, it does not affect productivity.

상기에서는 본 발명의 바람직한 실시예를 참조하여 설명하였지만, 해당 기술 분야의 숙련된 당업자는 하기의 특허 청구의 범위에 기재된 본 발명의 사상 및 영역으로부터 벗어나지 않는 범위내에서 본 발명을 다양하게 수정 및 변경시킬 수 있음을 이해할 수 있을 것이다.Although the above has been described with reference to a preferred embodiment of the present invention, those skilled in the art will be variously modified and changed within the scope of the present invention without departing from the spirit and scope of the invention described in the claims below. I can understand that you can.

Claims (3)

인쇄회로기판;Printed circuit board; 상기 인쇄회로기판 상에 형성되는 볼랜드;A ball land formed on the printed circuit board; 상기 볼랜드를 갖는 인쇄회로기판 상에 형성되고, 상기 볼랜드를 노출시키도록 구성된 제1솔더 레지스트; 및A first solder resist formed on the printed circuit board having the ball lands and configured to expose the ball lands; And 상기 제1솔더 레지스트 상에 형성되고, 상기 볼랜드와 상기 볼랜드를 노출시키는 제1솔더 레지스트의 일부를 노출시키도록 구성된 제2솔더 레지스트를 포함하는 반도체 칩 패키지용 회로 기판.And a second solder resist formed on the first solder resist and configured to expose the borland and a portion of the first solder resist that exposes the borland. 제1항에 있어서, 상기 볼랜드 상에 형성되는 솔더볼을 더 포함하는 것을 특징으로 하는 반도체 칩 패키지용 회로 기판.The circuit board of claim 1, further comprising solder balls formed on the ball lands. 인쇄회로기판 상에 볼랜드를 형성하는 단계;Forming a ball land on the printed circuit board; 상기 볼랜드를 갖는 인쇄회로기판 상에 상기 볼랜드를 노출시키도록 제1솔더 레지스트를 형성하는 단계; 및Forming a first solder resist to expose the ball land on a printed circuit board having the ball land; And 상기 볼랜드와 상기 볼랜드를 노출시키는 제1솔더 레지스트의 일부를 노출시키도록 상기 제1솔더 레지스트 상에 제2솔더 레지스트를 형성하는 단계를 포함하는 반도체 칩 패키지용 회로 기판의 제조 방법.Forming a second solder resist on the first solder resist to expose the borland and a portion of the first solder resist that exposes the borland.
KR1020040033418A 2004-05-12 2004-05-12 substrate of mounting a semiconductor device for packaging and method of forming the same KR100575885B1 (en)

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KR102434435B1 (en) * 2015-10-26 2022-08-19 삼성전자주식회사 Printed circuit board and semiconductor package having the same

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH08335781A (en) * 1995-06-06 1996-12-17 Ibiden Co Ltd Multilayer printed wiring board
JPH09232736A (en) * 1996-02-27 1997-09-05 Ibiden Co Ltd Printed wiring board
JPH09326412A (en) * 1996-06-07 1997-12-16 Tokuyama Corp Mounting solder ball
JP2000277898A (en) 1999-03-24 2000-10-06 Nippon Avionics Co Ltd Board for mounting of ball grid array package
JP2001230339A (en) 2000-02-18 2001-08-24 Nec Corp Semiconductor device

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* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH08335781A (en) * 1995-06-06 1996-12-17 Ibiden Co Ltd Multilayer printed wiring board
JPH09232736A (en) * 1996-02-27 1997-09-05 Ibiden Co Ltd Printed wiring board
JPH09326412A (en) * 1996-06-07 1997-12-16 Tokuyama Corp Mounting solder ball
JP2000277898A (en) 1999-03-24 2000-10-06 Nippon Avionics Co Ltd Board for mounting of ball grid array package
JP2001230339A (en) 2000-02-18 2001-08-24 Nec Corp Semiconductor device

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