KR101061175B1

KR101061175B1 - Semiconductor Package Substrate

Info

Publication number: KR101061175B1
Application number: KR20080014586A
Authority: KR
Inventors: 박신영; 하성권
Original assignee: 주식회사 하이닉스반도체
Priority date: 2008-02-18
Filing date: 2008-02-18
Publication date: 2011-09-01
Also published as: KR20090089175A

Abstract

A semiconductor package substrate according to the present invention, the insulating layer; A circuit pattern formed on one surface of the insulating layer; A dummy pattern formed on the other surface of the insulating layer to prevent bending; And a solder mask formed on one surface and the other surface of the insulating layer including the circuit pattern and the dummy pattern.

Description

Substrate for semiconductor package

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor package substrate, and more particularly, to a semiconductor package substrate capable of preventing warpage.

In the semiconductor industry, packaging technology for integrated circuits is continuously developed to meet the demand for miniaturization and mounting reliability.

For example, the demand for miniaturization is accelerating the development of technologies for packages close to chip size, and the demand for mounting reliability highlights the importance of packaging technologies that can improve the efficiency of mounting operations and the mechanical and electrical reliability after mounting. I'm making it.

One example of miniaturization of the package is a ball grid array (BGA) package. The BGA package has an overall package size that is substantially the same as or similar to that of a semiconductor chip. In particular, as the solder ball is provided, the BGA package is provided as an electrical connection means to the outside, that is, a mounting means on a printed circuit board. This has the advantage that it can be very advantageously applied to the trend that the mounting area is decreasing.

In addition, in recent years, the micro pitch of signal / power input / output pins is increased due to the high integration of semiconductor chips, and the FBGA (Fine) has the advantage of reducing signal transmission paths by reducing the mounting area and making electrical connections with external circuits by solder balls. pitch Ball Grid Array) package is widely used.

On the other hand, the substrate for forming the FBGA package is provided on the one surface only for the external connection terminal such as solder ball and the portion for the electrical connection, such as a connection pad.

The substrate in which the electrical connection portions are formed on only one surface thereof does not require a portion such as a via hole, compared to the substrate in which the electrical connection portions are formed on both surfaces thereof, thereby simplifying the manufacturing process, thereby reducing design and manufacturing time and cost.

However, since the substrate for forming the FBGA is formed only on one surface for the electrical connection, warpage occurs in the substrate.

1 is a view for explaining the warpage occurring in the conventional substrate for FBGA package.

As shown, the FBGA package substrate 100 has a window 140 in the center, the metal pattern 120 is formed only on one surface of the insulating layer 110, the insulating layer including the metal pattern 120 It includes a solder mask 130 formed on each of the upper and lower surfaces of the (110).

However, the FBGA package substrate 100 in which the metal pattern 120 is formed on only one surface of the FBGA package substrate is warped due to heat generated during the process of forming the semiconductor package.

That is, the insulating layer 110, the metal pattern 120, and the solder mask 130 constituting the FBGA package substrate 100 have different thermal expansion coefficients, and thus, only one surface of the substrate 100. When the metal pattern 120 is formed, the degree of expansion and compression of each component generated on both sides of the substrate 100 during the process is changed.

Accordingly, warpage occurs in the substrate 100 according to the degree of expansion and compression on one surface and the other surface, and the warpage makes the semiconductor package process difficult and causes reliability problems of the semiconductor package.

The present invention provides a substrate for a semiconductor package that can prevent warpage.

The dummy pattern is made of a metal having the same thermal expansion coefficient as the circuit pattern.

The dummy pattern has the same area as the circuit pattern.

The dummy pattern has the same thickness as the circuit pattern.

The dummy pattern has a mirror shape with the circuit pattern.

The dummy pattern has a mirror shape with the circuit pattern and has the same thermal expansion coefficient, area, and thickness as the circuit pattern.

The dummy pattern has a different area to compensate for the warpage and the coefficient of thermal expansion different from the circuit pattern.

The dummy pattern has a different thickness to compensate for the warpage and the coefficient of thermal expansion different from the circuit pattern.

The dummy pattern has a different shape to compensate for the thermal expansion coefficient and the warpage different from the circuit pattern.

The dummy pattern may have any one of a plurality of spaced apart circular or square shapes and a polygonal shape including a bar shape.

The present invention provides a semiconductor package substrate by forming a dummy pattern made of metal on the other surface of the semiconductor package substrate having a circuit pattern formed on only one surface thereof so as to correspond to the density of the circuit pattern formed on the surface of the semiconductor package substrate. Prevents warpage from occurring

In addition, compared to the semiconductor package substrate having a pattern electrically connected to both sides, a pattern density can be obtained without performing a drilling process, etc., thereby reducing the time and cost of manufacturing the substrate.

In addition, since the shape of the dummy pattern may be variously changed as necessary, the warpage generated in the semiconductor package substrate may be minimized.

The present invention includes forming a dummy pattern on the other surface of the substrate in order to prevent warpage caused by heat in the semiconductor package substrate having a circuit pattern formed on only one surface of the semiconductor package manufacturing process.

That is, the present invention forms a dummy pattern made of the same metal as the density of the circuit pattern formed on the one surface on the other surface of the substrate for a semiconductor package in which the circuit pattern is formed on only one surface, thereby adjusting the balance of the amount of physical change that is bent by heat to the semiconductor package. This is to prevent warpage occurring in the substrate for the use.

Accordingly, the present invention is easy to design and process the dummy pattern formation surface without proceeding the drilling process for electrical connection as compared to the conventional semiconductor package substrate having a pattern electrically connected to both sides, Compared to a semiconductor package substrate, manufacturing time and cost can be reduced.

In addition, the shape of the dummy pattern may be variously changed as necessary, thereby minimizing warpage generated in the semiconductor package substrate.

<Example>
Hereinafter, a semiconductor package substrate according to an embodiment of the present invention will be described in detail.

2A and 2B are plan views illustrating a substrate for a semiconductor package according to an exemplary embodiment of the present invention, FIG. 3 is a cross-sectional view taken along line AA ′ of FIGS. 2A and 2B, and FIGS. 4A to 4D illustrate the present invention. Fig. Is a plan view showing a dummy pattern of the substrate for semiconductor package according to the embodiment.

2A, 2B, and 3, the semiconductor package substrate 200 according to the present invention is for electrical connection with a semiconductor chip on one surface of an insulating layer 210 having a window 240 in the center thereof. And a circuit pattern 220 to which external connection terminals such as a connection pad and a solder ball are attached.

In addition, the semiconductor package substrate 200 according to the present invention is disposed on the other surface of the insulating layer 210 has a structure that is symmetrical with the circuit pattern 220 to prevent the warpage caused by heat during the process and In addition, the circuit pattern 220 includes a dummy pattern 250 that is electrically separated from the circuit pattern 220.

Furthermore, the semiconductor package substrate 200 according to the present invention includes a solder mask 230 formed on one surface and the other surface of the insulating layer including the circuit pattern 220 and the dummy pattern 250.

In detail, as shown in FIG. 3, the semiconductor package substrate 200 according to the present invention includes an insulating layer 210 having a window 240 in a central portion thereof, and a circuit pattern formed on one surface of the insulating layer 210. 220 and a dummy mask formed on the other surface of the insulating layer 210 and a solder mask formed on one surface and the other surface of the insulating layer 210 including the circuit pattern 220 and the dummy pattern 250, respectively ( 230).

The dummy pattern 250 is for a semiconductor package generated when the insulating layer 210, the circuit pattern 220, and the solder mask 230 forming the semiconductor package substrate 200 have different thermal expansion coefficients. It is formed to prevent bending of the substrate 200.

That is, the semiconductor package substrate 200 according to the present invention forms the dummy pattern 250 corresponding to the circuit pattern 220 formed on the one surface on the other surface, thereby expanding and compressing each component part generated on one surface and the other surface. Maintain similar accuracy to minimize warpage.

The dummy pattern 250 is formed of the same metal material as the circuit pattern 220 or made of a metal material having the same thermal expansion coefficient as the circuit pattern 220 in order to prevent bending of the semiconductor package substrate 200. Is formed. In addition, the dummy pattern 250 is preferably formed to have a mirror shape with the circuit pattern 220.
The dummy pattern 250 may be formed to have a different shape from that of the circuit pattern 220. In this case, in order to prevent bending of the substrate 200 for a semiconductor package, the dummy pattern 250 may include the circuit pattern ( 220 and the same area and thickness.

In addition, the dummy pattern 250 may be formed of a metal material having a thermal expansion coefficient different from that of the circuit pattern 220. In this case, in order to prevent bending of the substrate 200 for a semiconductor package, the dummy pattern 250 may be formed. May be formed in a different form from the circuit pattern 220 or may have a different area or thickness.

The dummy pattern 250 formed on the other surface of the semiconductor package substrate 200 having the window 240 may have a plurality of rectangular shapes 250-1 spaced apart from each other, as shown in FIGS. 4A to 4D. A circular shape 250-2, a bar shape 250-3 formed to be spaced apart in one direction, and a disordered shape 250-4 are arranged and sealed by the solder mask 230.

As described above, the present invention, by forming a dummy pattern made of the same metal as the density of the circuit pattern formed on the one surface on the other surface of the substrate for a semiconductor package in which the circuit pattern is formed on only one surface, to adjust the balance of the amount of physical change bent by heat This prevents warpage from occurring in the semiconductor package substrate.

In addition, the present invention can obtain a corresponding effect without performing a drilling process and the like compared to the substrate for a semiconductor package having a pattern electrically connected to both sides can reduce the production time and cost of the substrate.

In addition, according to the present invention, the shape of the dummy pattern may be variously changed as necessary, thereby minimizing warpage generated in the semiconductor package substrate.

As mentioned above, although the present invention has been illustrated and described with reference to specific embodiments, the present invention is not limited thereto, and the following claims are not limited to the scope of the present invention without departing from the spirit and scope of the present invention. It can be easily understood by those skilled in the art that can be modified and modified.

BRIEF DESCRIPTION OF THE DRAWINGS The figure for demonstrating the bending which arises in the board | substrate for conventional FBGA packages.

2A and 2B are plan views illustrating a substrate for a semiconductor package according to an embodiment of the present invention.

3 is a cross-sectional view taken along the line AA ′ of FIGS. 2A and 2B;

4A to 4D are plan views illustrating dummy patterns of a substrate for a semiconductor package according to an embodiment of the present invention.

Claims

Insulating layer;

A circuit pattern formed on one surface of the insulating layer;

A dummy pattern formed on the other surface of the insulating layer to prevent bending; And

A solder mask formed on one surface and the other surface of the insulating layer including the circuit pattern and the dummy pattern;

A substrate for a semiconductor package comprising a.

Claim 2 has been abandoned due to the setting registration fee.

The method of claim 1,

The dummy pattern is a semiconductor package substrate, characterized in that made of a metal having the same thermal expansion coefficient as the circuit pattern.

Claim 3 was abandoned when the setup registration fee was paid.

The method of claim 2,

The dummy pattern has the same area as the circuit pattern.

Claim 4 was abandoned when the registration fee was paid.

The method of claim 2,

The dummy pattern has the same thickness as the circuit pattern.

Claim 5 was abandoned upon payment of a set-up fee.

The method of claim 2,

The dummy pattern has a mirror shape with the circuit pattern.

Claim 6 was abandoned when the registration fee was paid.

The method of claim 1,

Claim 7 was abandoned upon payment of a set-up fee.

The method of claim 1,

And the dummy pattern has a different area to compensate for the thermal expansion coefficient and the warpage different from the circuit pattern.

Claim 8 was abandoned when the registration fee was paid.

The method of claim 1,

And the dummy pattern has a different thickness to compensate for the thermal expansion coefficient and the warpage different from the circuit pattern.

Claim 9 was abandoned upon payment of a set-up fee.

The method of claim 1,

Wherein the dummy pattern has a different shape to compensate for the thermal expansion coefficient and the warpage different from the circuit pattern.

Claim 10 was abandoned upon payment of a setup registration fee.

The method of claim 1,

The dummy pattern is a semiconductor package substrate, characterized in that any one of a plurality of spaced apart form of a circle or quadrangle, including the shape of a polygon (Bar).