WO2017200174A1

WO2017200174A1 - Insulating substrate using thick film printing technique

Info

Publication number: WO2017200174A1
Application number: PCT/KR2016/015263
Authority: WO
Inventors: 구도현; 장혁; 김성태
Original assignee: 엘지전자(주)
Priority date: 2016-05-18
Filing date: 2016-12-26
Publication date: 2017-11-23

Abstract

Disclosed is an insulating substrate using a thick film printing technique. A power semiconductor package of the present invention comprises: a first metal layer; a ceramic substrate disposed on the first metal layer; and a second metal layer which has at least one pattern formed thereon and is arranged on the ceramic substrate, wherein a volume of the first metal layer is at least 85% to at most 105% of that of the second metal layer. According to the present invention, volumes of the upper and lower layers of the ceramic substrate are the same or similar, and thus the difference in thermal stress applied to the ceramic substrate can be reduced.

Description

Insulation Board Using Thick Film Printing Technique

The present invention relates to an insulating substrate using a thick film printing technique, and more particularly, to the insulating substrate which can reduce the thermal stress difference received by the ceramic substrate during the manufacturing process of the insulating substrate because the volume of the upper and lower layers of the ceramic substrate is the same or similar. It is about.

The power semiconductor may perform control processing such as DC / AC conversion, voltage, and frequency change in order to utilize electrical energy. Power semiconductors perform various functions at various stages, from producing (generating) power to using (service). In particular, in the use stage, it is used as a key component that determines the operation and performance of the electric products such as home appliances, smart phones, automobiles.

Since the insulating substrate using the thick film printing method for manufacturing a power semiconductor repeats the sintering and cooling processes, there is a problem in that the substrate is bent or peeled off due to the thermal stress difference between the constituent materials.

It is an object of the present invention to solve the above and other problems. Another object is to provide an insulating substrate which can reduce the thermal stress difference received by the ceramic substrate during the manufacturing process of the insulating substrate.

According to an aspect of the present invention to achieve the or another object, a base, a first metal layer located on the base, a ceramic substrate located on the first metal layer, and at least one pattern formed on the ceramic substrate And a second metal layer, wherein the volume of the first metal layer is 85% or more and 105% or less of the volume of the second metal layer.

The first metal layer may have the same pattern as the second metal layer.

The first metal layer may have a pattern different from that of the second metal layer.

The first metal layer may have the same thickness as the second metal layer.

The thickness of the first metal layer may be thinner than the thickness of the second metal layer.

The first and second metal layers may include copper or nickel plated copper.

The ceramic substrate may include at least one of a low temperature co-fired ceramic (LTCC) high temperature co-fired ceramic (HTCC), and aluminum nitride (AIN).

Referring to the effect of the insulating substrate according to the present invention.

According to at least one of the embodiments of the present invention, since the volume of the upper and lower layers of the ceramic substrate is similar, the thermal stress difference received by the ceramic substrate during the insulating substrate manufacturing process may be reduced.

Further scope of the applicability of the present invention will become apparent from the following detailed description. However, various changes and modifications within the spirit and scope of the present invention can be clearly understood by those skilled in the art, and therefore, specific embodiments, such as the detailed description and the preferred embodiments of the present invention, should be understood as given by way of example only.

1 is a view showing a power semiconductor package according to an embodiment of the present invention.

2 to 13 are views illustrating an insulating substrate according to an embodiment of the present invention.

Hereinafter, embodiments of the present disclosure will be described in detail with reference to the accompanying drawings, and the same or similar components are denoted by the same reference numerals regardless of the reference numerals, and redundant description thereof will be omitted. The suffixes "module" and "unit" for components used in the following description are given or used in consideration of ease of specification, and do not have distinct meanings or roles from each other. In addition, in describing the embodiments disclosed herein, when it is determined that the detailed description of the related known technology may obscure the gist of the embodiments disclosed herein, the detailed description thereof will be omitted. In addition, the accompanying drawings are intended to facilitate understanding of the embodiments disclosed herein, but are not limited to the technical spirit disclosed herein by the accompanying drawings, all changes included in the spirit and scope of the present invention. It should be understood to include equivalents and substitutes.

Terms including ordinal numbers such as first and second may be used to describe various components, but the components are not limited by the terms. The terms are used only for the purpose of distinguishing one component from another.

When a component is referred to as being "connected" or "connected" to another component, it may be directly connected to or connected to that other component, but it may be understood that other components may be present in between. Should be. On the other hand, when a component is said to be "directly connected" or "directly connected" to another component, it should be understood that there is no other component in between.

Singular expressions include plural expressions unless the context clearly indicates otherwise.

In this application, the terms "comprises" or "having" are intended to indicate that there is a feature, number, step, operation, component, part, or combination thereof described in the specification, and one or more other features. It is to be understood that the present invention does not exclude the possibility of the presence or the addition of numbers, steps, operations, components, components, or a combination thereof.

As shown in FIG. 1, the power semiconductor package 100 according to the present invention includes a base 110, a first metal layer 120, a ceramic substrate 130, a second metal layer 140, and a semiconductor sequentially stacked. Chip 150 may be included.

The base 110 may include a metal material. For example, the base 110 may include at least one of copper, nickel plated copper, aluminum silicon carbide (AlSiC), or copper molybdenum alloy (Cu / Mo alloy). The base 110 may mount at least one ceramic substrate 130. Accordingly, the area of the base 110 may be wider than other layers. Since the base 110 includes a metal material having high thermal conductivity, it may be helpful for heat dissipation.

The first metal layer 120 may be located on one surface of the base 110. The first metal layer 120 may be coupled to the base 110 through the lower solder 132. The first metal layer 120 may include a material having excellent electrical conductivity. The first metal layer 120 may include copper or nickel plated copper. The first metal layer 120 may transfer heat generated from the upper portion to the base 110.

The ceramic substrate 130 may be located on one surface of the first metal layer 120. The ceramic substrate 130 may have an insulating property so that the semiconductor chip 150 and the base 110 do not flow electricity. In addition, the ceramic substrate 130 may include a material having high thermal conductivity in order to transfer heat generated from the upper portion to the base 110. For example, the ceramic substrate 130 may include at least one of low temperature co-fired ceramic (LTCC), high temperature co-fired ceramic (HTCC), and aluminum nitride (AIN).

The second metal layer 140 may be located on one surface of the ceramic substrate 130. The second metal layer 140 may be positioned with a pattern on at least a portion of the ceramic substrate 130. The second metal layer 140 may include a material having high conductivity and good heat dissipation. The second metal layer 140 may include the same or similar material as the first metal layer 140. For example, the second metal layer 140 may include copper or copper plated with nickel.

The semiconductor chip 150 may be located on one surface of the second metal layer 140. The semiconductor chip 150 may be directly coupled to the second metal layer 140 or may be coupled through the wire 117. When the semiconductor chip 150 is directly coupled to the second metal layer 140, the semiconductor chip 150 may be coupled through the upper solder 134.

The semiconductor chip 150 may include a high power chip 152 and a low power chip 154. For example, the high power chip 152 may be an insulated gate bipolar transistor (IGBT) that is a power device, and the low power chip 154 may be a diode that is a control device.

The frame 160 may protrude upward from surrounding the side of the base 110. The frame 160 may function to protect the semiconductor chip 150. The frame 160 may include an insulating material because the lead 170 connecting the inside and the outside of the power semiconductor package 100 is located therein.

The lid 170 may be fixed inside the frame 160. Both ends of the lid 170 may protrude to the outside of the frame 160. One end of the lead 170 may protrude into the power semiconductor package 100, and the other end of the lead 170 may protrude to the outside of the power semiconductor package 100. The lead 170 may electrically connect the second metal layer 140 to the outside. Accordingly, the lead 170 may include a material having high electrical conductivity. For example, the lead 170 may include at least one of gold, silver, copper, or nickel.

The mold 180 may be filled in the frame 160. The mold 180 may fix the semiconductor chip 150, the ceramic substrate 130, and the like located in the power semiconductor package 100. In addition, the mold 170 may protect the semiconductor chip 150, the ceramic substrate 130, and the like located in the power semiconductor package 100 from an external shock. Accordingly, the mold 180 may be formed to the upper surface of the semiconductor chip 150. For example, the mold 180 may comprise an epoxy mold compound (EMC) or a silicone gel.

The cover 190 may be located above the mold 180 to protect the power semiconductor package 100 from an external impact. Since the cover 190 may contact the lid 170, the cover 190 may include an insulating material.

2 to 13 are views illustrating an insulating substrate of a power semiconductor package according to an embodiment of the present invention.

As shown in FIG. 2, the first metal layer 120 is positioned on one surface of the ceramic substrate 130, and the second metal layer 140 may be formed on the other surface opposite thereto. As described above, the second metal layer 140 may have a pattern formed thereon.

The ceramic substrate 130 may be formed using any one of a direct bonded copper (DBC) method, a direct plated copper (DPC) method, an active metal method (AMC, active metal brazed copper), or a metallizing method. 120, 140 may be deposited.

In the case of using the DBC method, after forming an oxide film (for example, aluminum oxide) on the ceramic substrate 130, the second metal layer 140 may be deposited. For example, the thickness of the deposited second metal layer 140 may be about 300 μm. Thereafter, the second metal layer 140 may be sintered. For example, the sintering temperature may be about 1700 degrees. Thereafter, a pattern may be formed on the second metal layer 140 using an etching process.

On the other hand, in the case of using the metallizing method, a material (for example, a paste in which a glass binder is mixed with tungsten, molybdenum, copper, etc.) of the second metal layer 140 is thinly patterned on the ceramic substrate 130. You can print. Thereafter, the printed material can be sintered. For example, the sintering temperature may be about 900 degrees. Thereafter, the material included in the second metal layer 140 may be printed on the sintered material in a pattern.

The metallizing method can be low in cost because the sintering temperature is low by DBC method. In addition, an etching process is not required separately and the process can be simplified.

As shown in FIG. 3A, in the conventional power semiconductor package 100, the thickness MLD1 of the first metal layer 120 and the thickness MLD2 of the second metal layer 140 may be the same or similar. have. In this case, volumes of the first metal layer 120 and the second metal layer 140 may be different from each other by the pattern of the second metal layer 140.

In this case, even if the thermal expansion coefficients of the first metal layer 120 and the second metal layer 140 are the same, the volume may be different, and thus the stress applied to the ceramic substrate 130 may vary according to temperature change.

As described above, such a temperature change may occur rapidly by the sintering and cooling processes of the first and

second metal layers

120 and 140. That is, it means that irregular stress may be applied to the ceramic substrate 130 up and down.

Accordingly, if the sintering and cooling processes are repeated when the first and

second metal layers

120 and 140 are deposited, as shown in FIG. 3 (b), bent to one side or shown in FIG. 3 (c). As described above, there is a problem that cracks may be formed in the ceramic substrate 130.

As shown in FIG. 4, in the power semiconductor package 100 according to an exemplary embodiment, the thickness MLD1 of the first metal layer 120 may be different from the thickness MLD2 of the second metal layer 140. . For example, the thickness MLD1 of the first metal layer 120 may be thinner than the thickness MLD2 of the second metal layer 140.

In this case, the volume of the first metal layer 120 and the second metal layer 140 may be the same or similar. Accordingly, the ceramic substrate 130 may have the same or similar thermal stress due to temperature change at both sides. That is, the thermal stresses are canceled with each other to prevent the ceramic substrate 130 from bending or breaking. For example, the volume of the first metal layer 120 may be 85% or more and 105% or less of the volume of the second metal layer 140.

As shown in FIG. 5, in the power semiconductor package 100 according to another exemplary embodiment, a pattern may be formed on the first metal layer 120 like the second metal layer 140. In this case, the thickness MLD1 of the first metal layer 120 and the thickness MLD2 of the second metal layer 140 may be the same or similar.

Although the thicknesses of the first metal layer 120 and the second metal layer 140 are similar, a pattern is formed on the first metal layer 120 so that the first metal layer 120 and the second metal layer 140 have the same volume. May be similar. For example, the volume of the first metal layer 120 may be 85% or more and 105% or less of the volume of the second metal layer 140. Accordingly, the thermal stress that the ceramic substrate 130 receives from both sides may be the same or similar. That is, the thermal stresses are canceled with each other to prevent the ceramic substrate 130 from bending or breaking.

As shown in FIG. 6, in the power semiconductor package 100 according to another exemplary embodiment, a pattern in which the first metal layer 120 is different from the second metal layer 140 may be formed. In this case, the thickness MLD1 of the first metal layer 120 and the thickness MLD2 of the second metal layer 140 may be the same or similar. However, the present invention is not limited thereto, and the thickness MLD1 of the first metal layer 120 and the thickness MLD2 of the second metal layer 140 may be different according to the pattern formed on the first metal layer 120.

Although the pattern of the first metal layer 120 is different from the pattern of the second metal layer 140, the first metal layer 120 may have the same volume or the same volume as the second metal layer 140 due to the formation of the pattern. For example, the volume of the first metal layer 120 may be 85% or more and 105% or less of the volume of the second metal layer 140. Accordingly, the thermal stress that the ceramic substrate 130 receives from both sides may be the same or similar. That is, the thermal stresses are canceled with each other to prevent the ceramic substrate 130 from bending or breaking.

As shown in FIG. 7, after depositing the first and

second metal layers

120 and 140 on the ceramic substrate 130, the semiconductor chip 150 and the wire 117 are deposited on the second metal layer 140. can do.

The semiconductor chip 150 may attach the semiconductor chip 150 and the second metal layer 140 through the upper solder 134. The semiconductor chip 150 may be electrically connected to the second metal layer 140 through the wire 117.

As shown in FIG. 8, in the power semiconductor package 100 according to the existing invention, a buffer layer 146 may be located between the second metal layer 140 and the semiconductor chip 150. Since the second metal layer 140 and the semiconductor chip 150 have a large difference in coefficient of thermal expansion, cracks may be formed or bent by thermal stress if the sintering and cooling processes are repeated. Accordingly, a thermal expansion coefficient higher than the second metal layer 140 and lower than the semiconductor chip 150 may be disposed between the two layers to prevent thermal stress.

However, when the buffer layer 146 is located, the first upper solder 134a is required to attach the buffer layer 146 on the second metal layer 140, and the semiconductor chip 150 may be attached to the buffer layer. 2 upper solder 134b may be required. In other words, a soldering process may be further added to manufacture the power semiconductor package. Accordingly, there is a problem that the manufacturing process of the power semiconductor package can be complicated and the cost can be increased.

In addition, when the second upper solder 134b and the buffer layer 146 are positioned, there is a problem that electrical and thermal performance of the power semiconductor package may be deteriorated because current and heat transfer paths become longer.

In contrast, as shown in FIG. 9, in the power semiconductor package 100 according to the present invention, the second metal layer 140 may include a plurality of printed metal layers. For example, the second metal layer 140 may include first to sixth printed

metal layers

140a and 140f. The first to sixth printed metal layers 140a to 140f may be sequentially stacked on the ceramic substrate 130. The first to sixth printed metal layers 140a to 140f may have different thermal expansion coefficients.

For example, as the printed metal layer moves from the first printed metal layer 140a to the sixth printed metal layer 140f, the content of the glass frit may increase in the copper. That is, the upper portion of the printed metal layer means that the content of the glass frit may be greater than the printed metal layer located below. The glass frit may help copper to adhere easily to the ceramic substrate 130.

Since the glass frit has a smaller thermal expansion coefficient than copper, the larger the glass frit content in the first to sixth printed metal layers 140a to 140f, the smaller the thermal expansion coefficient. Accordingly, the coefficient of thermal expansion may become smaller from the first printed metal layer 140a to the sixth printed metal layer 140f. That is, it means that the thermal expansion coefficient of the second metal layer 140 may be smaller toward the top.

Accordingly, the sixth printed metal layer 140f adjacent to the semiconductor chip 150 has a small difference in thermal expansion coefficient, thereby preventing the chip from bending or breaking due to thermal stress.

In the drawings, only the first to sixth printed metal layers 140a to 140f are illustrated, but the present invention is not limited thereto and may have various layers according to a manufacturing process.

A TPC process may be used to print the first to sixth printed metal layers 140a to 140f on the ceramic substrate 130. First, the first printed metal layer 140a having a high copper content may be printed on the ceramic substrate 130 and then sintered. Thereafter, each layer having a higher content of the glass component may be sequentially printed and then dried. Thereafter, up to the sixth printed metal layer 140f may be printed and sintered.

As described above in FIG. 2, the TPC process may be low in cost because of a low sintering temperature and the process may be simplified since no etching process is required. In addition, since the second metal layer 140 includes the first to sixth printed metal layers 140a to 140f, the buffer layer 146 is not necessary, thereby simplifying the process and reducing the cost. In addition, since the buffer layer 146 is not located, the current path and the heat transfer path may be shortened, thereby improving electrical and thermal performance of the power semiconductor package.

As illustrated in FIG. 10, the semiconductor chip 150 may be attached onto the second metal layer 140, and then the first metal layer 120 may be attached onto the base 110. The first metal layer 120 may be attached to the base 110 through the lower solder 132. The bonding process of the first metal layer 120 and the base 110 may be the same as or similar to the bonding process of the second metal layer 140 and the semiconductor chip 150.

Thereafter, as shown in FIG. 11, the frame 160 including the lid 170 may be coupled to the side of the base 110. For example, the frame 160 and the base 110 may be coupled through a screw.

The lead 170 may connect the second metal layer 140 to the outside through the wire 117.

Thereafter, as shown in FIG. 12, the mold 180 may be filled in the frame 160. As described above, the mold 180 may be filled up to an upper surface of the semiconductor chip 150 to protect the semiconductor chip 150 and the ceramic substrate 130.

Finally, as shown in FIG. 13, the power semiconductor package 100 may be completed by covering the cover 190 on the mold 180. The cover 190 may be combined with the frame 160.

The above detailed description should not be construed as limiting in all respects but should be considered as illustrative. The scope of the invention should be determined by reasonable interpretation of the appended claims, and all changes within the equivalent scope of the invention are included in the scope of the invention.

Claims

A first metal layer;

A ceramic substrate on the first metal layer; And

A second metal layer having at least one pattern formed on the ceramic substrate;

An insulating substrate having a volume of the first metal layer is 85% or more and 105% or less of the volume of the second metal layer.
The method of claim 1,

The first metal layer,

An insulating substrate having the same pattern as the second metal layer.
The method of claim 1,

The first metal layer,

An insulating substrate having a pattern different from that of the second metal layer.
The method of claim 1,

The first metal layer,

A power insulating substrate having the same thickness as the second metal layer.
The method of claim 1,

The thickness of the first metal layer,

An insulating substrate thinner than the thickness of the second metal layer.
The method of claim 1,

The first and second metal layers,

An insulating substrate comprising copper or nickel plated copper.
The method of claim 1,

The ceramic substrate,

An insulating substrate comprising at least one of Low Temperature Co-Fired Ceramic (LTCC), High Temperature Co-Fired Ceramic (HTCC), and Aluminum Nitride (AIN).