WO2021235721A1 - Method for manufacturing ceramic circuit board - Google Patents

Method for manufacturing ceramic circuit board Download PDF

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Publication number
WO2021235721A1
WO2021235721A1 PCT/KR2021/005346 KR2021005346W WO2021235721A1 WO 2021235721 A1 WO2021235721 A1 WO 2021235721A1 KR 2021005346 W KR2021005346 W KR 2021005346W WO 2021235721 A1 WO2021235721 A1 WO 2021235721A1
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WIPO (PCT)
Prior art keywords
layer
copper
warpage
paste
circuit board
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PCT/KR2021/005346
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French (fr)
Korean (ko)
Inventor
김민수
배일석
박진수
Original Assignee
주식회사 코멧네트워크
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Application filed by 주식회사 코멧네트워크 filed Critical 주식회사 코멧네트워크
Priority to CN202180035176.9A priority Critical patent/CN115606322A/en
Publication of WO2021235721A1 publication Critical patent/WO2021235721A1/en

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    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/10—Apparatus or processes for manufacturing printed circuits in which conductive material is applied to the insulating support in such a manner as to form the desired conductive pattern
    • H05K3/12—Apparatus or processes for manufacturing printed circuits in which conductive material is applied to the insulating support in such a manner as to form the desired conductive pattern using thick film techniques, e.g. printing techniques to apply the conductive material or similar techniques for applying conductive paste or ink patterns
    • H05K3/1283—After-treatment of the printed patterns, e.g. sintering or curing methods
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H05K1/0271—Arrangements for reducing stress or warp in rigid printed circuit boards, e.g. caused by loads, vibrations or differences in thermal expansion
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H05K1/03—Use of materials for the substrate
    • H05K1/0306—Inorganic insulating substrates, e.g. ceramic, glass
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H05K1/09—Use of materials for the conductive, e.g. metallic pattern

Definitions

  • the present invention relates to a method of manufacturing a ceramic circuit board, and more particularly, to a method of manufacturing a ceramic circuit board used as a substrate for a power semiconductor.
  • Power semiconductors which are widely used in mobiles, home appliances, and automobiles, play a role in converting, processing, and controlling power.
  • substrates on which they are mounted include Al 2 O 3 , AlN, Zirconia Toughened Alumina (ZTA), Si 3 N 4 , etc.
  • a substrate made of a ceramic material is used. Ceramics such as Al 2 O 3 , AlN, ZTA, and Si 3 N 4 have high insulation, mechanical strength, and relatively high heat dissipation performance, so they are suitable as substrates for high-power power semiconductors.
  • the ceramic circuit board should have a conductive pattern formed on the ceramic substrate. As the conductive pattern, an Al or Cu pattern is mainly used.
  • DBC Direct Bonded Copper
  • AMB Active Metal Brazing Copper
  • DPC Direct Plating Copper
  • DBC technology is a method of manufacturing a ceramic circuit board by bonding copper foil to one or both sides of a ceramic through a high-temperature oxidation process and then patterning the copper foil.
  • a copper-oxygen process eutectic is used to bond the substrate and the copper foil. Bonding is performed in a nitrogen atmosphere containing about 30 ppm oxygen at a temperature of 1083° C. or less, which is the melting point of copper.
  • the DBC method uses an etching process to form a bonded copper foil in a uniform pattern. After etching, Ni, Ag and Au are plated on the surface of the Cu pattern.
  • DBC technology has the advantage of good mechanical strength and adhesion.
  • a pattern that can be formed through etching is limited, and pores exist on the junction surface where copper oxide is not generated, thereby reducing stability to thermal cycles.
  • AMB technology joins ceramic and copper foil by sandwiching an active metal alloy whose melting point is lowered by adding Cu, Ag, etc. to a high-melting-point metal (Ti, Zr, Hf, etc.) that is active against oxygen between the ceramic and copper foil interface.
  • the Cu pattern after bonding is formed by etching copper foil like DBC.
  • DPC technology is a method of manufacturing a ceramic circuit board using a thin film process, an etching process, and a plating process. After depositing a seed layer with Ti, TiW, or the like, photoresist (PR) is applied, patterning is performed, and then a Cu layer is formed through Cu plating. The thickness of the Cu layer is limited to about 150 ⁇ m.
  • Patent Document 1 Korean Patent No. 0477866
  • Patent Document 2 Korea Patent Publication No. 2014-0127228
  • Patent Document 3 Korean Patent No. 1393760
  • Patent Document 4 Korea Patent Publication No. 2014-0095083
  • An object of the present invention is to provide a method of manufacturing a ceramic circuit board capable of forming a three-dimensional pattern on a ceramic substrate to be able to cope with various types of semiconductor devices mounted on the substrate.
  • Another object of the present invention is to provide a method of manufacturing a ceramic circuit board capable of improving durability against thermal cycles.
  • Another object of the present invention is to provide a method of manufacturing a ceramic circuit board capable of improving electrical conductivity and thermal conductivity of a copper pattern.
  • Another object of the present invention is to provide a method of manufacturing a ceramic circuit board capable of improving the surface roughness of a pattern while minimizing a difference between a pattern width on a side in contact with a ceramic substrate and a pattern width on an upper portion of the pattern.
  • Another object of the present invention is to provide a method of manufacturing a ceramic circuit board that minimizes bending of the ceramic substrate in the process of forming a copper pattern.
  • the present invention provides a method for manufacturing a ceramic circuit board in which a copper pattern is formed by printing a copper paste layer on a ceramic substrate, the ceramic substrate having a first surface and a second surface parallel to the first surface and preparing; forming a plurality of copper layers on a first surface of the ceramic substrate, wherein the forming of the plurality of copper layers includes printing a bonding paste on the first surface of the ceramic substrate and drying the bonding paste layer forming a first copper layer by pressing and sintering the dried bonding paste layer; printing a lamination paste on the first copper layer and drying to form a lamination paste layer; There is provided a method of manufacturing a ceramic circuit board comprising the step of forming a second copper layer by pressing and sintering the laminated paste layer.
  • the forming of the plurality of copper layers does not include a glass frit on the second copper layer, and includes copper oxide (Cu 2 O) particles and fine copper particles having an average particle diameter of 1 to 5 ⁇ m. It provides a method of manufacturing a ceramic circuit board, characterized in that it further comprises the step of forming a third copper layer by drying and sintering after printing the surface layer paste having a shrinkage ratio of 10% to 15% containing 60% by weight.
  • the method further includes forming a plurality of anti-warpage layers on the second surface of the ceramic substrate, wherein in the forming of the plurality of anti-warpage layers, the thickness of the plurality of anti-warpage layers is determined by the volume of the copper layers. It provides a method of manufacturing a ceramic circuit board, characterized in that the ratio of the sum of the sum and the sum of the volumes of the anti-warpage layers is adjusted to be 0.9 to 1.1.
  • the forming of the plurality of anti-warpage layers includes printing a bonding paste on the second surface, drying and sintering to form a first anti-warpage layer, and applying a lamination paste on the first anti-warpage layer. and drying and sintering after printing to form a second anti-warpage layer, wherein the thickness of the first anti-warpage layer and the thickness of the second anti-warpage layer are the thicknesses of the first copper layer and the second copper layer. It provides a method of manufacturing a ceramic circuit board, characterized in that the ratio of the sum of the volumes and the sum of the volumes of the first anti-warping layer and the second anti-warping layer is adjusted to be 0.9 to 1.1.
  • the thickness of the first anti-warpage layer is adjusted so that the ratio of the volume of the first copper layer to the volume of the first anti-warpage layer is 0.9 to 1.1
  • the thickness of the second anti-warpage layer is the second copper It provides a method of manufacturing a ceramic circuit board, characterized in that the ratio of the volume of the layer to the volume of the second anti-warpage layer is adjusted to be 0.9 to 1.1.
  • the thickness of the anti-warping layer and the thickness of the third anti-warpage layer are the sum of the volumes of the first copper layer, the second copper layer and the third copper layer and the first anti-warpage layer, the second anti-warpage layer and It provides a method of manufacturing a ceramic circuit board, characterized in that the ratio of the sum of the volumes of the third anti-warpage layer is adjusted to be 0.9 to 1.1.
  • the thickness of the first anti-warpage layer is adjusted so that the volume ratio of the first copper layer and the first anti-warpage layer is 0.9 to 1.1
  • the thickness of the second anti-warpage layer is the second copper layer and the The volume ratio of the second anti-warpage layer is adjusted to 0.9 to 1.1
  • the thickness of the third anti-warpage layer is adjusted so that the volume ratio of the third copper layer and the third anti-warpage layer is 0.9 to 1.1
  • the step of printing a lamination paste on the third copper layer, drying and sintering to form a fourth copper layer, and printing the surface layer paste on the fourth copper layer, drying and sintering to form a fifth copper layer It provides a method of manufacturing a ceramic circuit board, characterized in that it further comprises the step of forming.
  • the bonding paste provides a method of manufacturing a ceramic circuit board, characterized in that the shrinkage rate is 3% or less, including glass frit, inorganic particles, copper oxide particles, and copper particles.
  • the lamination paste does not include a glass frit, and provides a method of manufacturing a ceramic circuit board, characterized in that the shrinkage ratio including inorganic particles and copper particles is 3% to 9%.
  • the inorganic particles Al 2 O 3 , CaO, ZrO 2 Provides a method of manufacturing a ceramic circuit board, characterized in that it comprises at least one powder selected from the powder.
  • the method of manufacturing a ceramic circuit board according to the present invention has an advantage in that a three-dimensional pattern can be formed on the ceramic substrate so as to correspond to various types of semiconductor devices mounted on the substrate.
  • the ceramic circuit board according to the present invention has an advantage in that durability against thermal cycles is improved.
  • the ceramic circuit board according to the present invention has improved electrical conductivity and thermal conductivity of the copper pattern.
  • the method of manufacturing a ceramic circuit board according to some embodiments of the present invention has the advantage of improving the surface roughness of the pattern while minimizing the difference between the pattern width on the side in contact with the ceramic substrate and the pattern width on the top of the pattern.
  • the method of manufacturing a ceramic circuit board according to some embodiments of the present invention has an advantage in that the bending of the ceramic substrate can be minimized in the process of forming the copper pattern layer.
  • FIG. 1 is a conceptual diagram of a ceramic circuit board according to an embodiment of the present invention.
  • FIG. 2 is a flowchart of a method of manufacturing a ceramic circuit board according to an embodiment of the present invention.
  • FIG. 3 is a flow chart of the steps of forming a first copper layer.
  • FIG. 4 is a conceptual diagram of a ceramic circuit board according to another embodiment of the present invention.
  • 5 to 8 are conceptual views of a ceramic circuit board according to still other embodiments of the present invention.
  • a ceramic circuit board 100 according to an embodiment of the present invention has a first surface (top surface in FIG. 1 ) and a second surface (bottom surface in FIG. 1 ) parallel to the first surface.
  • the ceramic substrate 10 includes a conductive pattern 20 including a plurality of copper layers formed on the first surface of the ceramic substrate 10 and a plurality of anti-warpage layers 30 formed on the second surface of the ceramic substrate.
  • the ceramic substrate 10 is, for example, Al 2 O 3 , AlN, ZTA, Si 3 N 4 , etc.
  • the substrate may be made of a ceramic material.
  • the conductive pattern 20 includes a first copper layer 21 , a second copper layer 22 , and a third copper layer 23 sequentially formed on the first surface.
  • the first copper layer 21 includes a glass component
  • the second copper layer 22 and the third copper layer 23 do not include a glass component.
  • the anti-warpage layers 30 include a first anti-warpage layer 31 , a second anti-warpage layer 32 and a third anti-warpage layer 33 sequentially formed on the second surface.
  • the warpage prevention layers 30 serve to prevent the ceramic substrate 10 from being bent during a sintering process to form the conductive pattern 20 .
  • the first copper layer 21 and the first anti-warpage layer 31 are made of the same material
  • the second copper layer 22 and the second anti-warpage layer 32 are made of the same material
  • the third copper layer (23) may be made of the same material as the third anti-warpage layer (33).
  • the thickness of the plurality of anti-warpage layers 30 is adjusted such that a ratio of the sum of the volumes of the copper layers 21 , 22 , and 23 to the sum of the volumes of the anti-warpage layers 30 is 0.9 to 1.1.
  • the volume ratio of the layers corresponding to each other may be adjusted to be 0.9 to 1.1. That is, in the embodiment shown in FIG. 1 , the volume ratio of the first copper layer 21 and the first anti-warpage layer 31 is 0.9 to 1.1, and the second copper layer 22 and the second anti-warpage layer 32 .
  • the volume ratio of the third copper layer 23 and the third anti-warpage layer 33 may also be 0.9 to 1.1.
  • FIG. 2 is a flowchart of a method of manufacturing a ceramic circuit board according to an embodiment of the present invention.
  • a method of manufacturing the ceramic circuit board 100 shown in FIG. 1 will be described with reference to FIG. 2 .
  • the method of manufacturing a ceramic circuit board 100 includes a step ( S1 ) of preparing the ceramic substrate 10 , and a first surface of the ceramic substrate 10 .
  • step S1 of preparing the ceramic substrate 10 will be described.
  • the ceramic substrate 10 is made of Al 2 O 3 , AlN, Zirconia Toughened Alumina (ZTA), Si 3 N 4 , or the like.
  • the substrate may be made of a ceramic material.
  • the ceramic substrate 10 has a first surface and a second surface parallel to the first surface.
  • step S2 of forming the first copper layer 21 will be described.
  • the first copper layer 21 is formed on the first surface of the ceramic substrate 10 .
  • the first copper layer 21 may be formed directly on the first surface of the ceramic substrate 10 .
  • the step of forming the first copper layer 21 includes printing the bonding paste ( S21 ), drying the bonding paste layer ( S22 ), and pressing the dried bonding paste layer. (S23) and sintering the bonding paste layer (S24).
  • the bonding paste can be printed by a screen printing method.
  • the bonding paste includes glass frit, inorganic particles, copper oxide particles, copper particles, a solvent and a binder.
  • the glass frit is a sintering aid that helps sinter the copper (Cu) particles, and serves to bond the first copper layer 21 and the ceramic substrate 10 .
  • the inorganic particles may include at least one powder selected from Al 2 O 3 , CaO, and ZrO 2 powders. Inorganic particles are used to lower the shrinkage of the bonding paste.
  • the shrinkage rate of the paste is measured by printing the paste in the form of a disk, drying and sintering, and comparing the diameter of the disk after drying and sintering.
  • the shrinkage rate of the bonding paste is preferably 3% or less.
  • Copper oxide (CuO, Cu 2 O) particles are added to supplement bonding properties with the ceramic substrate 10 .
  • copper oxide reacts with alumina to form CuAlO 2 , CuAl 2 O 4 , thereby improving bonding properties.
  • the bonding paste layer is dried to remove the solvent.
  • the dried bonding paste layer is compressed to reduce the height difference between the bonding paste layers.
  • the boundary of the bonding paste layer has a higher viscosity than the center of the paste because the flow rate of the paste decreases. Therefore, the boundary of the dried bonding paste layer after printing is thicker than the central portion.
  • the heat treatment profile for sintering the bonding paste layer includes a bake out step of supplying a small amount of water vapor or oxygen to a nitrogen atmosphere in order to remove the binder, a step of liquid phase sintering of copper (Cu) particles, and a step of cooling.
  • the liquid phase sintering of copper (Cu) particles is preferably performed in a nitrogen atmosphere in order to prevent oxidation of copper (Cu). In this case, a small amount of oxygen may be supplied so that the glass frit is easily wetted on the copper (Cu) particles.
  • the bake-out step may be performed at about 300 to 500°C, and the liquid-phase sintering may be performed at about 700 to 900°C.
  • the total sintering time is about 50 to 90 minutes, and may be performed in a continuous heat treatment furnace such as a muffle type heat treatment furnace or a batch type heat treatment furnace such as a box oven.
  • the first anti-warpage layer 31 is formed on the second surface of the ceramic substrate 10 .
  • the first anti-warpage layer 31 may be formed directly on the second surface of the ceramic substrate 10 .
  • the first anti-warpage layer 31, like the first copper layer 21, is formed through the steps of printing the bonding paste, drying the bonding paste layer, pressing the dried bonding paste layer, and sintering the bonding paste layer. formed through steps.
  • the first anti-warpage layer 31 may be formed to cover the entire second surface of the ceramic substrate 10 .
  • the first anti-warpage layer 31 is formed together with the first copper layer 21 . After each bonding paste is printed on the first and second surfaces of the ceramic substrate 10, the bonding paste layers on both sides are dried at once, pressed and sintered at once to form the first anti-warpage layer 31 and the cuprous copper Layer 21 is formed at a time.
  • a second copper layer 22 is formed over the first copper layer 21 .
  • the second copper layer 22 is formed by printing the lamination paste and then drying, pressing and sintering.
  • the second copper layer 22 serves to increase the thickness of the conductive pattern 20 .
  • the lamination paste contains inorganic particles, copper particles, a solvent and a binder.
  • the inorganic particles may include at least one selected from among Al 2 O 3 , CaO, and ZrO 2 particles. Inorganic particles are used to lower the shrinkage of the bonding paste.
  • Lamination paste does not contain glass frit unlike bonding paste. Lamination pastes have a higher shrinkage rate than bonding pastes. It is preferable that the shrinkage ratio of the lamination paste is 3% to 9%.
  • Printing may be performed by a screen printing method. After printing, the lamination paste layer is dried to remove the solvent. Then, the dried lamination paste layer is compressed to reduce the height difference between the bonding paste layers. Next, by heat-treating the ceramic substrate 10 on which the first copper layer 21 and the pressed lamination paste layer are formed, the lamination paste layer is sintered to form the second copper layer 22 . Like the heat treatment of the bonding paste layer, the heat treatment may be performed in a nitrogen atmosphere containing a small amount of oxygen.
  • the step of forming the second copper layer 22 may be performed multiple times, or only the printing, drying, and pressing processes may be performed multiple times.
  • step (S5) of forming the second warpage prevention layer 32 will be described.
  • the second anti-warpage layer 32 is formed over the first anti-warpage layer 31 .
  • the second anti-warpage layer 32 like the second copper layer 22, is formed through the steps of printing the lamination paste, drying the lamination paste layer, pressing the dried lamination paste layer, and sintering the lamination paste layer. formed through steps.
  • the second anti-warpage layer 32 is formed together with the second copper layer 22 .
  • a third copper layer 23 is formed over the second copper layer 22 .
  • the third copper layer 23 is formed by printing the surface layer paste and then drying, pressing and sintering.
  • the third copper layer 23 serves to provide a dense surface for easy plating.
  • the surface layer paste does not contain a glass frit, but contains copper oxide (Cu2O) particles, copper particles, a solvent, and a binder.
  • the copper particles include fine copper particles having an average particle diameter of 1 to 5 ⁇ m.
  • the fine copper particles are contained in an amount of 5 to 60% by weight in the surface layer paste.
  • the fine copper particles serve to increase the density of the third copper layer 23 .
  • Copper oxide (Cu 2 O) particles may form a process liquid phase during the sintering process.
  • the surface layer paste preferably has a shrinkage ratio of 10% to 15%.
  • Printing may be performed by a screen printing method. After printing, the surface paste layer is dried to remove the solvent. And by compressing the dried surface paste layer, the height difference between the surface paste layer is reduced. Next, the third copper layer 23 is formed by heat-treating the ceramic substrate 10 on which the first copper layer 21 , the second copper layer 22 and the pressed surface paste layer are formed to sinter the surface paste layer. do. Like the heat treatment of the bonding paste layer, the heat treatment may be performed in a nitrogen atmosphere containing a small amount of oxygen.
  • step (S7) of forming the third anti-warpage layer 33 will be described.
  • the third anti-warpage layer 33 is formed over the second anti-warpage layer 32 .
  • the third anti-warpage layer 33 is formed by printing the surface paste, drying the surface paste layer, pressing the dried surface paste layer, and sintering the surface paste layer. formed through steps.
  • the third anti-warpage layer 33 is formed together with the third copper layer 23 .
  • the thickness of the first anti-warpage layer, the thickness of the second anti-warpage layer, and the thickness of the third anti-warpage layer are the first copper layer, the second The ratio of the sum of the volumes of the copper layer and the third copper layer to the sum of the volumes of the first, second, and third anti-warpage layers is adjusted to be 0.9 to 1.1.
  • the volume ratio of the layers corresponding to each other may be adjusted to be 0.9 to 1.1. That is, the thickness of the first anti-warpage layer 31 is adjusted so that the volume ratio of the first copper layer 21 and the first anti-warpage layer 31 is 0.9 to 1.1, and the thickness of the second anti-warpage layer 32 is adjusted so that the volume ratio of the second copper layer 22 and the second anti-warpage layer 32 is 0.9 to 1.1, and the thickness of the third anti-warpage layer 33 is the third copper layer 23 and the third warpage
  • the volume ratio of the barrier layer 33 may be adjusted to be 0.9 to 1.1.
  • FIG. 4 is a conceptual diagram of a ceramic circuit board according to another embodiment of the present invention.
  • the ceramic circuit board 200 according to the present embodiment is different from the embodiment shown in FIG. 1 in that the thickness of some conductive patterns 120 is thicker than the thickness of other patterns 20 .
  • the present embodiment has an advantage in that a separate spacer is not required to mount semiconductor devices having different heights.
  • a fourth copper layer 122 and a fifth copper layer 123 are formed on the third copper layer 23 .
  • the fourth copper layer 122 may be formed by printing a lamination paste on the third copper layer 23 and then drying, pressing, and sintering, and the fifth copper layer 123 is formed on the fourth copper layer 122 . After printing the surface layer paste, it can be formed by drying, pressing and sintering.
  • the fourth copper layer 122 may be made of the same material as the second copper layer 22 .
  • the fifth copper layer 123 may be made of the same material as the third copper layer 23 .
  • the fourth anti-warpage layer 132 and the fifth anti-warpage layer 133 are formed on the third anti-warpage layer 33 .
  • the fourth anti-warping layer 132 may be made of the same material as the second copper layer 22
  • the fifth anti-warping layer 133 may be made of the same material as the third copper layer 23 .
  • the thickness of the plurality of anti-warpage layers 130 is adjusted such that a ratio of the sum of the volumes of the copper layers 20 and 120 to the sum of the volumes of the anti-warpage layers 130 is 0.9 to 1.1.
  • the fourth anti-warpage layer 132 is formed together with the fourth copper layer 122 .
  • the fifth anti-warpage layer 133 is formed together with the fifth copper layer 123 .
  • FIG. 5 is a conceptual diagram of a ceramic circuit board according to another embodiment of the present invention.
  • the embodiment shown in FIG. 5 is different from the embodiment shown in FIG. 1 in that there is no third copper layer.
  • the third copper layer may be omitted.
  • the ceramic circuit board 300 of the present embodiment may be manufactured by omitting the process of printing the surface layer paste.
  • FIG. 6 is a conceptual diagram of a ceramic circuit board according to another embodiment of the present invention.
  • the embodiment shown in FIG. 6 is different from the embodiment shown in FIG. 4 in that the fourth anti-warpage layer 132 and the fifth anti-warpage layer 133 are absent.
  • the thickness of the second anti-warping layer 232 and the third anti-warping layer 233 is the second anti-warping layer 32 and the third anti-warpage of the embodiment shown in FIG. 4 . It is also different from the embodiment shown in FIG. 4 in that it is slightly thicker than the thickness of the layer 33 .
  • the second anti-warpage layer 232 and the third anti-warpage layer ( By forming the thickness of 233 to be thicker by the thickness of the fourth anti-warpage layer 132 and the fifth anti-warpage layer 133 , the sum of the volumes of the copper layers 20 and 120 and the volume of the anti-warpage layers 230 . It is adjusted so that the ratio of the sum of is 0.9 to 1.1.
  • FIG. 7 and 8 are conceptual views of a ceramic circuit board according to still other embodiments of the present invention.
  • the embodiment shown in FIG. 7 is shown in FIG. 4 in that the fourth anti-warpage layer 332 and the fifth anti-warpage layer 333 are not formed on the entire surface of the ceramic substrate 10, but form a pattern. There is a difference from the embodiment.
  • the embodiment illustrated in FIG. 8 is different from the embodiment illustrated in FIG. 7 in that a sixth copper layer 222 and a seventh copper layer 223 are formed on a part of the fifth copper layer 123 .
  • a fourth anti-warpage layer 432 and a fifth anti-warpage layer 433 are provided in the embodiment shown in FIG. There is also a difference in that it is slightly thicker than that.
  • compression and sintering are not necessarily performed step by step. After several layers are stacked, pressing can be done at once, and sintering can be done at once. For example, after printing and drying the bonding paste, pressing after printing and drying the lamination paste thereon, printing and drying the surface layer face thereon, pressing again, and sintering may be performed at once. At which stage compression is performed and sintering is performed, it can be appropriately selected according to need.

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  • Microelectronics & Electronic Packaging (AREA)
  • Manufacturing & Machinery (AREA)
  • Chemical & Material Sciences (AREA)
  • Ceramic Engineering (AREA)
  • Inorganic Chemistry (AREA)
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Abstract

The present invention relates to a ceramic circuit board and, more specifically, to a ceramic circuit board used as a board for a power semiconductor. The present invention relates to a method for manufacturing a ceramic circuit board in which a copper pattern is formed by printing a copper paste layer on a ceramic board, and provides the method for manufacturing a ceramic circuit board comprising the steps of: preparing a ceramic board having a first surface and a second surface parallel to the first surface; and forming a plurality of copper layers on the first surface of the ceramic board, wherein the step of forming a plurality of copper layers comprises the steps of: printing a bonding paste on the first surface of the ceramic board and then drying the printed bonding paste to form a bonding paste layer, and compressing the dried bonding paste layer and then sintering the compressed bonding paste layer to form a first copper layer; printing a laminating paste on the first copper layer and then drying the printed laminating paste to form a laminating paste layer, and compressing the dried laminating paste layer and then sintering the compressed laminating paste layer to form a second copper layer. The method for manufacturing a ceramic circuit board, according to the present invention, has an advantage in that a three-dimensional pattern can be formed on the ceramic board so as to enable correspondence to various types of semiconductor elements mounted on the board.

Description

세라믹 회로 기판의 제조방법Method for manufacturing a ceramic circuit board
본 발명은 세라믹 회로 기판의 제조방법에 관한 것으로서, 더욱 상세하게는 전력 반도체의 기판으로 사용되는 세라믹 회로 기판의 제조방법에 관한 것이다.The present invention relates to a method of manufacturing a ceramic circuit board, and more particularly, to a method of manufacturing a ceramic circuit board used as a substrate for a power semiconductor.
모바일, 가전 및 자동차 등에 폭넓게 활용되고 있는 전력 반도체(Power Semiconductor)는 전력을 변환·처리·제어하는 역할을 한다.Power semiconductors, which are widely used in mobiles, home appliances, and automobiles, play a role in converting, processing, and controlling power.
전력 공급을 위한 파워 소자 등 대전류, 고전압이 요구되는 전력 반도체 소자는 발열량이 매우 크기 때문에, 이것을 탑재하는 기판으로는 Al2O3, AlN, ZTA(Zirconia Toughened Alumina), Si3N4 등의 세라믹 재질로 이루어진 기판을 사용한다. Al2O3, AlN, ZTA, Si3N4 등의 세라믹은 높은 절연성과 기계적 강도 및 비교적 높은 방열 성능을 갖추고 있기에 고전력 전력 반도체의 기판으로 적합하다. 또한, 세라믹 회로 기판은 세라믹 기판 위에 형성된 전도성 패턴을 갖추어야 한다. 전도성 패턴으로는 Al이나 Cu 패턴이 주로 사용된다.Since power semiconductor devices that require large currents and high voltages, such as power devices for power supply, generate a very large amount of heat, substrates on which they are mounted include Al 2 O 3 , AlN, Zirconia Toughened Alumina (ZTA), Si 3 N 4 , etc. A substrate made of a ceramic material is used. Ceramics such as Al 2 O 3 , AlN, ZTA, and Si 3 N 4 have high insulation, mechanical strength, and relatively high heat dissipation performance, so they are suitable as substrates for high-power power semiconductors. In addition, the ceramic circuit board should have a conductive pattern formed on the ceramic substrate. As the conductive pattern, an Al or Cu pattern is mainly used.
세라믹 회로 기판을 제조하는 종래의 기술은 DBC(Direct Bonded Copper), AMB(Active Metal Brazing Copper), DPC(Direct Plating Copper)가 있으며, 가장 보편적인 방법은 DBC 기술이다.Conventional techniques for manufacturing a ceramic circuit board include DBC (Direct Bonded Copper), AMB (Active Metal Brazing Copper), and DPC (Direct Plating Copper), and the most common method is DBC technology.
DBC 기술은 세라믹의 한 면 혹은 양면에 동박(Copper Foil)을 고온 산화공정으로 접합한 후 동박을 패터닝하여 세라믹 회로 기판을 제조하는 방법이다. 기판과 동박을 접착하기 위하여 구리-산소(copper-oxygen) 공정 액상(eutectic)을 이용한다. 접합은 구리의 융점인 1083℃ 이하의 온도에서, 약 30ppm의 산소를 포함하는 질소분위기에서 수행된다. DBC 방법은 접합된 동박을 일정한 패턴으로 형성하기 위하여 식각공정을 이용한다. 그리고 식각 후 Cu 패턴의 표면에 Ni, Ag와 Au를 도금한다. DBC 기술은 기계적 강도와 접착력이 양호하다는 장점이 있다. 그러나 동박의 최소 두께에 한계가 있으며, 에칭을 통해서 형성할 수 있는 패턴이 제한되며, 산화구리가 생성되지 않은 접합면에서는 기공이 존재하여 열 사이클에 대한 안정성이 떨어진다는 단점이 있다.DBC technology is a method of manufacturing a ceramic circuit board by bonding copper foil to one or both sides of a ceramic through a high-temperature oxidation process and then patterning the copper foil. A copper-oxygen process eutectic is used to bond the substrate and the copper foil. Bonding is performed in a nitrogen atmosphere containing about 30 ppm oxygen at a temperature of 1083° C. or less, which is the melting point of copper. The DBC method uses an etching process to form a bonded copper foil in a uniform pattern. After etching, Ni, Ag and Au are plated on the surface of the Cu pattern. DBC technology has the advantage of good mechanical strength and adhesion. However, there is a limit to the minimum thickness of the copper foil, a pattern that can be formed through etching is limited, and pores exist on the junction surface where copper oxide is not generated, thereby reducing stability to thermal cycles.
AMB 기술은 산소에 대해 활성인 고융점 금속(Ti, Zr, Hf 등)에 Cu, Ag 등을 첨가해 융점을 낮춘 활성금속합금을 세라믹과 동박 계면 사이에 끼워서 세라믹과 동박을 접합한다. 접합 후의 Cu 패턴은 DBC와 마찬가지로 동박을 에칭하여 형성한다.AMB technology joins ceramic and copper foil by sandwiching an active metal alloy whose melting point is lowered by adding Cu, Ag, etc. to a high-melting-point metal (Ti, Zr, Hf, etc.) that is active against oxygen between the ceramic and copper foil interface. The Cu pattern after bonding is formed by etching copper foil like DBC.
DPC 기술은 박막 필름공정, 식각공정 및 도금공정을 활용하여 세라믹 회로 기판을 제조하는 방법이다. 시드(Seed) 층을 Ti, TiW 등으로 증착한 후에 포토레지스트(PR, Photo Resist)를 도포하고, 패터닝을 실시한 후에 Cu 도금을 통해서, Cu 층을 형성한다. Cu 층의 두께는 약 150㎛까지로 제한된다.DPC technology is a method of manufacturing a ceramic circuit board using a thin film process, an etching process, and a plating process. After depositing a seed layer with Ti, TiW, or the like, photoresist (PR) is applied, patterning is performed, and then a Cu layer is formed through Cu plating. The thickness of the Cu layer is limited to about 150 μm.
이러한 종래의 세라믹 회로 기판을 제작하는 기술들은, 패턴 형성을 위하여 식각공정을 이용하기 때문에 패턴 형태에 제한이 있다는 한계가 있었다. 특히, 다양한 형태의 반도체 소자에 대응하기 위해서 패턴 간에 두께의 차이를 두거나, 패턴 위에 2차 패턴 및 3차 패턴을 형성하기가 어렵다는 문제가 있었다.These conventional techniques for manufacturing a ceramic circuit board have a limitation in that there is a limitation in the shape of the pattern because an etching process is used to form the pattern. In particular, in order to respond to various types of semiconductor devices, there is a problem in that it is difficult to provide a difference in thickness between patterns or to form a secondary pattern and a tertiary pattern on the patterns.
종래의 세라믹 회로 기판에서는 패턴 간의 두께의 차이를 형성하기 어렵기 때문에, 패턴 중 일부에 스페이서를 배치하는 방법으로 단차를 형성하였다. 그러나 전도성 스페이서의 열전도도가 낮으며, 스페이서를 패턴 위에 실장하는 부가적인 공정이 필요하다는 문제점이 있었다.Since it is difficult to form a difference in thickness between patterns in a conventional ceramic circuit board, a step is formed by arranging spacers in some of the patterns. However, there is a problem in that the thermal conductivity of the conductive spacer is low, and an additional process of mounting the spacer on the pattern is required.
[선행기술문헌][Prior art literature]
(특허문헌 1) 한국등록특허 제0477866호(Patent Document 1) Korean Patent No. 0477866
(특허문헌 2) 한국공개특허 제2014-0127228호(Patent Document 2) Korea Patent Publication No. 2014-0127228
(특허문헌 3) 한국등록특허 제1393760호(Patent Document 3) Korean Patent No. 1393760
(특허문헌 4) 한국공개특허 제2014-0095083호(Patent Document 4) Korea Patent Publication No. 2014-0095083
본 발명은 상술한 문제점을 개선하기 위한 것으로서, 기판 위에 실장되는 다양한 형태의 반도체 소자에 대응 가능하도록 세라믹 기판 위에 입체적인 패턴을 형성할 수 있는 세라믹 회로 기판의 제조방법을 제공하는 것을 목적으로 한다.An object of the present invention is to provide a method of manufacturing a ceramic circuit board capable of forming a three-dimensional pattern on a ceramic substrate to be able to cope with various types of semiconductor devices mounted on the substrate.
또한, 열 사이클에 대한 내구성을 향상할 수 있는 세라믹 회로 기판의 제조방법을 제공하는 것을 목적으로 한다.Another object of the present invention is to provide a method of manufacturing a ceramic circuit board capable of improving durability against thermal cycles.
또한, 구리패턴의 전기전도도와 열전도도를 향상할 수 있는 세라믹 회로 기판의 제조방법을 제공하는 것을 목적으로 한다. Another object of the present invention is to provide a method of manufacturing a ceramic circuit board capable of improving electrical conductivity and thermal conductivity of a copper pattern.
또한, 세라믹 기판과 접하는 쪽의 패턴 폭과 패턴 상부의 패턴 폭의 차이를 최소화하면서, 패턴의 표면 조도를 향상할 수 있는 세라믹 회로 기판의 제조방법을 제공하는 것을 목적으로 한다.Another object of the present invention is to provide a method of manufacturing a ceramic circuit board capable of improving the surface roughness of a pattern while minimizing a difference between a pattern width on a side in contact with a ceramic substrate and a pattern width on an upper portion of the pattern.
또한, 구리 패턴을 형성하는 과정에서 세라믹 기판이 휘는 것을 최소화하는 세라믹 회로 기판의 제조방법을 제공하는 것을 목적으로 한다.Another object of the present invention is to provide a method of manufacturing a ceramic circuit board that minimizes bending of the ceramic substrate in the process of forming a copper pattern.
상술한 목적을 달성하기 위해서, 본 발명은 세라믹 기판에 구리 페이스트 층을 인쇄하여 구리 패턴을 형성하는 세라믹 회로 기판의 제조방법으로서, 제1면과 제1면에 나란한 제2면을 구비하는 세라믹 기판을 준비하는 단계와; 상기 세라믹 기판의 제1면 위에 복수의 구리 층들을 형성하는 단계를 포함하며, 상기 복수의 구리 층들을 형성하는 단계는, 상기 세라믹 기판의 제1면 위에 접합 페이스트를 인쇄한 후 건조하여 접합 페이스트 층을 형성하고, 건조된 상기 접합 페이스트 층을 압착한 후 소결하여 제1 구리 층을 형성하는 단계와, 상기 제1 구리 층 위에 적층 페이스트를 인쇄한 후 건조하여 적층 페이스트 층을 형성하고, 건조된 상기 적층 페이스트 층을 압착한 후 소결하여 제2 구리 층을 형성하는 단계를 포함하는 것을 특징으로 하는 세라믹 회로 기판의 제조방법을 제공한다.In order to achieve the above object, the present invention provides a method for manufacturing a ceramic circuit board in which a copper pattern is formed by printing a copper paste layer on a ceramic substrate, the ceramic substrate having a first surface and a second surface parallel to the first surface and preparing; forming a plurality of copper layers on a first surface of the ceramic substrate, wherein the forming of the plurality of copper layers includes printing a bonding paste on the first surface of the ceramic substrate and drying the bonding paste layer forming a first copper layer by pressing and sintering the dried bonding paste layer; printing a lamination paste on the first copper layer and drying to form a lamination paste layer; There is provided a method of manufacturing a ceramic circuit board comprising the step of forming a second copper layer by pressing and sintering the laminated paste layer.
또한, 상기 복수의 구리 층들을 형성하는 단계는, 상기 제2 구리 층 위에 글라스 프릿을 포함하지 않으며, 산화구리(Cu2O) 입자들과 평균 입경이 1 내지 5㎛인 미세 구리 입자들을 5 내지 60중량% 포함하는 수축률이 10% 내지 15%인 표층 페이스트를 인쇄한 후 건조 및 소결하여 제3 구리 층을 형성하는 단계를 더 포함하는 것을 특징으로 하는 세라믹 회로 기판의 제조방법을 제공한다.In addition, the forming of the plurality of copper layers does not include a glass frit on the second copper layer, and includes copper oxide (Cu 2 O) particles and fine copper particles having an average particle diameter of 1 to 5 μm. It provides a method of manufacturing a ceramic circuit board, characterized in that it further comprises the step of forming a third copper layer by drying and sintering after printing the surface layer paste having a shrinkage ratio of 10% to 15% containing 60% by weight.
또한, 상기 세라믹 기판의 제2면 위에 복수의 휨 방지 층들을 형성하는 단계를 더 포함하며, 상기 복수의 휨 방지 층들을 형성하는 단계에서, 상기 복수의 휨 방지 층들의 두께는 상기 구리 층들의 부피의 합과 상기 휨 방지 층들의 부피의 합의 비가 0.9 내지 1.1이 되도록 조절되는 것을 특징으로 하는 세라믹 회로 기판의 제조방법을 제공한다.The method further includes forming a plurality of anti-warpage layers on the second surface of the ceramic substrate, wherein in the forming of the plurality of anti-warpage layers, the thickness of the plurality of anti-warpage layers is determined by the volume of the copper layers. It provides a method of manufacturing a ceramic circuit board, characterized in that the ratio of the sum of the sum and the sum of the volumes of the anti-warpage layers is adjusted to be 0.9 to 1.1.
또한, 상기 복수의 휨 방지 층들을 형성하는 단계는, 상기 제2면 위에 접합 페이스트를 인쇄한 후 건조 및 소결하여 제1 휨 방지 층을 형성하는 단계와, 상기 제1 휨 방지 층 위에 적층 페이스트를 인쇄한 후 건조 및 소결하여 제2 휨 방지 층을 형성하는 단계를 포함하며, 상기 제1 휨 방지 층의 두께와 상기 제2 휨 방지 층의 두께는 상기 제1 구리 층 및 상기 제2 구리 층의 부피의 합과 상기 제1 휨 방지 층 및 상기 제2 휨 방지 층의 부피의 합의 비가 0.9 내지 1.1이 되도록 조절되는 것을 특징으로 하는 세라믹 회로 기판의 제조방법을 제공한다.In addition, the forming of the plurality of anti-warpage layers includes printing a bonding paste on the second surface, drying and sintering to form a first anti-warpage layer, and applying a lamination paste on the first anti-warpage layer. and drying and sintering after printing to form a second anti-warpage layer, wherein the thickness of the first anti-warpage layer and the thickness of the second anti-warpage layer are the thicknesses of the first copper layer and the second copper layer. It provides a method of manufacturing a ceramic circuit board, characterized in that the ratio of the sum of the volumes and the sum of the volumes of the first anti-warping layer and the second anti-warping layer is adjusted to be 0.9 to 1.1.
또한, 상기 제1 휨 방지 층의 두께는 상기 제1 구리 층의 부피와 상기 제1 휨 방지 층의 부피의 비가 0.9 내지 1.1이 되도록 조절되며, 상기 제2 휨 방지 층의 두께는 상기 제2 구리 층의 부피와 상기 제2 휨 방지 층의 부피의 비가 0.9 내지 1.1이 되도록 조절되는 것을 특징으로 하는 세라믹 회로 기판의 제조방법을 제공한다.In addition, the thickness of the first anti-warpage layer is adjusted so that the ratio of the volume of the first copper layer to the volume of the first anti-warpage layer is 0.9 to 1.1, and the thickness of the second anti-warpage layer is the second copper It provides a method of manufacturing a ceramic circuit board, characterized in that the ratio of the volume of the layer to the volume of the second anti-warpage layer is adjusted to be 0.9 to 1.1.
또한, 상기 제2면 위에 접합 페이스트를 인쇄한 후 건조 및 소결하여 제1 휨 방지 층을 형성하는 단계와, 상기 제1 휨 방지 층 위에 적층 페이스트를 인쇄한 후 건조 및 소결하여 제2 휨 방지 층을 형성하는 단계와, 상기 제2 휨 방지 층 위에 표층 페이스트를 인쇄한 후 건조 및 소결하여 제3 휨 방지 층을 형성하는 단계를 더 포함하며, 상기 제1 휨 방지 층의 두께, 상기 제2 휨 방지 층의 두께 및 상기 제3 휨 방지 층의 두께는 상기 제1 구리 층, 상기 제2 구리 층 및 상기 제3 구리 층의 부피의 합과 상기 제1 휨 방지 층, 상기 제2 휨 방지 층 및 상기 제3 휨 방지 층의 부피의 합의 비가 0.9 내지 1.1이 되도록 조절되는 것을 특징으로 하는 세라믹 회로 기판의 제조방법을 제공한다.In addition, the steps of printing the bonding paste on the second surface, drying and sintering to form a first anti-warpage layer, and printing the lamination paste on the first anti-warpage layer, drying and sintering the second anti-warpage layer and forming a third anti-warpage layer by printing a surface paste on the second anti-warpage layer, followed by drying and sintering, wherein the thickness of the first anti-warpage layer, the second warpage The thickness of the anti-warping layer and the thickness of the third anti-warpage layer are the sum of the volumes of the first copper layer, the second copper layer and the third copper layer and the first anti-warpage layer, the second anti-warpage layer and It provides a method of manufacturing a ceramic circuit board, characterized in that the ratio of the sum of the volumes of the third anti-warpage layer is adjusted to be 0.9 to 1.1.
또한, 상기 제1 휨 방지 층의 두께는 상기 제1 구리 층과 상기 제1 휨 방지 층의 부피비가 0.9 내지 1.1이 되도록 조절되며, 상기 제2 휨 방지 층의 두께는 상기 제2 구리 층과 상기 제2 휨 방지 층의 부피비가 0.9 내지 1.1이 되도록 조절되며, 상기 제3 휨 방지 층의 두께는 상기 제3 구리 층과 상기 제3 휨 방지 층의 부피비가 0.9 내지 1.1이 되도록 조절되는 것을 특징으로 하는 세라믹 회로 기판의 제조방법을 제공한다.In addition, the thickness of the first anti-warpage layer is adjusted so that the volume ratio of the first copper layer and the first anti-warpage layer is 0.9 to 1.1, and the thickness of the second anti-warpage layer is the second copper layer and the The volume ratio of the second anti-warpage layer is adjusted to 0.9 to 1.1, and the thickness of the third anti-warpage layer is adjusted so that the volume ratio of the third copper layer and the third anti-warpage layer is 0.9 to 1.1 To provide a method for manufacturing a ceramic circuit board.
또한, 상기 제3 구리 층의 위에 적층 페이스트를 인쇄한 후 건조 및 소결하여 제4 구리 층을 형성하는 단계와, 상기 제4 구리 층 위에 표층 페이스트를 인쇄한 후 건조 및 소결하여 제5 구리 층을 형성하는 단계를 더 포함하는 것을 특징으로 하는 세라믹 회로 기판의 제조방법을 제공한다.In addition, the step of printing a lamination paste on the third copper layer, drying and sintering to form a fourth copper layer, and printing the surface layer paste on the fourth copper layer, drying and sintering to form a fifth copper layer It provides a method of manufacturing a ceramic circuit board, characterized in that it further comprises the step of forming.
또한, 상기 접합 페이스트는 글라스 프릿(Glass Frit), 무기물 입자들, 산화구리 입자들 및 구리 입자들을 포함하는 수축률이 3% 이하인 것을 특징으로 하는 세라믹 회로 기판의 제조방법을 제공한다.In addition, the bonding paste provides a method of manufacturing a ceramic circuit board, characterized in that the shrinkage rate is 3% or less, including glass frit, inorganic particles, copper oxide particles, and copper particles.
또한, 상기 적층 페이스트는 글라스 프릿을 포함하지 않으며, 무기물 입자들과 구리 입자들을 포함하는 수축률이 3% 내지 9%인 것을 특징으로 하는 세라믹 회로 기판의 제조방법을 제공한다.In addition, the lamination paste does not include a glass frit, and provides a method of manufacturing a ceramic circuit board, characterized in that the shrinkage ratio including inorganic particles and copper particles is 3% to 9%.
또한, 상기 무기물 입자들은 Al2O3, CaO, ZrO2 분말들 중 선택된 적어도 하나의 분말을 포함하는 것을 특징으로 하는 세라믹 회로 기판의 제조방법을 제공한다.In addition, the inorganic particles Al 2 O 3 , CaO, ZrO 2 Provides a method of manufacturing a ceramic circuit board, characterized in that it comprises at least one powder selected from the powder.
본 발명에 따른 세라믹 회로 기판의 제조방법은 기판 위에 실장되는 다양한 형태의 반도체 소자에 대응 가능하도록 세라믹 기판 위에 입체적인 패턴을 형성할 수 있다는 장점이 있다.The method of manufacturing a ceramic circuit board according to the present invention has an advantage in that a three-dimensional pattern can be formed on the ceramic substrate so as to correspond to various types of semiconductor devices mounted on the substrate.
또한, 본 발명에 따른 세라믹 회로 기판은 열 사이클에 대한 내구성이 향상된다는 장점이 있다. 또한, 본 발명에 따른 세라믹 회로 기판은 구리패턴의 전기전도도와 열전도도가 향상된다.In addition, the ceramic circuit board according to the present invention has an advantage in that durability against thermal cycles is improved. In addition, the ceramic circuit board according to the present invention has improved electrical conductivity and thermal conductivity of the copper pattern.
또한, 본 발명의 일부 실시예에 따른 세라믹 회로 기판의 제조방법은 세라믹 기판과 접하는 쪽의 패턴 폭과 패턴 상부의 패턴 폭의 차이를 최소화하면서, 패턴의 표면 조도를 향상할 수 있다는 장점이 있다.In addition, the method of manufacturing a ceramic circuit board according to some embodiments of the present invention has the advantage of improving the surface roughness of the pattern while minimizing the difference between the pattern width on the side in contact with the ceramic substrate and the pattern width on the top of the pattern.
또한, 본 발명의 일부 실시예에 따른 세라믹 회로 기판의 제조방법은 구리 패턴 층을 형성하는 과정에서 세라믹 기판이 휘는 것을 최소화할 수 있다는 장점도 있다.In addition, the method of manufacturing a ceramic circuit board according to some embodiments of the present invention has an advantage in that the bending of the ceramic substrate can be minimized in the process of forming the copper pattern layer.
도 1은 본 발명의 일실시예에 따른 세라믹 회로 기판의 개념도이다.1 is a conceptual diagram of a ceramic circuit board according to an embodiment of the present invention.
도 2는 본 발명의 일실시예에 따른 세라믹 회로 기판의 제조방법의 흐름도이다.2 is a flowchart of a method of manufacturing a ceramic circuit board according to an embodiment of the present invention.
도 3은 제1 구리 층을 형성하는 단계의 흐름도이다.3 is a flow chart of the steps of forming a first copper layer.
도 4는 본 발명의 다른 실시예에 따른 세라믹 회로 기판의 개념도이다.4 is a conceptual diagram of a ceramic circuit board according to another embodiment of the present invention.
도 5 내지 8은 본 발명의 또 다른 실시예들에 따른 세라믹 회로 기판의 개념도들이다.5 to 8 are conceptual views of a ceramic circuit board according to still other embodiments of the present invention.
이하에서 첨부된 도면들을 참조하여 본 발명의 실시예에 대해 상세하게 설명한다. 그러나 본 발명은 이하에서 개시되는 실시예에 한정되는 것이 아니라 서로 다른 다양한 형태로 구현될 것이며, 단지 본 실시예는 본 발명의 개시가 완전하도록 하며, 통상의 지식을 가진 자에게 발명의 범주를 완전하게 알려주기 위해 제공되는 것이다.Hereinafter, an embodiment of the present invention will be described in detail with reference to the accompanying drawings. However, the present invention is not limited to the embodiments disclosed below, but will be implemented in various different forms, only this embodiment allows the disclosure of the present invention to be complete, and the scope of the invention to those of ordinary skill in the art completely It is provided to inform you.
도 1은 본 발명의 일실시예에 따른 세라믹 회로 기판의 개념도이다. 도 1에 도시된 바와 같이, 본 발명의 일실시예에 따른 세라믹 회로 기판(100)은 제1면(도 1에서 상면)과 제1면과 나란한 제2면(도 1에서 하면)을 구비한 세라믹 기판(10)과 세라믹 기판(10)의 제1면 위에 형성된 복수의 구리 층들을 포함하는 전도성 패턴(20)과 세라믹 기판의 제2면 위에 형성된 복수의 휨 방지 층들(30)을 포함한다.1 is a conceptual diagram of a ceramic circuit board according to an embodiment of the present invention. As shown in FIG. 1 , a ceramic circuit board 100 according to an embodiment of the present invention has a first surface (top surface in FIG. 1 ) and a second surface (bottom surface in FIG. 1 ) parallel to the first surface. The ceramic substrate 10 includes a conductive pattern 20 including a plurality of copper layers formed on the first surface of the ceramic substrate 10 and a plurality of anti-warpage layers 30 formed on the second surface of the ceramic substrate.
세라믹 기판(10)은, 예를 들어, Al2O3, AlN, ZTA, Si3N4 등의 세라믹 재질로 이루어진 기판일 수 있다.The ceramic substrate 10 is, for example, Al 2 O 3 , AlN, ZTA, Si 3 N 4 , etc. The substrate may be made of a ceramic material.
전도성 패턴(20)은 제1면 위에 순차적으로 형성된 제1 구리 층(21), 제2 구리 층(22) 및 제3 구리 층(23)을 포함한다. 제1 구리 층(21)에는 글라스 성분이 포함되며, 제2 구리 층(22) 및 제3 구리 층(23)에는 글라스 성분이 포함되지 않는다.The conductive pattern 20 includes a first copper layer 21 , a second copper layer 22 , and a third copper layer 23 sequentially formed on the first surface. The first copper layer 21 includes a glass component, and the second copper layer 22 and the third copper layer 23 do not include a glass component.
휨 방지 층들(30)은 제2면 위에 순차적으로 형성된 제1 휨 방지 층(31), 제2 휨 방지 층(32) 및 제3 휨 방지 층(33)을 포함한다. 휨 방지 층들(30)은 전도성 패턴(20)을 형성하기 위한 소결 과정에서 세라믹 기판(10)이 휘는 것을 방지하는 역할을 한다.The anti-warpage layers 30 include a first anti-warpage layer 31 , a second anti-warpage layer 32 and a third anti-warpage layer 33 sequentially formed on the second surface. The warpage prevention layers 30 serve to prevent the ceramic substrate 10 from being bent during a sintering process to form the conductive pattern 20 .
제1 구리 층(21)과 제1 휨 방지 층(31)이 동일한 재료로 이루어지며, 제2 구리 층(22)과 제2 휨 방지 층(32)이 동일한 재료로 이루어지며, 제3 구리 층(23)은 제3 휨 방지 층(33)과 동일한 재료로 이루어질 수 있다.The first copper layer 21 and the first anti-warpage layer 31 are made of the same material, the second copper layer 22 and the second anti-warpage layer 32 are made of the same material, and the third copper layer (23) may be made of the same material as the third anti-warpage layer (33).
복수의 휨 방지 층들(30)의 두께는 구리 층들(21, 22, 23)의 부피의 합과 휨 방지 층들(30)의 부피의 합의 비가 0.9 내지 1.1이 되도록 조절된다.The thickness of the plurality of anti-warpage layers 30 is adjusted such that a ratio of the sum of the volumes of the copper layers 21 , 22 , and 23 to the sum of the volumes of the anti-warpage layers 30 is 0.9 to 1.1.
서로 대응하는 층들의 부피비가 0.9 내지 1.1이 되도록 조절될 수도 있다. 즉, 도 1에 도시된 실시예에서 제1 구리 층(21)과 제1 휨 방지 층(31)의 부피비는 0.9 내지 1.1이며, 제2 구리 층(22)과 제2 휨 방지 층(32)의 부피비와 제3 구리 층(23)과 제3 휨 방지 층(33)의 부피비도 0.9 내지 1.1일 수 있다.The volume ratio of the layers corresponding to each other may be adjusted to be 0.9 to 1.1. That is, in the embodiment shown in FIG. 1 , the volume ratio of the first copper layer 21 and the first anti-warpage layer 31 is 0.9 to 1.1, and the second copper layer 22 and the second anti-warpage layer 32 . The volume ratio of the third copper layer 23 and the third anti-warpage layer 33 may also be 0.9 to 1.1.
도 2는 본 발명의 일실시예에 따른 세라믹 회로 기판의 제조방법의 흐름도이다. 이하에서는 도 2를 참고하여, 도 1에 도시된 세라믹 회로 기판(100)의 제조방법을 설명한다.2 is a flowchart of a method of manufacturing a ceramic circuit board according to an embodiment of the present invention. Hereinafter, a method of manufacturing the ceramic circuit board 100 shown in FIG. 1 will be described with reference to FIG. 2 .
도 2에 도시된 바와 같이, 본 발명의 일실시예에 따른 세라믹 회로 기판(100)의 제조방법은 세라믹 기판(10)을 준비하는 단계(S1)와, 세라믹 기판(10)의 제1면 위에 제1 구리 층(21)을 형성하는 단계(S2)와, 세라믹 기판(10)의 제2면 위에 제1 휨 방지 층(31)을 형성하는 단계(S3)와, 제1 구리 층(21) 위에 제2 구리 층(22)을 형성하는 단계(S4)와, 제1 휨 방지 층(31) 위에 제2 휨 방지 층(32)을 형성하는 단계(S5)와, 제2 구리 층(22) 위에 제3 구리 층(23)을 형성하는 단계(S6)와, 제2 휨 방지 층(32) 위에 제3 휨 방지 층(33)을 형성하는 단계(S7)를 포함한다.As shown in FIG. 2 , the method of manufacturing a ceramic circuit board 100 according to an embodiment of the present invention includes a step ( S1 ) of preparing the ceramic substrate 10 , and a first surface of the ceramic substrate 10 . Forming the first copper layer 21 (S2), forming the first anti-warpage layer 31 on the second surface of the ceramic substrate 10 (S3), and the first copper layer 21 Forming a second copper layer 22 thereon (S4), forming a second anti-warpage layer 32 on the first anti-warpage layer 31 (S5), and a second copper layer 22 and forming a third copper layer 23 thereon ( S6 ), and forming a third anti-warpage layer 33 on the second anti-warpage layer 32 ( S7 ).
먼저, 세라믹 기판(10)을 준비하는 단계(S1)에 대해서 설명한다.First, the step S1 of preparing the ceramic substrate 10 will be described.
세라믹 기판(10)은, 상술한 바와 같이, Al2O3, AlN, ZTA(Zirconia Toughened Alumina), Si3N4 등의 세라믹 재질로 이루어진 기판일 수 있다. 세라믹 기판(10)은 제1면과 제1면에 나란한 제2면을 구비한다.As described above, the ceramic substrate 10 is made of Al 2 O 3 , AlN, Zirconia Toughened Alumina (ZTA), Si 3 N 4 , or the like. The substrate may be made of a ceramic material. The ceramic substrate 10 has a first surface and a second surface parallel to the first surface.
다음, 제1 구리 층(21)을 형성하는 단계(S2)에 대해서 설명한다.Next, the step S2 of forming the first copper layer 21 will be described.
제1 구리 층(21)은 세라믹 기판(10)의 제1면 위에 형성된다. 제1 구리 층(21)은 세라믹 기판(10)의 제1면 위에 직접 형성될 수 있다.The first copper layer 21 is formed on the first surface of the ceramic substrate 10 . The first copper layer 21 may be formed directly on the first surface of the ceramic substrate 10 .
도 3은 제1 구리 층(21)을 형성하는 단계의 흐름도이다. 도 3에 도시된 바와 같이, 제1 구리 층(21)을 형성하는 단계는 접합 페이스트를 인쇄하는 단계(S21), 접합 페이스트 층을 건조하는 단계(S22), 건조된 접합 페이스트 층을 압착하는 단계(S23) 및 접합 페이스트 층을 소결하는 단계(S24)를 포함한다.3 is a flowchart of the step of forming the first copper layer 21 . As shown in FIG. 3 , the step of forming the first copper layer 21 includes printing the bonding paste ( S21 ), drying the bonding paste layer ( S22 ), and pressing the dried bonding paste layer. (S23) and sintering the bonding paste layer (S24).
접합 페이스트는 스크린 프린팅 방법으로 인쇄할 수 있다.The bonding paste can be printed by a screen printing method.
접합 페이스트는 글라스 프릿(Glass Frit), 무기물 입자들, 산화구리 입자들, 구리 입자들, 용제 및 바인더를 포함한다. 글라스 프릿은 구리(Cu) 입자들의 소결을 돕는 소결조제인 동시에, 제1 구리 층(21)과 세라믹 기판(10)을 접합하는 역할을 한다. 무기물 입자들은 Al2O3, CaO, ZrO2 분말들 중 선택된 적어도 하나의 분말을 포함할 수 있다. 무기물 입자들은 접합 페이스트의 수축률을 낮추기 위해서 사용된다. 본 발명에서 페이스트의 수축률은 페이스트를 디스크 형태로 인쇄한 후 건조 및 소결하고, 건조 후와 소결 후의 디스크의 지름을 비교하는 방법으로 측정한다. 접합 페이스트의 수축률은 3% 이하인 것이 바람직하다. 산화구리(CuO, Cu2O) 입자들은 세라믹 기판(10)과의 접합 특성을 보완하기 위해서 첨가된다. 예를 들어, 세라믹 기판(10)으로 알루미나(Al2O3) 기판을 사용할 경우 산화구리가 알루미나와 반응하여 CuAlO2, CuAl2O4를 형성함으로써 접합 특성이 향상될 수 있다.The bonding paste includes glass frit, inorganic particles, copper oxide particles, copper particles, a solvent and a binder. The glass frit is a sintering aid that helps sinter the copper (Cu) particles, and serves to bond the first copper layer 21 and the ceramic substrate 10 . The inorganic particles may include at least one powder selected from Al 2 O 3 , CaO, and ZrO 2 powders. Inorganic particles are used to lower the shrinkage of the bonding paste. In the present invention, the shrinkage rate of the paste is measured by printing the paste in the form of a disk, drying and sintering, and comparing the diameter of the disk after drying and sintering. The shrinkage rate of the bonding paste is preferably 3% or less. Copper oxide (CuO, Cu 2 O) particles are added to supplement bonding properties with the ceramic substrate 10 . For example, when an alumina (Al 2 O 3 ) substrate is used as the ceramic substrate 10 , copper oxide reacts with alumina to form CuAlO 2 , CuAl 2 O 4 , thereby improving bonding properties.
인쇄 후 접합 페이스트 층을 건조하여, 용제를 제거한다.After printing, the bonding paste layer is dried to remove the solvent.
다음으로, 건조된 접합 페이스트 층을 압착하여, 접합 페이스트 층의 높이 차이를 줄인다. 인쇄 시 접합 페이스트 층의 경계부는 페이스트의 흐름 속도가 감소하여 페이스트의 중심부에 비해서 점도가 높다. 따라서 인쇄 후 건조된 접합 페이스트 층의 경계부는 중심부에 비해서 두께가 두껍다.Next, the dried bonding paste layer is compressed to reduce the height difference between the bonding paste layers. During printing, the boundary of the bonding paste layer has a higher viscosity than the center of the paste because the flow rate of the paste decreases. Therefore, the boundary of the dried bonding paste layer after printing is thicker than the central portion.
다음으로, 압착된 접합 페이스트 층이 형성된 세라믹 기판(10)을 열처리하여 접합 페이스트 층을 소결함으로써 제1 구리 층(21)을 형성한다. 접합 페이스트 층을 소결하는 열처리 프로파일은, 바인더를 제거하기 위해서 질소 분위기에 수증기나 산소를 소량 공급하는 베이크 아웃(bake out) 단계와, 구리(Cu) 입자들을 액상 소결하는 단계와, 냉각하는 단계를 포함한다.Next, the first copper layer 21 is formed by sintering the bonding paste layer by heat-treating the ceramic substrate 10 on which the compressed bonding paste layer is formed. The heat treatment profile for sintering the bonding paste layer includes a bake out step of supplying a small amount of water vapor or oxygen to a nitrogen atmosphere in order to remove the binder, a step of liquid phase sintering of copper (Cu) particles, and a step of cooling. include
구리(Cu) 입자들을 액상 소결하는 단계는 구리(Cu)의 산화를 방지하기 위해서, 질소분위기에서 진행하는 것이 바람직하다. 이때, 글라스 프릿이 구리(Cu) 입자들에 웨팅(wetting) 되기 용이하도록, 소량의 산소를 공급할 수 있다. 베이커 아웃 단계는 300 내지 500℃ 정도로 진행되며, 액상 소결하는 단계는 700 내지 900℃ 정도로 진행될 수 있다.The liquid phase sintering of copper (Cu) particles is preferably performed in a nitrogen atmosphere in order to prevent oxidation of copper (Cu). In this case, a small amount of oxygen may be supplied so that the glass frit is easily wetted on the copper (Cu) particles. The bake-out step may be performed at about 300 to 500°C, and the liquid-phase sintering may be performed at about 700 to 900°C.
전체 소결에 소요되는 시간은 대략 50 내지 90분 정도이며, 머플 타입 열처리로와 같은 연속식 열처리로에서 진행되거나 박스 오븐과 같은 배치 타입 열처리로에서 진행될 수 있다.The total sintering time is about 50 to 90 minutes, and may be performed in a continuous heat treatment furnace such as a muffle type heat treatment furnace or a batch type heat treatment furnace such as a box oven.
다음, 제1 휨 방지 층(31)을 형성하는 단계(S3)에 대해서 설명한다.Next, the step of forming the first warpage prevention layer 31 ( S3 ) will be described.
제1 휨 방지 층(31)은 세라믹 기판(10)의 제2면 위에 형성된다. 제1 휨 방지 층(31)은 세라믹 기판(10)의 제2면 위에 직접 형성될 수 있다. 제1 휨 방지 층(31)은 제1 구리 층(21)과 마찬가지로, 접합 페이스트를 인쇄하는 단계, 접합 페이스트 층을 건조하는 단계, 건조된 접합 페이스트 층을 압착하는 단계 및 접합 페이스트 층을 소결하는 단계를 통해서 형성된다.The first anti-warpage layer 31 is formed on the second surface of the ceramic substrate 10 . The first anti-warpage layer 31 may be formed directly on the second surface of the ceramic substrate 10 . The first anti-warpage layer 31, like the first copper layer 21, is formed through the steps of printing the bonding paste, drying the bonding paste layer, pressing the dried bonding paste layer, and sintering the bonding paste layer. formed through steps.
제1 휨 방지 층(31)은 세라믹 기판(10)의 제2면 전면을 덮는 형태로 형성될 수 있다.The first anti-warpage layer 31 may be formed to cover the entire second surface of the ceramic substrate 10 .
제1 휨 방지 층(31)은 제1 구리 층(21)과 함께 형성된다. 세라믹 기판(10)의 제1면과 제2면에 각각 접합 페이스트를 인쇄한 후, 양면의 접합 페이스트 층을 한꺼번에 건조하고, 압착한 후 한꺼번에 소결하여 제1 휨 방지 층(31)과 제1 구리 층(21)을 한 번에 형성한다.The first anti-warpage layer 31 is formed together with the first copper layer 21 . After each bonding paste is printed on the first and second surfaces of the ceramic substrate 10, the bonding paste layers on both sides are dried at once, pressed and sintered at once to form the first anti-warpage layer 31 and the cuprous copper Layer 21 is formed at a time.
다음, 제2 구리 층(22)을 형성하는 단계(S4)에 대해서 설명한다.Next, the step of forming the second copper layer 22 ( S4 ) will be described.
제2 구리 층(22)은 제1 구리 층(21) 위에 형성된다. 제2 구리 층(22)은 적층 페이스트를 인쇄한 후 건조, 압착 및 소결하여 형성한다. 제2 구리 층(22)은 전도성 패턴(20)의 두께를 증가시키는 역할을 한다.A second copper layer 22 is formed over the first copper layer 21 . The second copper layer 22 is formed by printing the lamination paste and then drying, pressing and sintering. The second copper layer 22 serves to increase the thickness of the conductive pattern 20 .
적층 페이스트는 무기물 입자들, 구리 입자들, 용제 및 바인더를 포함한다. 무기물 입자들은 Al2O3, CaO, ZrO2 입자들 중 선택된 적어도 하나의 입자들을 포함할 수 있다. 무기물 입자들은 접합 페이스트의 수축률을 낮추기 위해서 사용된다. 적층 페이스트는 접합 페이스트와 달리 글라스 프릿을 포함하지 않는다. 적층 페이스트는 접합 페이스트에 비해서 수축률이 높다. 적층 페이스트의 수축률은 3% 내지 9%인 것이 바람직하다.The lamination paste contains inorganic particles, copper particles, a solvent and a binder. The inorganic particles may include at least one selected from among Al 2 O 3 , CaO, and ZrO 2 particles. Inorganic particles are used to lower the shrinkage of the bonding paste. Lamination paste does not contain glass frit unlike bonding paste. Lamination pastes have a higher shrinkage rate than bonding pastes. It is preferable that the shrinkage ratio of the lamination paste is 3% to 9%.
인쇄는 스크린 프린팅 방법으로 진행할 수 있다. 인쇄 후 적층 페이스트 층을 건조하여, 용제를 제거한다. 그리고 건조된 적층 페이스트 층을 압착하여, 접합 페이스트 층의 높이 차이를 줄인다. 다음으로, 제1 구리 층(21)과 압착된 적층 페이스트 층이 형성된 세라믹 기판(10)을 열처리함으로써, 적층 페이스트 층을 소결하여, 제2 구리 층(22)을 형성한다. 열처리는 접합 페이스트 층의 열처리와 마찬가지로 소량의 산소가 포함된 질소 분위기에서 진행될 수 있다.Printing may be performed by a screen printing method. After printing, the lamination paste layer is dried to remove the solvent. Then, the dried lamination paste layer is compressed to reduce the height difference between the bonding paste layers. Next, by heat-treating the ceramic substrate 10 on which the first copper layer 21 and the pressed lamination paste layer are formed, the lamination paste layer is sintered to form the second copper layer 22 . Like the heat treatment of the bonding paste layer, the heat treatment may be performed in a nitrogen atmosphere containing a small amount of oxygen.
300㎛ 이상의 두꺼운 전도성 패턴이 요구되는 경우에는 제2 구리 층(22)을 형성하는 단계를 복수 회 실시하거나, 인쇄, 건조, 압착 과정만을 복수 회 실시할 수도 있다.When a thick conductive pattern of 300 μm or more is required, the step of forming the second copper layer 22 may be performed multiple times, or only the printing, drying, and pressing processes may be performed multiple times.
다음, 제2 휨 방지 층(32)을 형성하는 단계(S5)에 대해서 설명한다.Next, the step (S5) of forming the second warpage prevention layer 32 will be described.
제2 휨 방지 층(32)은 제1 휨 방지 층(31) 위에 형성된다. 제2 휨 방지 층(32)은 제2 구리 층(22)과 마찬가지로, 적층 페이스트를 인쇄하는 단계, 적층 페이스트 층을 건조하는 단계, 건조된 적층 페이스트 층을 압착하는 단계 및 적층 페이스트 층을 소결하는 단계를 통해서 형성된다.The second anti-warpage layer 32 is formed over the first anti-warpage layer 31 . The second anti-warpage layer 32, like the second copper layer 22, is formed through the steps of printing the lamination paste, drying the lamination paste layer, pressing the dried lamination paste layer, and sintering the lamination paste layer. formed through steps.
제2 휨 방지 층(32)은 제2 구리 층(22)과 함께 형성된다.The second anti-warpage layer 32 is formed together with the second copper layer 22 .
다음, 제3 구리 층(23)을 형성하는 단계(S6)에 대해서 설명한다.Next, the step of forming the third copper layer 23 ( S6 ) will be described.
제3 구리 층(23)은 제2 구리 층(22) 위에 형성된다. 제3 구리 층(23)은 표층 페이스트를 인쇄한 후 건조, 압착 및 소결하여 형성한다. 제3 구리 층(23)은 도금이 용이한 치밀한 표면을 제공하는 역할을 한다.A third copper layer 23 is formed over the second copper layer 22 . The third copper layer 23 is formed by printing the surface layer paste and then drying, pressing and sintering. The third copper layer 23 serves to provide a dense surface for easy plating.
표층 페이스트는 글라스 프릿을 포함하지 않으며, 산화구리(Cu2O) 입자들, 구리 입자들, 용제 및 바인더를 포함한다. 구리 입자들은 평균 입경이 1 내지 5㎛ 미세 구리 입자들을 포함한다. 미세 구리 입자들은 표층 페이스트에 5 내지 60중량% 포함된다. 미세 구리 입자들은 제3 구리 층(23)의 밀도를 높이는 역할을 한다. 산화구리(Cu2O) 입자들은 소결 과정에서 공정 액상을 형성할 수 있다. 표층 페이스트는 수축률은 10% 내지 15%인 것이 바람직하다. The surface layer paste does not contain a glass frit, but contains copper oxide (Cu2O) particles, copper particles, a solvent, and a binder. The copper particles include fine copper particles having an average particle diameter of 1 to 5 μm. The fine copper particles are contained in an amount of 5 to 60% by weight in the surface layer paste. The fine copper particles serve to increase the density of the third copper layer 23 . Copper oxide (Cu 2 O) particles may form a process liquid phase during the sintering process. The surface layer paste preferably has a shrinkage ratio of 10% to 15%.
인쇄는 스크린 프린팅 방법으로 진행할 수 있다. 인쇄 후 표층 페이스트 층을 건조하여, 용제를 제거한다. 그리고 건조된 표층 페이스트 층을 압착하여, 표층 페이스트 층의 높이 차이를 줄인다. 다음으로, 제1 구리 층(21), 제2 구리 층(22) 및 압착된 표층 페이스트 층이 형성된 세라믹 기판(10)을 열처리하여 표층 페이스트 층을 소결함으로써, 제3 구리 층(23)을 형성한다. 열처리는 접합 페이스트 층의 열처리와 마찬가지로 소량의 산소가 포함된 질소 분위기에서 진행될 수 있다.Printing may be performed by a screen printing method. After printing, the surface paste layer is dried to remove the solvent. And by compressing the dried surface paste layer, the height difference between the surface paste layer is reduced. Next, the third copper layer 23 is formed by heat-treating the ceramic substrate 10 on which the first copper layer 21 , the second copper layer 22 and the pressed surface paste layer are formed to sinter the surface paste layer. do. Like the heat treatment of the bonding paste layer, the heat treatment may be performed in a nitrogen atmosphere containing a small amount of oxygen.
다음, 제3 휨 방지 층(33)을 형성하는 단계(S7)에 대해서 설명한다.Next, the step (S7) of forming the third anti-warpage layer 33 will be described.
제3 휨 방지 층(33)은 제2 휨 방지 층(32) 위에 형성된다. 제3 휨 방지 층(33)은 제3 구리 층(23)과 마찬가지로, 표층 페이스트를 인쇄하는 단계, 표층 페이스트 층을 건조하는 단계, 건조된 표층 페이스트 층을 압착하는 단계 및 표층 페이스트 층을 소결하는 단계를 통해서 형성된다.The third anti-warpage layer 33 is formed over the second anti-warpage layer 32 . As with the third copper layer 23, the third anti-warpage layer 33 is formed by printing the surface paste, drying the surface paste layer, pressing the dried surface paste layer, and sintering the surface paste layer. formed through steps.
제3 휨 방지 층(33)은 제3 구리 층(23)과 함께 형성된다.The third anti-warpage layer 33 is formed together with the third copper layer 23 .
상술한 휨 방지 층들(31, 32, 33)을 형성하는 단계들에서, 제1 휨 방지 층의 두께, 제2 휨 방지 층의 두께 및 제3 휨 방지 층의 두께는 제1 구리 층, 제2 구리 층 및 제3 구리 층의 부피의 합과 제1 휨 방지 층, 제2 휨 방지 층 및 제3 휨 방지 층의 부피의 합의 비가 0.9 내지 1.1이 되도록 조절된다. In the above-described steps of forming the anti-warpage layers 31, 32, 33, the thickness of the first anti-warpage layer, the thickness of the second anti-warpage layer, and the thickness of the third anti-warpage layer are the first copper layer, the second The ratio of the sum of the volumes of the copper layer and the third copper layer to the sum of the volumes of the first, second, and third anti-warpage layers is adjusted to be 0.9 to 1.1.
이때, 서로 대응하는 층들의 부피비가 0.9 내지 1.1이 되도록 조절될 수도 있다. 즉, 제1 휨 방지 층(31)의 두께는 제1 구리 층(21)과 제1 휨 방지 층(31)의 부피비가 0.9 내지 1.1이 되도록 조절되고, 제2 휨 방지 층(32)의 두께는 제2 구리 층(22)과 제2 휨 방지 층(32)의 부피비가 0.9 내지 1.1이 되도록 조절되고, 제3 휨 방지 층(33)의 두께는 제3 구리 층(23)과 제3 휨 방지 층(33)의 부피비가 0.9 내지 1.1이 되도록 조절될 수 있다.In this case, the volume ratio of the layers corresponding to each other may be adjusted to be 0.9 to 1.1. That is, the thickness of the first anti-warpage layer 31 is adjusted so that the volume ratio of the first copper layer 21 and the first anti-warpage layer 31 is 0.9 to 1.1, and the thickness of the second anti-warpage layer 32 is adjusted so that the volume ratio of the second copper layer 22 and the second anti-warpage layer 32 is 0.9 to 1.1, and the thickness of the third anti-warpage layer 33 is the third copper layer 23 and the third warpage The volume ratio of the barrier layer 33 may be adjusted to be 0.9 to 1.1.
도 4는 본 발명의 다른 실시예에 따른 세라믹 회로 기판의 개념도이다.4 is a conceptual diagram of a ceramic circuit board according to another embodiment of the present invention.
본 실시예에 따른 세라믹 회로 기판(200)은 일부 전도성 패턴(120)의 두께가 다른 패턴(20)의 두께에 비해서 두껍다는 점에서 도 1에 도시된 실시예와 차이가 있다. 본 실시예는 높이 차이가 있는 반도체 소자들을 실장하기 위해서 별도의 스페이서가 필요하지 않다는 점에서 장점이 있다.The ceramic circuit board 200 according to the present embodiment is different from the embodiment shown in FIG. 1 in that the thickness of some conductive patterns 120 is thicker than the thickness of other patterns 20 . The present embodiment has an advantage in that a separate spacer is not required to mount semiconductor devices having different heights.
두꺼운 패턴(120)에는 제3 구리 층(23) 위에 제4 구리 층(122)과 제5 구리 층(123)이 형성되어 있다. 제4 구리 층(122)은 제3 구리 층(23) 위에 적층 페이스트를 인쇄한 후, 건조, 압착 및 소결하여 형성할 수 있으며, 제5 구리 층(123)은 제4 구리 층(122) 위에 표층 페이스트를 인쇄한 후, 건조, 압착 및 소결하여 형성할 수 있다. 제4 구리 층(122)은 제2 구리 층(22)과 동일한 재질일 수 있다. 제5 구리 층(123)은 제3 구리 층(23)과 동일한 재질일 수 있다.In the thick pattern 120 , a fourth copper layer 122 and a fifth copper layer 123 are formed on the third copper layer 23 . The fourth copper layer 122 may be formed by printing a lamination paste on the third copper layer 23 and then drying, pressing, and sintering, and the fifth copper layer 123 is formed on the fourth copper layer 122 . After printing the surface layer paste, it can be formed by drying, pressing and sintering. The fourth copper layer 122 may be made of the same material as the second copper layer 22 . The fifth copper layer 123 may be made of the same material as the third copper layer 23 .
그리고 제3 휨 방지 층(33) 위에 제4 휨 방지 층(132)과 제5 휨 방지 층(133)이 형성되어 있다 점에서 도 1에 도시된 실시예와 차이가 있다. 제4 휨 방지 층(132)은 제2 구리 층(22)과 동일한 재질일 수 있으며, 제5 휨 방지 층(133)은 제3 구리 층(23)과 동일한 재질일 수 있다.And it is different from the embodiment shown in FIG. 1 in that the fourth anti-warpage layer 132 and the fifth anti-warpage layer 133 are formed on the third anti-warpage layer 33 . The fourth anti-warping layer 132 may be made of the same material as the second copper layer 22 , and the fifth anti-warping layer 133 may be made of the same material as the third copper layer 23 .
복수의 휨 방지 층들(130)의 두께는 구리 층들(20, 120)의 부피의 합과 휨 방지 층들(130)의 부피의 합의 비가 0.9 내지 1.1이 되도록 조절된다.The thickness of the plurality of anti-warpage layers 130 is adjusted such that a ratio of the sum of the volumes of the copper layers 20 and 120 to the sum of the volumes of the anti-warpage layers 130 is 0.9 to 1.1.
제4 휨 방지 층(132)은 제4 구리 층(122)과 함께 형성된다. 제5 휨 방지 층(133)은 제5 구리 층(123)과 함께 형성된다.The fourth anti-warpage layer 132 is formed together with the fourth copper layer 122 . The fifth anti-warpage layer 133 is formed together with the fifth copper layer 123 .
도 5는 본 발명의 또 다른 실시예에 따른 세라믹 회로 기판의 개념도이다.5 is a conceptual diagram of a ceramic circuit board according to another embodiment of the present invention.
도 5에 도시된 실시예는 제3 구리 층이 없다는 점에서 도 1에 도시된 실시예와 차이가 있다. 두꺼운 전도성 패턴이 필요하지 않은 세라믹 회로 기판(300)의 경우에는 제3 구리 층을 생략할 수 있다. 본 실시예의 세라믹 회로 기판(300)은 표층 페이스트를 인쇄하는 과정을 생략하는 방법으로 제조할 수 있다.The embodiment shown in FIG. 5 is different from the embodiment shown in FIG. 1 in that there is no third copper layer. In the case of the ceramic circuit board 300 that does not require a thick conductive pattern, the third copper layer may be omitted. The ceramic circuit board 300 of the present embodiment may be manufactured by omitting the process of printing the surface layer paste.
도 6은 본 발명의 또 다른 실시예에 따른 세라믹 회로 기판의 개념도이다.6 is a conceptual diagram of a ceramic circuit board according to another embodiment of the present invention.
도 6에 도시된 실시예는 제4 휨 방지 층(132)과 제5 휨 방지 층(133)이 없다는 점에서 도 4에 도시된 실시예와 차이가 있다. 또한, 도 6에 도시된 실시예에서는 제2 휨 방지 층(232)과 제3 휨 방지 층(233)의 두께가 도 4에 도시된 실시예의 제2 휨 방지 층(32)과 제3 휨 방지 층(33)의 두께에 비해서 다소 두껍다는 점에서도 도 4에 도시된 실시예와 차이가 있다.The embodiment shown in FIG. 6 is different from the embodiment shown in FIG. 4 in that the fourth anti-warpage layer 132 and the fifth anti-warpage layer 133 are absent. In addition, in the embodiment shown in FIG. 6 , the thickness of the second anti-warping layer 232 and the third anti-warping layer 233 is the second anti-warping layer 32 and the third anti-warpage of the embodiment shown in FIG. 4 . It is also different from the embodiment shown in FIG. 4 in that it is slightly thicker than the thickness of the layer 33 .
도 6에 도시된 실시예에서는 도 4에 도시된 제4 휨 방지 층(132)과 제5 휨 방지 층(133)을 형성하는 대신에 제2 휨 방지 층(232)과 제3 휨 방지 층(233)의 두께를 제4 휨 방지 층(132)과 제5 휨 방지 층(133)의 두께만큼 더 두껍게 형성함으로써, 구리 층들(20, 120)의 부피의 합과 휨 방지 층들(230)의 부피의 합의 비가 0.9 내지 1.1이 되도록 조절된다.In the embodiment shown in Fig. 6, instead of forming the fourth anti-warpage layer 132 and the fifth anti-warpage layer 133 shown in Fig. 4, the second anti-warpage layer 232 and the third anti-warpage layer ( By forming the thickness of 233 to be thicker by the thickness of the fourth anti-warpage layer 132 and the fifth anti-warpage layer 133 , the sum of the volumes of the copper layers 20 and 120 and the volume of the anti-warpage layers 230 . It is adjusted so that the ratio of the sum of is 0.9 to 1.1.
도 7과 8은 본 발명의 또 다른 실시예들에 따른 세라믹 회로 기판의 개념도들이다. 도 7에 도시된 실시예는 제4 휨 방지 층(332)과 제5 휨 방지 층(333)이 세라믹 기판(10)의 표면 전체에 형성되지 않고, 패턴을 형성한다는 점에서 도 4에 도시된 실시예와 차이가 있다.7 and 8 are conceptual views of a ceramic circuit board according to still other embodiments of the present invention. The embodiment shown in FIG. 7 is shown in FIG. 4 in that the fourth anti-warpage layer 332 and the fifth anti-warpage layer 333 are not formed on the entire surface of the ceramic substrate 10, but form a pattern. There is a difference from the embodiment.
도 8에 도시된 실시예는 일부 제5 구리 층 위(123)에 제6 구리 층(222)과 제7 구리 층(223)이 형성된다는 점에서 도 7에 도시된 실시예와 차이가 있다. 또한, 구리 층들(20, 120, 220)과 휨 방지 층들(430)의 부피비를 유지하기 위해서 제4 휨 방지 층(432)과 제5 휨 방지 층(433)이 도 7에 도시된 실시예에 비해서 다소 두껍다는 점에서도 차이가 있다.The embodiment illustrated in FIG. 8 is different from the embodiment illustrated in FIG. 7 in that a sixth copper layer 222 and a seventh copper layer 223 are formed on a part of the fifth copper layer 123 . In addition, in order to maintain the volume ratio of the copper layers 20, 120, 220 and the anti-warpage layers 430, a fourth anti-warpage layer 432 and a fifth anti-warpage layer 433 are provided in the embodiment shown in FIG. There is also a difference in that it is slightly thicker than that.
이상에서 본 발명의 바람직한 실시예에 대해 도시하고 설명하였으나, 본 발명은 상술한 특정의 바람직한 실시예에 한정되지 아니하며, 청구범위에서 청구하는 본 발명의 요지를 벗어남이 없이 당해 발명이 속하는 기술분야에서 통상의 지식을 가진 자라면 누구든지 다양한 변형 실시가 가능한 것은 물론이고, 그와 같은 변경은 청구범위 기재의 범위 내에 있게 된다.Although preferred embodiments of the present invention have been illustrated and described above, the present invention is not limited to the specific preferred embodiments described above, and in the technical field to which the present invention belongs, without departing from the gist of the present invention as claimed in the claims Any person skilled in the art can make various modifications, of course, and such modifications are within the scope of the claims.
예를 들어, 상술한 실시예들에서는 구리 페이스트의 인쇄 및 건조 단계별로 압착도 진행하는 것으로 설명하였으나, 압착과 소결은 반드시 단계별로 진행할 필요는 없다. 몇 개의 층이 쌓인 후 한 번에 압착을 할 수도 있으며, 소결은 한 번에 진행할 수도 있다. 예를 들어, 접합 페이스트를 인쇄 및 건조한 후 그 위에 적층 페이스트를 인쇄 및 건조한 후에 압착을 하고, 그 위에 표층 페이스를 인쇄 및 건조한 후에 다시 압착하고, 한꺼번에 소결을 진행할 수도 있다. 어느 단계에서 압착을 하고, 소결을 할 것인지는 필요에 따라서 적절하게 선택할 수 있다.For example, in the above-described embodiments, although it has been described that compression is performed in each step of printing and drying the copper paste, compression and sintering are not necessarily performed step by step. After several layers are stacked, pressing can be done at once, and sintering can be done at once. For example, after printing and drying the bonding paste, pressing after printing and drying the lamination paste thereon, printing and drying the surface layer face thereon, pressing again, and sintering may be performed at once. At which stage compression is performed and sintering is performed, it can be appropriately selected according to need.
<부호의 설명><Explanation of code>
100, 200, 300, 400, 500, 600: 세라믹 회로 기판100, 200, 300, 400, 500, 600: ceramic circuit board
10: 세라믹 기판10: ceramic substrate
20, 120, 220: 전도성 패턴20, 120, 220: conductive pattern
30, 130, 230, 330, 430: 휨 방지 층들30, 130, 230, 330, 430: anti-warpage layers
21: 제1 구리 층21: first copper layer
22: 제2 구리 층22: second copper layer
23: 제3 구리 층23: third copper layer
31, 231: 제1 휨 방지 층31, 231: first anti-warpage layer
32, 232: 제2 휨 방지 층32, 232: second anti-warpage layer
33, 233: 제3 휨 방지 층33, 233: third anti-warpage layer
122: 제4 구리 층122: fourth copper layer
123: 제5 구리 층123: fifth copper layer
132, 332, 432: 제4 휨 방지 층132, 332, 432: fourth anti-warpage layer
133, 333, 433: 제5 휨 방지 층133, 333, 433: fifth anti-warpage layer

Claims (12)

  1. 세라믹 기판에 구리 페이스트 층을 인쇄하여 구리 패턴을 형성하는 세라믹 회로 기판의 제조방법으로서,A method of manufacturing a ceramic circuit board for forming a copper pattern by printing a layer of copper paste on the ceramic substrate, the method comprising:
    제1면과 제1면에 나란한 제2면을 구비하는 세라믹 기판을 준비하는 단계와,Preparing a ceramic substrate having a first surface and a second surface parallel to the first surface;
    상기 세라믹 기판의 제1면 위에 복수의 구리 층들을 형성하는 단계를 포함하며,forming a plurality of copper layers on the first surface of the ceramic substrate;
    상기 복수의 구리 층들을 형성하는 단계는,Forming the plurality of copper layers comprises:
    상기 세라믹 기판의 제1면 위에 접합 페이스트를 인쇄한 후 건조하여 접합 페이스트 층을 형성하고, 건조된 상기 접합 페이스트 층을 압착한 후 소결하여 제1 구리 층을 형성하는 단계와,forming a first copper layer by printing a bonding paste on the first surface of the ceramic substrate and drying it to form a bonding paste layer, pressing and sintering the dried bonding paste layer;
    상기 제1 구리 층 위에 적층 페이스트를 인쇄한 후 건조하여 적층 페이스트 층을 형성하고, 건조된 상기 적층 페이스트 층을 압착한 후 소결하여 제2 구리 층을 형성하는 단계를 포함하는 것을 특징으로 하는 세라믹 회로 기판의 제조방법.and printing a lamination paste on the first copper layer, drying the lamination paste layer, and compressing and sintering the dried lamination paste layer to form a second copper layer. A method for manufacturing a substrate.
  2. 제1항에 있어서,According to claim 1,
    상기 복수의 구리 층들을 형성하는 단계는,Forming the plurality of copper layers comprises:
    상기 제2 구리 층 위에 글라스 프릿을 포함하지 않으며, 산화구리(Cu2O) 입자들과 평균 입경이 1 내지 5㎛인 미세 구리 입자들을 5 내지 60중량% 포함하는 수축률이 10% 내지 15%인 표층 페이스트를 인쇄한 후 건조 및 소결하여 제3 구리 층을 형성하는 단계를 더 포함하는 것을 특징으로 하는 세라믹 회로 기판의 제조방법.The second copper layer does not contain a glass frit, and includes copper oxide (Cu 2 O) particles and fine copper particles having an average particle diameter of 1 to 5 μm in an amount of 5 to 60% by weight and a shrinkage ratio of 10% to 15% The method of manufacturing a ceramic circuit board, characterized in that it further comprises the step of forming a third copper layer by drying and sintering the surface paste after printing.
  3. 제1항에 있어서,According to claim 1,
    상기 세라믹 기판의 제2면 위에 복수의 휨 방지 층들을 형성하는 단계를 더 포함하며,Further comprising the step of forming a plurality of anti-warpage layers on the second surface of the ceramic substrate,
    상기 복수의 휨 방지 층들을 형성하는 단계에서, 상기 복수의 휨 방지 층들의 두께는 상기 구리 층들의 부피의 합과 상기 휨 방지 층들의 부피의 합의 비가 0.9 내지 1.1이 되도록 조절되는 것을 특징으로 하는 세라믹 회로 기판의 제조방법.In the step of forming the plurality of anti-warpage layers, the thickness of the plurality of anti-warpage layers is adjusted so that the ratio of the sum of the volumes of the copper layers to the sum of the volumes of the anti-warpage layers is 0.9 to 1.1. A method for manufacturing a circuit board.
  4. 제3항에 있어서,4. The method of claim 3,
    상기 복수의 휨 방지 층들을 형성하는 단계는,Forming the plurality of anti-warpage layers comprises:
    상기 제2면 위에 접합 페이스트를 인쇄한 후 건조 및 소결하여 제1 휨 방지 층을 형성하는 단계와,forming a first anti-warpage layer by printing a bonding paste on the second surface and drying and sintering;
    상기 제1 휨 방지 층 위에 적층 페이스트를 인쇄한 후 건조 및 소결하여 제2 휨 방지 층을 형성하는 단계를 포함하며,and printing a lamination paste on the first anti-warpage layer, followed by drying and sintering to form a second anti-warpage layer,
    상기 제1 휨 방지 층의 두께와 상기 제2 휨 방지 층의 두께는 상기 제1 구리 층 및 상기 제2 구리 층의 부피의 합과 상기 제1 휨 방지 층 및 상기 제2 휨 방지 층의 부피의 합의 비가 0.9 내지 1.1이 되도록 조절되는 것을 특징으로 하는 세라믹 회로 기판의 제조방법.The thickness of the first anti-warpage layer and the thickness of the second anti-warpage layer are the sum of the volumes of the first copper layer and the second copper layer and the volume of the first anti-warpage layer and the second anti-warpage layer A method of manufacturing a ceramic circuit board, characterized in that the ratio of the sum is adjusted to be 0.9 to 1.1.
  5. 제4항에 있어서,5. The method of claim 4,
    상기 제1 휨 방지 층의 두께는 상기 제1 구리 층의 부피와 상기 제1 휨 방지 층의 부피의 비가 0.9 내지 1.1이 되도록 조절되며,The thickness of the first anti-warpage layer is adjusted so that the ratio of the volume of the first copper layer to the volume of the first anti-warpage layer is 0.9 to 1.1,
    상기 제2 휨 방지 층의 두께는 상기 제2 구리 층의 부피와 상기 제2 휨 방지 층의 부피의 비가 0.9 내지 1.1이 되도록 조절되는 것을 특징으로 하는 세라믹 회로 기판의 제조방법.The thickness of the second anti-warpage layer is a method of manufacturing a ceramic circuit board, characterized in that the ratio of the volume of the second copper layer to the volume of the second anti-warpage layer is adjusted to be 0.9 to 1.1.
  6. 제2항에 있어서,3. The method of claim 2,
    상기 제2면 위에 접합 페이스트를 인쇄한 후 건조 및 소결하여 제1 휨 방지 층을 형성하는 단계와,forming a first anti-warpage layer by printing a bonding paste on the second surface and drying and sintering;
    상기 제1 휨 방지 층 위에 적층 페이스트를 인쇄한 후 건조 및 소결하여 제2 휨 방지 층을 형성하는 단계와,After printing the lamination paste on the first anti-warpage layer, drying and sintering to form a second anti-warpage layer;
    상기 제2 휨 방지 층 위에 표층 페이스트를 인쇄한 후 건조 및 소결하여 제3 휨 방지 층을 형성하는 단계를 더 포함하며,Further comprising the step of printing a surface layer paste on the second anti-warpage layer, followed by drying and sintering to form a third anti-warpage layer,
    상기 제1 휨 방지 층의 두께, 상기 제2 휨 방지 층의 두께 및 상기 제3 휨 방지 층의 두께는 상기 제1 구리 층, 상기 제2 구리 층 및 상기 제3 구리 층의 부피의 합과 상기 제1 휨 방지 층, 상기 제2 휨 방지 층 및 상기 제3 휨 방지 층의 부피의 합의 비가 0.9 내지 1.1이 되도록 조절되는 것을 특징으로 하는 세라믹 회로 기판의 제조방법.The thickness of the first anti-warpage layer, the thickness of the second anti-warpage layer, and the thickness of the third anti-warpage layer are the sum of the volumes of the first copper layer, the second copper layer and the third copper layer and the A method of manufacturing a ceramic circuit board, characterized in that the ratio of the sum of the volumes of the first anti-warping layer, the second anti-warping layer, and the third anti-warping layer is adjusted to be 0.9 to 1.1.
  7. 제6항에 있어서,7. The method of claim 6,
    상기 제1 휨 방지 층의 두께는 상기 제1 구리 층과 상기 제1 휨 방지 층의 부피비가 0.9 내지 1.1이 되도록 조절되며,The thickness of the first anti-warping layer is adjusted so that the volume ratio of the first copper layer and the first anti-warping layer is 0.9 to 1.1,
    상기 제2 휨 방지 층의 두께는 상기 제2 구리 층과 상기 제2 휨 방지 층의 부피비가 0.9 내지 1.1이 되도록 조절되며, The thickness of the second anti-warping layer is adjusted so that the volume ratio of the second copper layer and the second anti-warping layer is 0.9 to 1.1,
    상기 제3 휨 방지 층의 두께는 상기 제3 구리 층과 상기 제3 휨 방지 층의 부피비가 0.9 내지 1.1이 되도록 조절되는 것을 특징으로 하는 세라믹 회로 기판의 제조방법.The thickness of the third anti-warpage layer is a method of manufacturing a ceramic circuit board, characterized in that the volume ratio of the third copper layer and the third anti-warpage layer is adjusted to be 0.9 to 1.1.
  8. 제2항에 있어서,3. The method of claim 2,
    상기 제3 구리 층의 위에 적층 페이스트를 인쇄한 후 건조 및 소결하여 제4 구리 층을 형성하는 단계와,forming a fourth copper layer by printing a lamination paste on the third copper layer and then drying and sintering;
    상기 제4 구리 층 위에 표층 페이스트를 인쇄한 후 건조 및 소결하여 제5 구리 층을 형성하는 단계를 더 포함하는 것을 특징으로 하는 세라믹 회로 기판의 제조방법.The method of manufacturing a ceramic circuit board according to claim 1, further comprising: printing a surface paste on the fourth copper layer and drying and sintering to form a fifth copper layer.
  9. 제1항에 있어서,According to claim 1,
    상기 접합 페이스트는 글라스 프릿(Glass Frit), 무기물 입자들, 산화구리 입자들 및 구리 입자들을 포함하는 수축률이 3% 이하인 것을 특징으로 하는 세라믹 회로 기판의 제조방법.The method of manufacturing a ceramic circuit board, characterized in that the bonding paste contains glass frit, inorganic particles, copper oxide particles, and copper particles and has a shrinkage ratio of 3% or less.
  10. 제1항에 있어서,According to claim 1,
    상기 적층 페이스트는 글라스 프릿을 포함하지 않으며, 무기물 입자들과 구리 입자들을 포함하는 수축률이 3% 내지 9%인 것을 특징으로 하는 세라믹 회로 기판의 제조방법.The method for manufacturing a ceramic circuit board, characterized in that the lamination paste does not include a glass frit and has a shrinkage ratio of 3% to 9% including inorganic particles and copper particles.
  11. 제9항 또는 제10항에 있어서,11. The method of claim 9 or 10,
    상기무기물 입자들은 Al2O3, CaO, ZrO2 분말들 중 선택된 적어도 하나의 분말을 포함하는 것을 특징으로 하는 세라믹 회로 기판의 제조방법.The inorganic particles are Al 2 O 3 , CaO, ZrO 2 Method of manufacturing a ceramic circuit board, characterized in that it comprises at least one powder selected from the powder.
  12. 세라믹 기판에 구리 페이스트 층을 인쇄하여 구리 패턴을 형성하는 세라믹 회로 기판의 제조방법으로서,A method of manufacturing a ceramic circuit board for forming a copper pattern by printing a layer of copper paste on the ceramic substrate, the method comprising:
    제1면과 제1면에 나란한 제2면을 구비하는 세라믹 기판을 준비하는 단계와,Preparing a ceramic substrate having a first surface and a second surface parallel to the first surface;
    상기 세라믹 기판의 제1면 위에 복수의 구리 층들을 형성하는 단계를 포함하며,forming a plurality of copper layers on the first surface of the ceramic substrate;
    상기 복수의 구리 층들을 형성하는 단계는,Forming the plurality of copper layers comprises:
    상기 세라믹 기판의 제1면 위에 구리 페이스트를 인쇄한 후 건조하여 구리 페이스트 층을 형성하고, 상기 구리 페이스트 층을 압착한 후 소결하는 단계를 포함하는 것을 특징으로 하는 세라믹 회로 기판의 제조방법.and printing a copper paste on the first surface of the ceramic substrate and drying the copper paste to form a copper paste layer, and sintering after pressing the copper paste layer.
PCT/KR2021/005346 2020-05-19 2021-04-28 Method for manufacturing ceramic circuit board WO2021235721A1 (en)

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