KR100691014B1 - Formative method of solder terminal - Google Patents

Formative method of solder terminal Download PDF

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Publication number
KR100691014B1
KR100691014B1 KR1020050106418A KR20050106418A KR100691014B1 KR 100691014 B1 KR100691014 B1 KR 100691014B1 KR 1020050106418 A KR1020050106418 A KR 1020050106418A KR 20050106418 A KR20050106418 A KR 20050106418A KR 100691014 B1 KR100691014 B1 KR 100691014B1
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South Korea
Prior art keywords
substrate
solder terminal
solder
protective film
ball
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KR1020050106418A
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Korean (ko)
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김진용
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주식회사 하이닉스반도체
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • G—PHYSICS
    • G03—PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
    • G03F—PHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR
    • G03F7/00—Photomechanical, e.g. photolithographic, production of textured or patterned surfaces, e.g. printing surfaces; Materials therefor, e.g. comprising photoresists; Apparatus specially adapted therefor
    • G03F7/20—Exposure; Apparatus therefor
    • G03F7/2002—Exposure; Apparatus therefor with visible light or UV light, through an original having an opaque pattern on a transparent support, e.g. film printing, projection printing; by reflection of visible or UV light from an original such as a printed image
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/34—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies not provided for in groups H01L21/0405, H01L21/0445, H01L21/06, H01L21/16 and H01L21/18 with or without impurities, e.g. doping materials
    • H01L21/46—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/428
    • H01L21/461—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/428 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/481—Internal lead connections, e.g. via connections, feedthrough structures

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Manufacturing & Machinery (AREA)
  • Non-Metallic Protective Coatings For Printed Circuits (AREA)

Abstract

A method for forming a solder terminal is provided to avoid influence of warpage by forming a solder terminal prior to a molding process. A plurality of interconnections and a via hole(112) for connecting the plurality of interconnections are formed in a substrate(110). A plurality of ball lands are formed at one side of the substrate to expose the interconnection. A solder terminal(120) is inserted into the plurality of ball lands to be exposed to the outside of one surface of the substrate. A protection film(130) is coated on one surface of the substrate on the same level of the protruding solder terminal. After the other surface of the substrate is molded, the protection film is removed by an etch process or an ultraviolet exposure process.

Description

솔더 터미널 형성방법{Formative method of solder terminal}Formatting method of solder terminal

도 1은 종래 기판에 솔더 볼이 마련된 모습을 나타낸 단면도,1 is a cross-sectional view showing a state where a solder ball is provided on a conventional substrate;

도 2a 내지 도 2d는 본 발명의 일 실시예에 따른 솔더 터미널 형성방법을 순차적으로 나타낸 단면도.2A through 2D are cross-sectional views sequentially illustrating a solder terminal forming method according to an embodiment of the present invention.

<도면의 주요부분에 대한 부호의 설명><Description of the symbols for the main parts of the drawings>

110... 기판 111... 배선110 ... PCB 111 ... Wiring

112... 비아 홀 113... 볼 랜드112 ... Via Hall 113 ... Borland

120... 솔더 터미널 130... 보호 필름120 ... solder terminal 130 ... protective film

본 발명은 솔더 터미널 형성방법에 관한 것으로서, 특히 반도체 패키지의 기판에 형성된 볼 랜드에 솔더 터미널을 형성하는 방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a solder terminal forming method, and more particularly, to a method for forming a solder terminal on a ball land formed on a substrate of a semiconductor package.

반도체 패키지는 웨이퍼 공정에 의해 만들어진 개개의 다이를 실제 전자 부품으로써 사용할 수 있도록 전기적 연결을 해주고, 외부의 충격으로부터 보호되도록 밀봉 포장한 것을 말하며, 최근 고용량, 고집적, 초소형화된 반도체 제품에 대한 요구에 부응하기 위해 다양한 반도체 패키지들이 개발되고 있다.A semiconductor package is a package that is electrically sealed so that individual dies made by a wafer process can be used as actual electronic components, and is sealed to protect against external shocks. Various semiconductor packages are being developed to meet this.

이러한 다양한 반도체 패키지 중 도 1과 같이 기판(10) 상면에 칩(미도시)이 실장되고, 기판(10) 하부에 형성된 볼 랜드(11)에 솔더 볼(20)이 배열된 형태의 BGA 패키지가 출현하였다.Among these various semiconductor packages, a BGA package in which chips (not shown) are mounted on the upper surface of the substrate 10 and solder balls 20 are arranged on the ball lands 11 formed below the substrate 10 is shown. Appeared.

이 솔더 볼(20)은 패키지 모서리 부분에 마련되는 리드를 대체한 것으로, 패키지 모서리 부분의 리드 수 증가의 한계를 극복하기 위한 것이다.This solder ball 20 is to replace the lead provided in the package edge portion, to overcome the limitation of the lead number increase in the package edge portion.

그런데, 이와 같은 솔더 볼은 패키지의 몰딩 공정 후에 솔더 볼 마운팅 공정에 의하여 기판 하부에 마련되는데, 몰딩 공정 이후 온도, 습도 등의 환경 변화에 따른 워페이지 발생 시, 솔더 볼을 기판 하부의 볼 랜드에 적절히 형성할 수 없어, 볼 넥 부분의 신뢰성이 떨어지는 등 패키지의 불량을 야기하는 문제점이 있다.However, such a solder ball is provided in the lower part of the substrate by the solder ball mounting process after the molding process of the package, when the warpage occurs due to environmental changes such as temperature and humidity after the molding process, the solder ball to the ball land of the lower substrate There is a problem that it can not be formed properly, causing poor package, such as poor reliability of the ball neck portion.

미설명 부호 12는 배선, 13은 비아 홀, 14는 코어이다.Reference numeral 12 denotes a wiring, 13 a via hole, and 14 a core.

본 발명은 상기의 문제점을 해결하기 위하여 창출된 것으로서, 워페이지 등의 발생에 따른 패키지의 불량을 방지할 수 있는 개선된 솔더 터미널 형성방법을 제공하는 것을 그 목적으로 한다.The present invention has been made to solve the above problems, and an object thereof is to provide an improved solder terminal forming method which can prevent a defect of a package caused by warpage or the like.

상기의 목적을 달성하기 위한 본 발명의 솔더 터미널 형성방법은, 내부에 다수의 배선과, 상기 다수의 배선을 연결하는 비아홀이 형성되고, 일측에 상기 배선이 노출되도록 다수의 볼 랜드가 형성된 기판을 마련하는 단계; 상기 다수의 볼 랜드에 삽입되어 상기 기판 일측면 외부로 돌출되도록 솔더 터미널을 마련하는 단계; 상기 기판 일측면 상에 상기 돌출된 솔더 터미널과 동일한 레벨로 보호 필름을 코 팅하는 단계; 및 상기 기판 타측의 몰딩 후, 상기 보호 필름을 제거하는 단계를 포함한 것이 바람직하다.In the solder terminal forming method of the present invention for achieving the above object, a plurality of wirings, via holes connecting the plurality of wirings are formed therein, a substrate having a plurality of ball land is formed so that the wiring is exposed on one side; Preparing; Preparing a solder terminal inserted into the plurality of ball lands to protrude out of one side of the substrate; Coating a protective film on one side of the substrate to the same level as the protruding solder terminal; And after molding the other side of the substrate, removing the protective film.

여기서, 상기 보호 필름의 제거는 에칭 및 자외선 노광 중 어느 한 방법에 의한 것이 바람직하다.Here, it is preferable to remove the said protective film by either the method of etching and ultraviolet exposure.

이하 첨부된 도면을 참조하면서 본 발명의 바람직한 실시예를 상세히 설명하기로 한다.Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings.

도 2a 내지 도 2d는 본 발명의 일 실시예에 따른 솔더 볼 형성방법을 순차적으로 나타낸 단면도이다.2A to 2D are cross-sectional views sequentially illustrating a solder ball forming method according to an embodiment of the present invention.

도면을 참조하면, 솔더 볼 형성방법은 도 2a와 같이 내부에 다수의 배선(111)이 배치되고, 다수의 배선(111)을 연결하는 비아 홀(112)이 형성되며, 일측에 배선(111)의 일부가 노출되도록 다수의 볼 랜드(113)가 형성된 기판(110)을 마련한다.Referring to the drawing, in the solder ball forming method, as shown in FIG. 2A, a plurality of wirings 111 are disposed inside, via holes 112 connecting the plurality of wirings 111 are formed, and wirings 111 are formed at one side thereof. A substrate 110 having a plurality of ball lands 113 formed thereon is provided to expose a portion of the substrate.

다음으로, 도 2b와 같이 다수의 볼 랜드(113)에 솔더 레지스트를 삽입시켜 솔더 터미널(120)을 마련한다. 이 솔더 터미널(120)은 일부는 볼 랜드(113)에 삽입되며, 나머지 부분은 기판(110) 외부로 돌출된 형태를 가진다.Next, as shown in FIG. 2B, solder resists are inserted into the plurality of ball lands 113 to prepare solder terminals 120. The solder terminal 120 is partially inserted into the ball land 113, and the remaining portion of the solder terminal 120 protrudes out of the substrate 110.

다음으로, 도 2c와 같이 솔더 터미널(120)이 마련된 기판(110)의 면에 보호 필름(130)을 코팅한다. 이 보호 필름(130)은 솔더 터미널(120)의 높이와 동일한 높이의 레벨로 코팅되는데, 이는 후술할 몰딩 공정에서 발생하는 압력을 분산시키기 위함이다.Next, as shown in FIG. 2C, the protective film 130 is coated on the surface of the substrate 110 on which the solder terminal 120 is provided. The protective film 130 is coated at the same level as the height of the solder terminal 120, to disperse the pressure generated in the molding process to be described later.

이와 같은 보호 필름(1230)의 압력 분산 효과는 몰딩 공정에서 발생하는 압 력에 의한 솔더 터미널(120)의 파손이나 형태의 변형을 방지한다.The pressure dispersion effect of the protective film 1230 prevents damage or deformation of the solder terminal 120 due to the pressure generated in the molding process.

마지막으로, 도 2d와 같이 기판(110) 상부를 EMC(140)에 의하여 몰딩한 후, 보호 필름(130)을 제거한다.Finally, as shown in FIG. 2d, the upper portion of the substrate 110 is molded by the EMC 140, and then the protective film 130 is removed.

이때, 보호 필름(130)의 제거는 에칭이나 자외선 노광 등의 방법에 의하여 이루어진다.At this time, the protective film 130 is removed by a method such as etching or ultraviolet exposure.

이와 같은 솔더 터미널 형성방법에 의하면, 몰딩 공정 후에 환경 변화 등에 의하여 워페이지 등이 발생되더라도, 인쇄회로기판에 실장되는 부분인 솔더 터미널이 몰딩 공정보다 먼저 진행되므로, 종래와 같은 솔더 터미널의 부적절한 위치에의 형성을 방지할 수 있고, 볼 랜드 부분과 일자로 형성되므로 종래 볼 넥 부분의 신뢰성 저하의 문제도 해결할 수 있어, 전체적으로 패키지의 불량을 방지할 수 있게 된다.According to such a solder terminal forming method, even if warpage occurs due to environmental changes after the molding process, the solder terminal, which is a part mounted on the printed circuit board, proceeds before the molding process, and thus, the solder terminal may be placed at an inappropriate position. Can be prevented, and since it is formed with the ball land portion and the date, the problem of deterioration of reliability of the conventional ball neck portion can also be solved, and the defect of the package as a whole can be prevented.

상술한 바와 같이 본 발명의 솔더 터미널 형성방법에 의하면, 몰딩 공정 이전에 솔더 터미널을 형성하므로 워페이지 등에 의한 영향을 받지 않아 패키지의 불량 발생을 방지할 수 있는 효과를 제공한다.As described above, according to the solder terminal forming method of the present invention, since the solder terminal is formed before the molding process, the solder terminal is not affected by the warpage, thereby providing an effect of preventing defects in the package.

본 발명은 상기에 설명되고 도면에 예시된 것에 의해 한정되는 것은 아니며, 다음에 기재되는 청구의 범위 내에서 더 많은 변형 및 변용예가 가능한 것임은 물론이다.It is to be understood that the invention is not limited to that described above and illustrated in the drawings, and that more modifications and variations are possible within the scope of the following claims.

Claims (2)

내부에 다수의 배선과, 상기 다수의 배선을 연결하는 비아홀이 형성되고, 일측에 상기 배선이 노출되도록 다수의 볼 랜드가 형성된 기판을 마련하는 단계; Providing a substrate having a plurality of wirings and via holes connecting the plurality of wirings and having a plurality of ball lands formed at one side thereof to expose the wirings; 상기 다수의 볼 랜드에 삽입되어 상기 기판 일측면 외부로 돌출되도록 솔더 터미널을 마련하는 단계; Preparing a solder terminal inserted into the plurality of ball lands to protrude out of one side of the substrate; 상기 기판 일측면 상에 상기 돌출된 솔더 터미널과 동일한 레벨로 보호 필름을 코팅하는 단계; 및 Coating a protective film on one side of the substrate to the same level as the protruding solder terminal; And 상기 기판 타측의 몰딩 후, 상기 보호 필름을 제거하는 단계를 포함한 것을 특징으로 하는 솔더 터미널 형성방법.After molding the other side of the substrate, the solder terminal forming method comprising the step of removing the protective film. 제1항에 있어서,The method of claim 1, 상기 보호 필름의 제거는 에칭 및 자외선 노광 중 어느 한 방법에 의한 것을 특징으로 하는 솔더 터미널 형성방법.And removing the protective film by any one of etching and ultraviolet exposure.
KR1020050106418A 2005-11-08 2005-11-08 Formative method of solder terminal KR100691014B1 (en)

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Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20030012994A (en) * 2001-08-06 2003-02-14 삼성전자주식회사 Tape ball grid array semiconductor chip package having ball land pad which is isolated with adhesive and manufacturing method thereof and multi chip package

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20030012994A (en) * 2001-08-06 2003-02-14 삼성전자주식회사 Tape ball grid array semiconductor chip package having ball land pad which is isolated with adhesive and manufacturing method thereof and multi chip package

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