JPH07176565A - Wiring board and its manufacture - Google Patents

Wiring board and its manufacture

Info

Publication number
JPH07176565A
JPH07176565A JP5344017A JP34401793A JPH07176565A JP H07176565 A JPH07176565 A JP H07176565A JP 5344017 A JP5344017 A JP 5344017A JP 34401793 A JP34401793 A JP 34401793A JP H07176565 A JPH07176565 A JP H07176565A
Authority
JP
Japan
Prior art keywords
wiring board
wiring
protective film
connection
connection pad
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP5344017A
Other languages
Japanese (ja)
Inventor
Michihiko Yamamoto
充彦 山本
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Casio Computer Co Ltd
Original Assignee
Casio Computer Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Casio Computer Co Ltd filed Critical Casio Computer Co Ltd
Priority to JP5344017A priority Critical patent/JPH07176565A/en
Publication of JPH07176565A publication Critical patent/JPH07176565A/en
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/1012Auxiliary members for bump connectors, e.g. spacers
    • H01L2224/10152Auxiliary members for bump connectors, e.g. spacers being formed on an item to be connected not being a semiconductor or solid-state body
    • H01L2224/10175Flow barriers
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30Technical effects
    • H01L2924/38Effects and problems related to the device integration
    • H01L2924/384Bump effects
    • H01L2924/3841Solder bridging
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00Apparatus or processes for manufacturing printed circuits
    • H05K3/0011Working of insulating substrates or insulating layers
    • H05K3/0017Etching of the substrate by chemical or physical means
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00Apparatus or processes for manufacturing printed circuits
    • H05K3/22Secondary treatment of printed circuits
    • H05K3/28Applying non-metallic protective coatings
    • H05K3/281Applying non-metallic protective coatings by means of a preformed insulating foil

Landscapes

  • Wire Bonding (AREA)

Abstract

PURPOSE:To form a protective film which has fine apertures whose diameters are smaller than the diameters of connection pads with a high accuracy and at a low cost in order to prevent solder from penetrating onto wiring patterns from the connection pads on a wiring board when the connection electrodes of an electronic component such as a semiconductor chip are connected to the connection pads on the wiring boards with solder bumps which are formed on the connection electrodes of the electronic components beforehand. CONSTITUTION:A wiring board 41 has wiring patterns having connection pads to which the connection electrodes of an electronic component are connected. A protective film composed of an insulating film 51 such as polyimide film, PET film or PES film is applied to the approximately whole surface of a wiring board 41 which includes the wiring patterns and connection pads which are composed of metal films 43. Then the parts of the protective film composed of the insulating film 51 which are on the connection pads are removed by a laser beam 54 such as an excimer laser to form apertures 55.

Description

【発明の詳細な説明】Detailed Description of the Invention

【0001】[0001]

【産業上の利用分野】本発明は、配線基板に関し、特
に、その配線パターンの電子部品との接続部の構成と、
その接続部の製造方法に関するものである。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a wiring board, and more particularly, to a structure of a connection portion of the wiring pattern with an electronic component,
The present invention relates to a method for manufacturing the connecting portion.

【0002】[0002]

【従来の技術】一般に、配線基板に半導体チップ、例え
ば、LSI(Large ScaleIntegrat
ion:大規模集積回路)を搭載する手法の一つとして
フリップチップボンディングがある。このフリップチッ
プボンディングにおいて、配線基板の配線パターンの接
続パッドに、LSIの接続電極を半田バンプを介して熱
圧着により接続すると、その熱圧着時に一旦溶融した半
田が接続パッドから配線パターン上に流れ出し、さら
に、配線パターン上からその隣の配線パターンに向かっ
て流れ出し、隣合う配線パターン間で短絡が発生してし
まうことがある。このため、配線基板上に半田流れ防止
ダムを形成しておく必要がある。
2. Description of the Related Art Generally, a semiconductor chip such as an LSI (Large Scale Integrator) is mounted on a wiring board.
(ion: large-scale integrated circuit) is one of the methods for mounting flip-chip bonding. In this flip-chip bonding, when the connection electrodes of the LSI are connected to the connection pads of the wiring pattern of the wiring board by thermocompression bonding via solder bumps, the solder once melted during the thermocompression bonding flows out onto the wiring pattern from the connection pads, Furthermore, it may flow out from above the wiring pattern toward the adjacent wiring pattern, and a short circuit may occur between the adjacent wiring patterns. Therefore, it is necessary to form a solder flow prevention dam on the wiring board.

【0003】図6は従来の印刷による半田流れ防止ダム
を形成した配線基板を例示するもので、配線パターン6
2,62,62,…およびその接続パッド63,63,
63,…が形成された配線基板61上に、例えば、スク
リーン印刷等の印刷によりソルダーレジストを用いて、
接続パッド63,63,63,…の配列部に対応した開
口部67を有する半田流れ防止用の保護膜66を形成し
ていた。65は搭載されるLSI71(図7参照)のチ
ップサイズを示している。
FIG. 6 shows an example of a conventional wiring board on which a solder flow prevention dam is formed by printing.
2, 62, 62, ... And their connection pads 63, 63,
On the wiring substrate 61 on which 63, ... Are formed, for example, by using a solder resist by printing such as screen printing,
The protective film 66 for preventing the solder flow having the opening 67 corresponding to the arrangement portion of the connection pads 63, 63, 63, ... Is formed. Reference numeral 65 indicates the chip size of the LSI 71 (see FIG. 7) mounted.

【0004】[0004]

【発明が解決しようとする課題】このような印刷による
保護膜66において、その印刷技術では印刷精度があま
り高くないので、図6に示した通り、搭載するチップサ
イズ65より一回り大きいサイズの開口部67しか印刷
できず、個々の接続パッド63,63,63,…ごとに
対応する等、理想的な半田流れ防止ダムが形成できなか
った。
In the protective film 66 formed by such printing, since the printing precision is not so high in the printing technique, as shown in FIG. 6, an opening having a size slightly larger than the chip size 65 to be mounted is formed. Only the portion 67 can be printed, and it is impossible to form an ideal solder flow prevention dam by corresponding to each individual connection pad 63, 63, 63 ,.

【0005】このため、図7(a)および(b)に示す
ように、配線基板61の配線パターン62の接続パッド
63に、LSI71の接続電極72をこれに予め設けた
半田バンプ75を介して熱圧着すると、溶融した半田7
6が配線パターン62に沿って流れ出てしまう欠点があ
った。なお、理想半田形状を符号75で示し、現状半田
形状を符号76で示しており、現状半田形状76によれ
ば、LSI71の位置が点線形状で示すように下がって
しまっている。
Therefore, as shown in FIGS. 7A and 7B, the connection electrodes 72 of the LSI 71 are connected to the connection pads 63 of the wiring pattern 62 of the wiring substrate 61 via the solder bumps 75 provided in advance. Melted solder 7 when thermocompression bonded
6 has a drawback that it flows out along the wiring pattern 62. The ideal solder shape is indicated by reference numeral 75, and the current solder shape is indicated by reference numeral 76. According to the current solder shape 76, the position of the LSI 71 is lowered as indicated by the dotted line shape.

【0006】ところで、配線基板上に接着剤を介して金
属膜を接着し、フォトレジスト形成、ウェットエッチン
グにより配線パターンを形成する場合、例えば、フォト
レジストの線幅を50μm以下としても、接着剤の存在
により断面がほぼ台形状となって裾の部分を除去できな
いことから、配線パターンの線幅を50μm以下とする
ことができず、50〜60μm程度が限界である。この
場合、接続パッドの直径を100〜140μm程度とす
ると、この接続パッドにLSIの接続電極を半田バンプ
を介して熱圧着により接続すると、配線パターンの線幅
が50〜60μm程度と比較的大きいため、その熱圧着
時に一旦溶融した半田が接続パッドから配線パターン上
に流れ出してしまうのである。
By the way, when a metal film is adhered on a wiring board via an adhesive and a wiring pattern is formed by photoresist formation and wet etching, for example, even if the line width of the photoresist is 50 μm or less, the adhesive Since the cross section becomes almost trapezoidal due to the existence and the hem portion cannot be removed, the line width of the wiring pattern cannot be set to 50 μm or less, and the limit is about 50 to 60 μm. In this case, assuming that the diameter of the connection pad is about 100 to 140 μm, if the connection electrode of the LSI is connected to this connection pad by thermocompression bonding via the solder bump, the line width of the wiring pattern is relatively large, about 50 to 60 μm. During the thermocompression bonding, the solder once melted flows out from the connection pad onto the wiring pattern.

【0007】そこで、接続パッドから配線パターンへの
半田の流出を防止するために、保護膜の開口部の直径を
接続パッドの直径よりもやや小さくし、例えば、60〜
100μm程度として、その開口部によって半田を堰止
めるようにする手法もある。しかし、保護膜の開口部の
直径が60〜100μm程度と微細なパターンである
と、そのような開口部を有する保護膜をスクリーン印刷
により形成することができず、フォトリソグラフィの方
法により形成することになる。その理由は、スクリーン
印刷の場合、開口部の最小直径が200μm程度で位置
精度が±300μm程度以内であるのに対し、フォトリ
ソグラフィの方法の場合には、開口部の最小直径が10
μm程度で位置精度が±20μm程度以内であることに
よる。
Therefore, in order to prevent the solder from flowing out from the connection pad to the wiring pattern, the diameter of the opening of the protective film is made slightly smaller than the diameter of the connection pad.
There is also a method of setting the thickness to about 100 μm and blocking the solder by the opening. However, if the diameter of the opening of the protective film is a fine pattern of about 60 to 100 μm, the protective film having such an opening cannot be formed by screen printing, and the protective film should be formed by the photolithography method. become. The reason is that in the case of screen printing, the minimum diameter of the opening is about 200 μm and the positional accuracy is within ± 300 μm, whereas in the case of the photolithography method, the minimum diameter of the opening is 10 μm.
This is because the position accuracy is within ± 20 μm at about μm.

【0008】しかし、フォトリソグラフィの方法により
微細なパターンの開口部を有する保護膜を形成する場
合、例えば、スクリーン印刷により形成する場合と比較
して、工程数がかなり多く、生産性が悪いばかりでな
く、コストがアップするという問題があった。
However, when a protective film having a fine pattern of openings is formed by a photolithography method, the number of steps is considerably large and productivity is poor as compared with the case where it is formed by screen printing. However, there was a problem that the cost increased.

【0009】そこで、本発明の目的は、半導体チップ等
の電子部品の接続電極に予め設けた半田バンプを介して
熱圧着により接続する際、配線基板上の接続パッドから
配線パターンへの半田を堰止めるため、接続パッドの直
径よりも小さい微細な開口部を有する保護膜を精度良く
かつ低コストにて形成した配線基板およびその製造方法
を提供することにある。
Therefore, an object of the present invention is to dampen solder from a connection pad on a wiring board to a wiring pattern when connecting by thermocompression bonding to a connection electrode of an electronic component such as a semiconductor chip via a solder bump provided in advance. In order to stop the problem, it is an object of the present invention to provide a wiring board in which a protective film having a fine opening smaller than the diameter of the connection pad is formed accurately and at low cost, and a manufacturing method thereof.

【0010】[0010]

【課題を解決するための手段】以上の課題を解決すべく
請求項1記載の発明は、例えば、半導体チップ等の電子
部品の接続電極と接続される接続パッドを有する配線パ
ターンを備えた配線基板であって、この配線基板の前記
配線パターンおよび前記接続パッドを含む面のほぼ全面
に、例えば、ポリイミドまたはPETまたはPES等の
絶縁フィルムによる保護膜を形成して、この保護膜の前
記接続パッドの上面部に、例えば、エキシマレーザー等
のレーザー光により除去された開口部を形成してなる構
成を特徴としている。
In order to solve the above problems, the invention according to claim 1 is, for example, a wiring board having a wiring pattern having a connection pad connected to a connection electrode of an electronic component such as a semiconductor chip. A protective film made of, for example, an insulating film of polyimide, PET, PES, or the like is formed on almost the entire surface of the wiring board including the wiring pattern and the connection pad. The structure is characterized in that an opening removed by a laser beam such as an excimer laser is formed on the upper surface.

【0011】そして、請求項2記載の発明は、例えば、
半導体チップ等の電子部品の接続電極と接続される接続
パッドを有する配線パターンを備えた配線基板の製造方
法において、この配線基板の前記配線パターンおよび前
記接続パッドを含む面のほぼ全面に、例えば、ポリイミ
ドまたはPETまたはPES等の絶縁フィルムによる保
護膜を接合した後、この保護膜の前記接続パッドの上面
部を、例えば、エキシマレーザー等のレーザー光により
除去して開口部を形成する製造方法を特徴としている。
The invention according to claim 2 is, for example,
In a method of manufacturing a wiring board having a wiring pattern having a connection pad connected to a connection electrode of an electronic component such as a semiconductor chip, almost the entire surface including the wiring pattern and the connection pad of the wiring board, for example, A manufacturing method is characterized in that after bonding a protective film made of an insulating film such as polyimide, PET or PES, the upper surface of the connection pad of the protective film is removed by laser light such as excimer laser to form an opening. I am trying.

【0012】[0012]

【作用】本発明によれば、配線基板の配線パターンおよ
び接続パッドを含む面のほぼ全面に接合した絶縁フィル
ムによる保護膜の接続パッドの上面部を、エキシマレー
ザー等のレーザー光により除去して開口部を形成したの
で、保護膜に接続パッドの直径よりも小さい微細な開口
部を精度良くかつ低コストにて形成できる。
According to the present invention, the upper surface of the connection pad of the protective film formed by the insulating film bonded to almost the entire surface of the wiring board including the wiring pattern and the connection pad is removed by laser light such as an excimer laser to form an opening. Since the portion is formed, it is possible to accurately form a fine opening portion smaller than the diameter of the connection pad in the protective film at low cost.

【0013】[0013]

【実施例】以下に、本発明に係る配線基板およびその製
造方法の実施例を図1乃至図5に基づいて説明する。
EXAMPLE An example of a wiring board and a method for manufacturing the same according to the present invention will be described below with reference to FIGS.

【0014】先ず、図1および図2は本発明を適用した
一例としての配線基板1を部分的に示すもので、2は配
線パターン、3は接続パッド、4は保護膜、5は開口部
である。配線基板1は、セラミックやガラスエポキシ等
からなるハードな基板、または、ポリイミドや他の樹脂
からなるフレキシブルな基板の何れであってもよい。
First, FIGS. 1 and 2 partially show a wiring board 1 as an example to which the present invention is applied, in which 2 is a wiring pattern, 3 is a connection pad, 4 is a protective film, and 5 is an opening. is there. The wiring substrate 1 may be either a hard substrate made of ceramic or glass epoxy, or a flexible substrate made of polyimide or another resin.

【0015】図1および図2に示すように、配線基板1
の上面には、図示しない接着剤を介して銅等の金属膜か
らなる配線パターン2と、その端部のほぼ円形状の接続
パッド3が形成されている。さらに、この配線基板1の
上面には、図示しない接着剤を介してポリイミドまたは
PET(ポリエチレンテレフタレート)またはPES
(ポリエーテルサルフォン)等の絶縁フィルムによる保
護膜4が接合されている。
As shown in FIGS. 1 and 2, the wiring board 1
On the upper surface of the wiring pattern 2, a wiring pattern 2 made of a metal film such as copper and a substantially circular connection pad 3 at its end are formed via an adhesive (not shown). Further, polyimide, PET (polyethylene terephthalate), or PES is formed on the upper surface of the wiring board 1 via an adhesive (not shown).
A protective film 4 made of an insulating film such as (polyether sulfone) is bonded.

【0016】そして、この絶縁フィルムによる保護膜4
には、後述するエキシマレーザー等のレーザー光の照射
により、接続パッド3の上面部を除去したほぼ円形状を
なす小径の開口部5が形成されている。ここで、配線パ
ターン2の線幅は50〜60μm程度で、接続パッド3
の直径は100〜140μm程度で、開口部5の直径は
60〜100μm程度である。
The protective film 4 made of this insulating film
A small circular opening 5 having a substantially circular shape is formed by removing the upper surface of the connection pad 3 by irradiation with laser light such as an excimer laser described later. Here, the line width of the wiring pattern 2 is about 50 to 60 μm, and the connection pad 3
Has a diameter of about 100 to 140 μm, and the diameter of the opening 5 is about 60 to 100 μm.

【0017】以上の配線基板1へのLSI11の搭載の
仕方について、図3を参照しつつ説明する。図示のよう
に、LSI11は、その下面に所定数の接続電極12を
有するもので、この接続電極12には予め半田バンプ1
5が備えられている。このLSI11を図示しない熱圧
着ヘッドにより吸着して移動し、その接続電極12に予
め設けた半田バンプ15を、図示しない圧着機ヘッド上
に置かれた配線基板1上の開口部5に位置合わせする。
A method of mounting the LSI 11 on the wiring board 1 will be described with reference to FIG. As shown in the figure, the LSI 11 has a predetermined number of connection electrodes 12 on its lower surface.
5 is provided. The LSI 11 is attracted and moved by a thermocompression bonding head (not shown), and the solder bumps 15 provided in advance on the connection electrodes 12 are aligned with the openings 5 on the wiring board 1 placed on the pressure bonding machine head (not shown). .

【0018】このように、配線基板1の接続パッド3上
に半田バンプ15を介在させてLSI11を熱圧着ヘッ
ドにより加圧・加熱することによって、半田バンプ15
を溶融・固化させる。これにより、配線基板1の接続パ
ッド3上にLSI11下面の接続電極12が半田バンプ
15を介して接続状態となり、しかも、保護膜4の微細
な開口部5の内壁により半田が溶融して流れようとする
のを堰止めて、配線基板1上にLSI11が固定され
る。
As described above, the solder bumps 15 are interposed between the solder bumps 15 on the wiring board 1 and the LSI 11 is pressed and heated by the thermocompression bonding head.
To melt and solidify. As a result, the connection electrodes 12 on the lower surface of the LSI 11 are connected to the connection pads 3 of the wiring board 1 via the solder bumps 15, and moreover, the solder melts and flows by the inner walls of the minute openings 5 of the protective film 4. Then, the LSI 11 is fixed on the wiring board 1 by blocking.

【0019】次に、以上のような配線基板1を製造する
場合について、図4(a)〜(f)および図5(g)〜
(j)を参照しながら説明する。
Next, in the case of manufacturing the wiring board 1 as described above, FIGS. 4 (a) to 4 (f) and 5 (g) to
This will be described with reference to (j).

【0020】先ず、図4(a)は金属膜の接着工程を示
すもので、ハードまたはフレキシブルなどの基板41上
に、接着剤42を用いて銅等の金属膜43を接着する。
ここでは、基板41、接着剤42、金属膜43による3
層構造としたが、金属膜43は、接着ではなくて、スパ
ッタリングや蒸着等の方法で形成して、2層構造として
も構わない。なお、接着剤を用いずに、基板41上に金
属膜43を直接形成した場合、後述するようにして得ら
れる前記配線パターン2の線幅は10〜30μm程度と
することができる。
First, FIG. 4A shows a step of adhering a metal film, in which a metal film 43 of copper or the like is adhered onto a hard or flexible substrate 41 using an adhesive 42.
Here, the substrate 41, the adhesive 42, and the metal film 43
Although the metal film 43 has a layered structure, the metal film 43 may have a two-layered structure formed by a method such as sputtering or vapor deposition instead of bonding. When the metal film 43 is directly formed on the substrate 41 without using an adhesive, the line width of the wiring pattern 2 obtained as described later can be about 10 to 30 μm.

【0021】図4(b)は次のレジスト塗布工程を示す
もので、金属膜43の上面に、回路パターンニングのた
めにレジスト44を塗布する。図4(c)は次の露光工
程を示すもので、所定のパターンを有するガラスマスク
45を用いて、UV光等の光エネルギー46でレジスト
44を露光する。
FIG. 4B shows the next resist coating step. A resist 44 is coated on the upper surface of the metal film 43 for circuit patterning. FIG. 4C shows the next exposure step, in which the resist 44 is exposed with light energy 46 such as UV light using a glass mask 45 having a predetermined pattern.

【0022】図4(d)は次の現像工程を示すもので、
これによりレジスト開口部47,47,47,…を形成
する。図4(e)は次のエッチング工程を示すもので、
これにより金属膜43にパターン間の開口部48を形成
する。図4(f)は次のレジスト剥離工程を示すもの
で、このようにレジスト44,44,44,…を剥離し
て、金属膜43,43,43,…による回路パターンを
形成する。
FIG. 4D shows the next development step.
As a result, resist openings 47, 47, 47, ... Are formed. FIG. 4E shows the next etching step.
As a result, the openings 48 between the patterns are formed in the metal film 43. FIG. 4 (f) shows the next resist stripping step. In this way, the resists 44, 44, 44, ... Are stripped to form a circuit pattern by the metal films 43, 43, 43 ,.

【0023】そして、図5(g)は次のラミネート工程
を示すもので、金属膜43,43,43,…による回路
パターンを形成した基板41の全上面に、エポキシ樹脂
等の接着剤52が片面にラミネートされたポリイミドま
たはPETまたはPES等の絶縁フィルム51を、上下
のローラー53,53によりラミネートする。図5
(h)は次のキュアー工程を示すもので、加熱により接
着剤52を硬化させ、絶縁フィルム51を固定する。
Then, FIG. 5 (g) shows the next laminating step, in which an adhesive 52 such as an epoxy resin is provided on the entire upper surface of the substrate 41 on which the circuit pattern is formed by the metal films 43, 43, 43, .... An insulating film 51 such as polyimide or PET or PES laminated on one surface is laminated by upper and lower rollers 53, 53. Figure 5
(H) shows the next curing step, in which the adhesive 52 is cured by heating and the insulating film 51 is fixed.

【0024】さらに、図5(i)は次のパターンニング
工程を示すもので、低コストで高精度のスポット加工が
簡単に行えるエキシマレーザー等のレーザー光54を局
所的に照射して、絶縁フィルム51の金属膜43による
前記配線パターン2における前記接続パッド3の上面部
のみを局所的に加熱して炭化させて除去し、これにより
開口部55を形成して、パターンニングされた金属膜4
3の表面を露出させる。
Further, FIG. 5 (i) shows the next patterning step, in which the insulating film is locally irradiated with a laser beam 54 such as an excimer laser capable of easily performing high-precision spot processing at low cost. Only the upper surface portion of the connection pad 3 in the wiring pattern 2 by the metal film 43 of 51 is locally heated to be carbonized and removed, thereby forming the opening 55, and the patterned metal film 4 is formed.
The surface of 3 is exposed.

【0025】ここで、レーザー光54は、X,Y方向に
スキャンニングし、次々に前記接続パッド3上の絶縁フ
ィルム51を炭化させて除去していくもので、その具体
的な除去は、真空引き、洗浄、エア吹き出し等の任意の
手段により行う。
Here, the laser beam 54 is scanned in the X and Y directions to carbonize and remove the insulating film 51 on the connection pad 3 one after another. The specific removal is a vacuum. It is carried out by any means such as pulling, washing, blowing air.

【0026】そして、図5(j)は最後のアッシング工
程を示すもので、開口部55に露出された金属膜43の
表面に残ったスカム(有機物残さ)を除去するため、酸
素プラズマによりアッシングを行う。
FIG. 5 (j) shows the final ashing step. In order to remove scum (organic residue) remaining on the surface of the metal film 43 exposed in the opening 55, ashing is performed by oxygen plasma. To do.

【0027】このようにして、金属膜43による線幅が
50〜60μm程度(もしくは10〜30μm程度)の
配線パターン2および直径が100〜140μm程度の
接続パッド3を形成するとともに、絶縁フィルム51に
よる保護膜5にレーザー光54により開けた開口部55
による直径が60〜100μm程度の開口部5を形成す
る。
In this way, the wiring pattern 2 having a line width of about 50 to 60 μm (or about 10 to 30 μm) and the connection pad 3 having a diameter of about 100 to 140 μm are formed by the metal film 43, and the insulating film 51 is used. An opening 55 opened by the laser beam 54 in the protective film 5
To form an opening 5 having a diameter of about 60 to 100 μm.

【0028】以上の通り、金属膜43による回路パター
ンを形成した基板41の全上面に、絶縁フィルム51を
ラミネートし、接続パッドの上面部をエキシマレーザー
によるレーザー光54を用いて除去したことにより、フ
レキシブル基板においてでも超ファインでも理想的な半
田流れ防止ダムとしての開口部55の形成が低温でかつ
低コストにて可能である。また、回路パターン全部を絶
縁フィルム51で完全にコートしたため、パターン間絶
縁性を向上させ、且つパターンの機械的強度を飛躍的に
向上させることができる。
As described above, the insulating film 51 is laminated on the entire upper surface of the substrate 41 on which the circuit pattern is formed by the metal film 43, and the upper surface portion of the connection pad is removed by using the laser beam 54 by the excimer laser. The formation of the opening 55 as an ideal solder flow prevention dam is possible at low temperature and at low cost even in a flexible substrate or ultrafine. Further, since the entire circuit pattern is completely coated with the insulating film 51, the inter-pattern insulating property can be improved and the mechanical strength of the pattern can be dramatically improved.

【0029】なお、以上の実施例においては、配線基板
へのLSIの搭載としたが、本発明はこれに限定される
ものではなく、他の半導体チップ等の電子部品の配線基
板への搭載であってもよい。また、配線パターンの形状
や本発明を適用する用途等も任意であり、その他、具体
的な細部構造等についても適宜に変更可能であることは
勿論である。
Although the LSI is mounted on the wiring board in the above embodiments, the present invention is not limited to this, and electronic components such as other semiconductor chips can be mounted on the wiring board. It may be. Further, the shape of the wiring pattern, the application of the present invention, and the like are arbitrary, and it is needless to say that the specific detailed structure and the like can be appropriately changed.

【0030】[0030]

【発明の効果】以上のように、本発明に係る配線基板お
よびその製造方法によれば、配線パターンおよび接続パ
ッドを含む面のほぼ全面に接合した絶縁フィルムによる
保護膜の接続パッドの上面部を、エキシマレーザー等の
レーザー光により除去することによって、接続パッドの
直径よりも小さい微細な開口部を精度良くかつ低コスト
にて形成することができる。従って、半導体チップ等の
電子部品の接続電極に予め設けた半田バンプを介して熱
圧着により接続する際、配線基板上の接続パッドにその
微細な開口部により半田を堰止めて、確実な接続を行う
ことができる。
As described above, according to the wiring board and the method of manufacturing the same of the present invention, the upper surface of the connection pad of the protective film formed of the insulating film bonded to almost the entire surface including the wiring pattern and the connection pad is formed. By removing with a laser beam such as an excimer laser, a fine opening smaller than the diameter of the connection pad can be formed accurately and at low cost. Therefore, when connecting by thermocompression bonding to a connection electrode of an electronic component such as a semiconductor chip through a solder bump provided in advance, the solder is blocked by the fine opening in the connection pad on the wiring board to ensure a reliable connection. It can be carried out.

【図面の簡単な説明】[Brief description of drawings]

【図1】本発明を適用した一例としての配線基板を部分
的に示す平面図である。
FIG. 1 is a plan view partially showing a wiring board as an example to which the present invention is applied.

【図2】図1の配線基板の各部断面を示すもので、
(a)は図1の矢印A−A線に沿った断面図、(b)は
同じく図1の矢印B−B線に沿った断面図である。
2 is a cross-sectional view of each part of the wiring board of FIG.
1A is a sectional view taken along the line AA of FIG. 1, and FIG. 1B is a sectional view taken along the line BB of FIG.

【図3】本発明による図1の配線基板へのLSIの搭載
例を示す破断側面図である。
FIG. 3 is a cutaway side view showing an example of mounting an LSI on the wiring board of FIG. 1 according to the present invention.

【図4】本発明を適用する配線基板の製造工程を示すも
ので、(a)は金属膜の接着工程を示す断面図、(b)
はレジスト塗布工程を示す断面図、(c)は露光工程を
示す断面図、(d)は現像工程を示す断面図、(e)は
エッチング工程を示す断面図、(f)はレジスト剥離工
程を示す断面図である。
4A and 4B show a manufacturing process of a wiring board to which the present invention is applied, wherein FIG. 4A is a sectional view showing a bonding process of a metal film;
Is a sectional view showing a resist coating step, (c) is a sectional view showing an exposure step, (d) is a sectional view showing a developing step, (e) is a sectional view showing an etching step, and (f) is a resist stripping step. It is sectional drawing shown.

【図5】図4の製造工程に続く本発明による配線基板の
製造工程を示すもので、(g)はラミネート工程を示す
断面図、(h)はキュアー工程を示す断面図、(i)は
パターンニング工程を示す断面図、(j)はアッシング
工程を示す断面図である。
5A to 5C show a manufacturing process of a wiring board according to the present invention subsequent to the manufacturing process of FIG. 4, in which (g) is a sectional view showing a laminating process, (h) is a sectional view showing a curing process, and (i) is a sectional view. FIG. 3J is a sectional view showing a patterning step, and FIG. 3J is a sectional view showing an ashing step.

【図6】従来の印刷による半田流れ防止ダムを形成した
配線基板を例示する概略平面図である。
FIG. 6 is a schematic plan view illustrating a wiring board having a conventional solder flow prevention dam formed by printing.

【図7】図6の配線基板へのLSIの搭載例を示すもの
で、(a)は破断側面図、(b)はLSIを透視状態で
示した平面図である。
7A and 7B show an example of mounting the LSI on the wiring board of FIG. 6, where FIG. 7A is a cutaway side view and FIG. 7B is a plan view showing the LSI in a see-through state.

【符号の説明】[Explanation of symbols]

1 配線基板 2 配線パターン 3 接続パッド 4 保護膜 5 開口部 11 LSI 12 接続電極 15 半田バンプ 41 基板 42 接着剤 43 金属膜 44 レジスト 45 ガラスマスク 46 光エネルギー 47,48 開口部 51 絶縁フィルム 52 接着剤 53 ローラー 54 レーザー光 55 開口部 1 Wiring Board 2 Wiring Pattern 3 Connection Pad 4 Protective Film 5 Opening 11 LSI 12 Connection Electrode 15 Solder Bump 41 Substrate 42 Adhesive 43 Metal Film 44 Resist 45 Glass Mask 46 Light Energy 47, 48 Opening 51 Insulating Film 52 Adhesive 53 roller 54 laser light 55 opening

Claims (2)

【特許請求の範囲】[Claims] 【請求項1】 電子部品の接続電極と接続される接続パ
ッドを有する配線パターンを備えた配線基板であって、 この配線基板の前記配線パターンおよび前記接続パッド
を含む面のほぼ全面に絶縁フィルムによる保護膜を形成
して、 この保護膜の前記接続パッドの上面部にレーザー光によ
り除去された開口部を形成したことを特徴とする配線基
板。
1. A wiring board having a wiring pattern having a connection pad connected to a connection electrode of an electronic component, wherein an insulating film is formed on substantially the entire surface of the wiring board including the wiring pattern and the connection pad. A wiring board, wherein a protective film is formed, and an opening removed by laser light is formed on an upper surface of the connection pad of the protective film.
【請求項2】 電子部品の接続電極と接続される接続パ
ッドを有する配線パターンを備えた配線基板の製造方法
において、 この配線基板の前記配線パターンおよび前記接続パッド
を含む面のほぼ全面に絶縁フィルムによる保護膜を接合
した後、 この保護膜の前記接続パッドの上面部をレーザー光によ
り除去して開口部を形成することを特徴とする配線基板
の製造方法。
2. A method for manufacturing a wiring board having a wiring pattern having a connection pad connected to a connection electrode of an electronic component, wherein an insulating film is formed on substantially the entire surface of the wiring board including the wiring pattern and the connection pad. The method for manufacturing a wiring board according to claim 1, wherein after the protective film is bonded, the upper surface of the connection pad of the protective film is removed by laser light to form an opening.
JP5344017A 1993-12-16 1993-12-16 Wiring board and its manufacture Pending JPH07176565A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP5344017A JPH07176565A (en) 1993-12-16 1993-12-16 Wiring board and its manufacture

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP5344017A JPH07176565A (en) 1993-12-16 1993-12-16 Wiring board and its manufacture

Publications (1)

Publication Number Publication Date
JPH07176565A true JPH07176565A (en) 1995-07-14

Family

ID=18366018

Family Applications (1)

Application Number Title Priority Date Filing Date
JP5344017A Pending JPH07176565A (en) 1993-12-16 1993-12-16 Wiring board and its manufacture

Country Status (1)

Country Link
JP (1) JPH07176565A (en)

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6677970B1 (en) * 1998-02-20 2004-01-13 Sanyo Electric Co., Ltd. Light-emitting diode array and optical print head
WO2004032321A1 (en) * 2002-10-04 2004-04-15 Toyo Communication Equipment Co., Ltd. Production method for surface-mounted saw device
EP1427032A3 (en) * 2002-12-06 2006-01-11 Murata Manufacturing Co., Ltd. Method of producing a piezoelectric part and piezoelectric part
KR100871384B1 (en) * 2007-06-26 2008-12-02 주식회사 하이닉스반도체 Method of manufacturing semiconductor package
CN115038255A (en) * 2022-06-27 2022-09-09 西安易朴通讯技术有限公司 Windowing method for covering film of flexible circuit board

Cited By (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6677970B1 (en) * 1998-02-20 2004-01-13 Sanyo Electric Co., Ltd. Light-emitting diode array and optical print head
WO2004032321A1 (en) * 2002-10-04 2004-04-15 Toyo Communication Equipment Co., Ltd. Production method for surface-mounted saw device
US7183124B2 (en) 2002-10-04 2007-02-27 Toyo Communication Equipment Co., Ltd. Surface mount saw device manufacturing method
EP1427032A3 (en) * 2002-12-06 2006-01-11 Murata Manufacturing Co., Ltd. Method of producing a piezoelectric part and piezoelectric part
US7261792B2 (en) * 2002-12-06 2007-08-28 Murata Manufacturing Co., Ltd. Method of producing piezoelectric component and piezoelectric component
KR100871384B1 (en) * 2007-06-26 2008-12-02 주식회사 하이닉스반도체 Method of manufacturing semiconductor package
CN115038255A (en) * 2022-06-27 2022-09-09 西安易朴通讯技术有限公司 Windowing method for covering film of flexible circuit board
CN115038255B (en) * 2022-06-27 2024-02-27 西安易朴通讯技术有限公司 Windowing method for cover film of flexible circuit board

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