TW241385B - Etching method for DRAM peripheral circuit - Google Patents

Abstract

A method for confining the dielectric layer thickness one the peripheral circuit of DRAM IC and etching opening with proper aspect ratio through the dielectric overlaying area to make the peripheral contact the semiconductor wafer electrically, includes: 1. supplying DRAM IC electric contact with above peripheral circuit in and above the wafer; 2. forming the first conductive polysilicon layer on the DRAM IC, and patterning the layer, then leaving it on the peripheral circuit; 3. forming the first dielectric layer on the patterned polysilicon layer; 4. forming the second conductive layer on the first dielectric layer, and patterning the second conductive layer, then leaving it outside the peripheral circuit; 5. masking and etching the first dielectric layer and the first polysilicon below it to remove the first dielectric layer and the first polysilicon of all peripheral circuits; 6. forming the second dielectric on the exposed second conductive layer, the first dielectric layer and semiconductor wafer , and etching opening with proper aspect ratio through the second dielectric layer.