JPH02170436A - Manufacture of semiconductor device - Google Patents
Manufacture of semiconductor deviceInfo
- Publication number
- JPH02170436A JPH02170436A JP63325187A JP32518788A JPH02170436A JP H02170436 A JPH02170436 A JP H02170436A JP 63325187 A JP63325187 A JP 63325187A JP 32518788 A JP32518788 A JP 32518788A JP H02170436 A JPH02170436 A JP H02170436A
- Authority
- JP
- Japan
- Prior art keywords
- film
- diffusion region
- type
- implanted
- ions
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims description 13
- 238000004519 manufacturing process Methods 0.000 title claims description 8
- 238000009792 diffusion process Methods 0.000 claims abstract description 38
- 239000000758 substrate Substances 0.000 claims abstract description 14
- 239000012535 impurity Substances 0.000 claims abstract description 8
- 239000002184 metal Substances 0.000 claims abstract description 7
- 229910052751 metal Inorganic materials 0.000 claims abstract description 7
- 238000000034 method Methods 0.000 claims abstract description 7
- 229910052710 silicon Inorganic materials 0.000 claims description 9
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 8
- 239000010703 silicon Substances 0.000 claims description 8
- 238000002844 melting Methods 0.000 claims description 6
- 230000008018 melting Effects 0.000 claims description 6
- 238000000151 deposition Methods 0.000 claims description 3
- 238000005530 etching Methods 0.000 claims description 3
- 229910021332 silicide Inorganic materials 0.000 claims description 2
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 claims description 2
- 150000002500 ions Chemical class 0.000 abstract description 15
- 229920002120 photoresistant polymer Polymers 0.000 abstract description 10
- 239000010936 titanium Substances 0.000 abstract description 9
- 229910021341 titanium silicide Inorganic materials 0.000 abstract description 7
- 230000015572 biosynthetic process Effects 0.000 abstract description 6
- 230000015556 catabolic process Effects 0.000 abstract description 3
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 abstract description 2
- 229910021420 polycrystalline silicon Inorganic materials 0.000 abstract description 2
- 229910052814 silicon oxide Inorganic materials 0.000 abstract description 2
- 229910018125 Al-Si Inorganic materials 0.000 abstract 1
- 229910018520 Al—Si Inorganic materials 0.000 abstract 1
- 238000010438 heat treatment Methods 0.000 description 5
- 239000005380 borophosphosilicate glass Substances 0.000 description 3
- 230000000694 effects Effects 0.000 description 2
- 230000010354 integration Effects 0.000 description 2
- 238000005468 ion implantation Methods 0.000 description 2
- 101150034533 ATIC gene Proteins 0.000 description 1
- VHUUQVKOLVNVRT-UHFFFAOYSA-N Ammonium hydroxide Chemical compound [NH4+].[OH-] VHUUQVKOLVNVRT-UHFFFAOYSA-N 0.000 description 1
- 101100162197 Aspergillus parasiticus (strain ATCC 56775 / NRRL 5862 / SRRC 143 / SU-1) aflA gene Proteins 0.000 description 1
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 description 1
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 1
- 229910000676 Si alloy Inorganic materials 0.000 description 1
- 230000003213 activating effect Effects 0.000 description 1
- 229910045601 alloy Inorganic materials 0.000 description 1
- 239000000956 alloy Substances 0.000 description 1
- 235000011114 ammonium hydroxide Nutrition 0.000 description 1
- 229910052796 boron Inorganic materials 0.000 description 1
- 238000006243 chemical reaction Methods 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 230000003647 oxidation Effects 0.000 description 1
- 238000007254 oxidation reaction Methods 0.000 description 1
- 238000005192 partition Methods 0.000 description 1
- 229910052698 phosphorus Inorganic materials 0.000 description 1
- 239000011574 phosphorus Substances 0.000 description 1
- 238000000206 photolithography Methods 0.000 description 1
- 239000003870 refractory metal Substances 0.000 description 1
- 238000004544 sputter deposition Methods 0.000 description 1
- 229910052719 titanium Inorganic materials 0.000 description 1
Landscapes
- Electrodes Of Semiconductors (AREA)
- Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分骨〕
本発明は半導体装置の製造方法に関し、特にＭＯＳトラ
ンジスタを有する半導体装置の製造方法に関する。DETAILED DESCRIPTION OF THE INVENTION [Industrial Application] The present invention relates to a method for manufacturing a semiconductor device, and particularly to a method for manufacturing a semiconductor device having a MOS transistor.
従来のＭ ＯＳ ＋−ランジスタを有する半導体装置の
製造方法は、高集積化を向上させるために、ソース・ド
レイン領域とコンタクト用開口部との写真蝕刻時の目合
せ余裕を縮小し、その結果、目合わせ誤差によりソース
・ドレイン領域から一部はみ出して形成された開口部の
領域にそれぞれのソース・トレイン領域と同一導電型の
不純物をそれぞれの開口部にイオン注入してソース・ド
レイン領域に隣接する部分に補助拡散領域を設は熱処理
により活性化を行った後、ＡＩ又はＡｆ−３ｉ合金で開
口部のソース・ドレイン領域と接続する配線を選択的に
形成していた。In the conventional manufacturing method of a semiconductor device having a MOS +- transistor, in order to improve high integration, the alignment margin during photolithography between the source/drain region and the contact opening is reduced, and as a result, Impurity ions of the same conductivity type as the respective source/train regions are implanted into the respective openings, which are formed partially protruding from the source/drain regions due to alignment errors, to form adjacent regions to the source/drain regions. After providing an auxiliary diffusion region in a portion and activating it by heat treatment, wiring connected to the source/drain region of the opening was selectively formed using AI or Af-3i alloy.
上述した従来の半導体装置の製造方法は、次の２点が問
題となっていた。The conventional semiconductor device manufacturing method described above has the following two problems.
（Ａ）イオン注入法により開口部を通してｎ型又はｐ型
不純物を導入する際、加速されたイオンにより基板表面
がチャージアップし、薄いゲート酸化膜が絶縁破壊され
る場合がしばしば発生する。(A) When n-type or p-type impurities are introduced through an opening by ion implantation, the surface of the substrate is charged up by the accelerated ions, which often causes dielectric breakdown of a thin gate oxide film.
（Ｂ）Ａ、ｆｆ又はＡＪ−Ｓｉ合金による配線とｎ型又
はｐ型拡散領域からなるソース・ドレイン領域が直接開
口部において接触する場合のコンタクト抵抗が大きい。(B) Contact resistance is large when wiring made of A, ff or AJ-Si alloy and source/drain regions made of n-type or p-type diffusion regions are in direct contact at the opening.
本発明の半導体装置の製造方法は、−導電型シリコン基
板の一主面に選択的に逆導電型の拡散領域を設ける工程
と、前記拡散領域を含む表面に設けた絶縁膜を選択的に
エツチングして前記拡散領域及び前記拡散領域に隣接す
る前記シリコン基板の表面を含む開口部を設ける工程と
、前記開口部を含む表面に高融点金属膜を堆積する工程
と、熱処理により前記開口部の前記拡散領域及び前記シ
リコン基板の表面に高融点金属硅化物膜を形成する工程
と、逆導電型不純物を選択的にイオン注入して前記開口
部の前記シリコン基板の表面に前記拡’ａｆｌＡ域と接
続する逆導電型の補助拡散領域を形成する工程とを含ん
で構成される。The method for manufacturing a semiconductor device of the present invention includes: - selectively providing a diffusion region of an opposite conductivity type on one main surface of a conductivity type silicon substrate; and selectively etching an insulating film provided on a surface including the diffusion region; forming an opening including the diffusion region and the surface of the silicon substrate adjacent to the diffusion region; depositing a high melting point metal film on the surface including the opening; forming a high melting point metal silicide film on the diffusion region and the surface of the silicon substrate, and selectively ion-implanting opposite conductivity type impurities to connect the surface of the silicon substrate in the opening with the expanded aflA region; forming an auxiliary diffusion region of opposite conductivity type.
次に、本発明の実施例について図面を参照して説明する
。Next, embodiments of the present invention will be described with reference to the drawings.
第１図（ａ）〜（ｄ）は本発明の第１の実施例を説明す
るための工程順に示した半導体チップの断面図である。FIGS. 1(a) to 1(d) are cross-sectional views of a semiconductor chip shown in order of steps for explaining a first embodiment of the present invention.
まず、第１図（ａ）に示すように、ｐ型シリコン基板１
の主面に選択的にｎ型ウェル２を設け、ｎ型ウェル２の
表面及びｎ型ウェル２以外の領域の表面のそれぞれに選
択的にフィールド酸化膜３を設けて素子形成領域を区画
する０次に、前記素子形成領域の表面にゲート酸化ｓ４
を設け、ゲート酸化ｆｌ１４を含む表面に多結晶シリコ
ン膜を堆積してこれを選択的にエツチングしゲート電極
５を形成する。次に、ゲート電極５及びフィールド酸化
膜３をマスクとして自己整合的に不純物をイオン注入し
、ｎ型ウェル２の前記素子形成領域にはｐ＋型拡散領域
６を形成し、ｎ型ウェル２以外の前記素子形成領域には
ｎ＋型拡散領域７を形成して、それぞれソース・ドレイ
ン領域を設けｎチャネルトランジスタ及びｎチャネルト
ランジスタを形成する。次に、ゲート電極５を含む表面
にリン及びホウ素を含む酸化シリコン膜（以下ＢＰＳＧ
膜と記す）８を堆積し、ｐ＋型拡散領域６及びｎ“型拡
散領域７の上のＢＰＳＧ膜８及びゲート酸化膜４を選択
的に順次エツチングしてコンタクト用の開口部９を設け
る。ここで、開口部９は高集積度化のために位置合わせ
余裕を小さくしているのでｐ＋型拡散領域６又はｎ１型
拡散領域７より逸脱してｎ型ウェル２又はｐ型Ｓｉ基板
１の領域の表面まではみ出して形成される。First, as shown in FIG. 1(a), a p-type silicon substrate 1
An n-type well 2 is selectively provided on the main surface of the n-type well 2, and a field oxide film 3 is selectively provided on each of the surface of the n-type well 2 and the surface of a region other than the n-type well 2 to partition an element formation region. Next, gate oxidation s4 is applied to the surface of the element formation region.
A polycrystalline silicon film is deposited on the surface including the gate oxide fl14 and selectively etched to form the gate electrode 5. Next, impurity ions are implanted in a self-aligned manner using the gate electrode 5 and field oxide film 3 as masks, and a p+ type diffusion region 6 is formed in the element formation region of the n-type well 2. An n+ type diffusion region 7 is formed in the element formation region, and source and drain regions are provided respectively to form an n-channel transistor and an n-channel transistor. Next, a silicon oxide film containing phosphorus and boron (hereinafter referred to as BPSG) is formed on the surface including the gate electrode 5.
A contact opening 9 is formed by selectively and sequentially etching the BPSG film 8 and the gate oxide film 4 on the p+ type diffusion region 6 and the n" type diffusion region 7. Since the opening 9 has a small alignment margin for high integration, it deviates from the p+ type diffusion region 6 or the n1 type diffusion region 7 and forms the area of the n-type well 2 or the p-type Si substrate 1. It is formed by protruding to the surface.
次に、第１図（ｂ）に示すように、開口部９を含む表面
にスパッタ法によりＴｉ膜１０を堆積し、ランプ加熱法
により開口部９のＳｉとＴｉを反応させて硅化チタン膜
１１を形成する。Next, as shown in FIG. 1(b), a Ti film 10 is deposited on the surface including the opening 9 by sputtering, and the Si in the opening 9 is reacted with Ti by a lamp heating method to form a titanium silicide film 11. form.
次に、第１図（ｃ）に示すように、ｎ型ウェル２の素子
形成領域に形成したＰチャネルトランジスタの領域上に
選択的にホトレジスト膜１２を設ける。次に、ホトレジ
スト膜１２及びＢ Ｐ Ｓ Ｇ Ｊｌ’１８をマスクと
してＡｓイオン１３をイオン注入し、硅化チタン膜１１
の下のｐ型Ｓｔ基板１の表面に補助ｎ＋型拡散領域１４
を形成する。Next, as shown in FIG. 1(c), a photoresist film 12 is selectively provided on the region of the P channel transistor formed in the element formation region of the n-type well 2. Next, As ions 13 are implanted using the photoresist film 12 and the B P S G Jl' 18 as a mask, and the titanium silicide film 11 is
Auxiliary n+ type diffusion region 14 on the surface of p type St substrate 1 under
form.
次に、第１図（ｄ）に示すように、ホトレジスト膜２を
除去し、ｎチャネルトランジスタの領域上に選択的にホ
トレジスト膜１５を設け、ホトレジスト膜１５及びＢＰ
ＳＧ膜８をマスクとしてＢイオン１６をイオン注入し、
硅化チタン膜１１の下のｎ型ウェルの表面に補助ｐ＋型
拡散領域１７を形成する。ここで、Ｔｉ膜１０のために
前述した２回のイオン注入時に局所的なチャージアップ
を防ぐことができ、薄いゲート酸化Ｍ４の絶縁破壊を防
止することができる。Next, as shown in FIG. 1(d), the photoresist film 2 is removed, a photoresist film 15 is selectively provided on the n-channel transistor region, and the photoresist film 15 and BP
Using the SG film 8 as a mask, B ions 16 are implanted,
An auxiliary p + -type diffusion region 17 is formed on the surface of the n-type well under the titanium silicide film 11 . Here, local charge-up can be prevented during the above-described two ion implantations for the Ti film 10, and dielectric breakdown of the thin gate oxide M4 can be prevented.
次に、第１図（ｅ）に示すように、ＮＨ４ＯＨ十Ｈ２ｏ
２＋Ｈ２０溶液中で未反応のＴｉ膜１０を除去した後、
９００℃の熱処理を行い補助ｎ＋型拡散領域１４及び補
助ｐ＋型拡散領域１７の活性化を行う。Next, as shown in FIG. 1(e), NH4OH+H2o
After removing the unreacted Ti film 10 in the 2+H20 solution,
Heat treatment at 900° C. is performed to activate the auxiliary n+ type diffusion region 14 and the auxiliary p+ type diffusion region 17.
次に、第１図に（ｆ）に示すように、開口部９を含む表
面にＡ、＆−３ｉ層を堆積し、これを選択的にエツチン
グしてρ“型拡散領域６及びｎ＋型拡散領域７のそれぞ
れと電気的に接続する配線１８をそれぞれ形成して半導
体装置を構成する。Next, as shown in FIG. 1(f), an A, &-3i layer is deposited on the surface including the opening 9, and this is selectively etched to form the ρ" type diffusion region 6 and the n+ type diffusion region. Wirings 18 electrically connected to each region 7 are formed to constitute a semiconductor device.
なお、ここでＴｉ膜１０の代りにＣｏやＮｉ等の高融点
金属を使用しても良い。Note that here, instead of the Ti film 10, a high melting point metal such as Co or Ni may be used.
第２図（ａ）、（ｂ）は本発明の第２の実施例を説明す
るための工程順に示した半導体チップの断面図である。FIGS. 2(a) and 2(b) are cross-sectional views of a semiconductor chip shown in order of steps for explaining a second embodiment of the present invention.
第２図（ａ）に示すように、第１図（ａ）（ｂ）で説明
した第１の実施例と同じ工程によりＴｉ膜１０までを形
成し、熱処理により開口部９のＳｉとＴｉを反応させて
硅化チタン膜１１を形成する。次に、全面にＢイオンを
イオン注入して硅化チタン膜１１及び開口部９のｎ型ウ
ェル２及びＰ型Ｓｔ基板１の表面にｐ型不純物を導入す
る。As shown in FIG. 2(a), up to the Ti film 10 is formed by the same steps as in the first embodiment explained in FIGS. 1(a) and (b), and the Si and Ti in the opening 9 are removed by heat treatment. A titanium silicide film 11 is formed by the reaction. Next, B ions are implanted into the entire surface to introduce p-type impurities into the titanium silicide film 11, the n-type well 2 in the opening 9, and the surfaces of the P-type St substrate 1.
次に、第２図（ｂ）に示すように、ｎチャネルトランジ
スタの領域上に選択的にホトレジスト膜１２を設けてＡ
ｓイオンをイオン注入し、ｎチャネルトランジスタの領
域の開口部９のｐ型不純物をうち消して補助ｎ＋型拡散
領域１４を形成する。以後、第１の実施例と同様に熱処
理により補助ｎ＋型拡散領域１４及び補助ｐ＋型拡散領
域１７の活性化を行い、ＣＭＯＳトランジスタを形成す
る。第２の実施例では、Ｂイオンをマスクを用いずに導
入することができるなめ、第１の実施例に比べて工程が
簡略化できる効果がある。Next, as shown in FIG. 2(b), a photoresist film 12 is selectively provided on the region of the n-channel transistor.
S ions are implanted to cancel out the p-type impurity in the opening 9 in the n-channel transistor region to form an auxiliary n + -type diffusion region 14 . Thereafter, the auxiliary n+ type diffusion region 14 and the auxiliary p+ type diffusion region 17 are activated by heat treatment in the same manner as in the first embodiment, thereby forming a CMOS transistor. In the second embodiment, since B ions can be introduced without using a mask, the process can be simplified compared to the first embodiment.
以上説明したように本発明は、高融点金属膜か全面に成
長された状態で開口部へのイオン注入を行うことができ
るので、この工程でのチャージアップによるゲート酸化
膜破壊等のＥＳＤ（ＥＪｅｃｔｒｏ −Ｓｔ、ａｔｉｃ
Ｄａｍａｇｅ ）をほぼ完全に防止でき、歩留の高い
信頼性の高い半導体装置を製造できる。また、本発明は
、コンタクト用開口部に、高融点金属硅化物膜を選択的
に形成することにより、Ａ！２又はＡｆｆｌ−３ｉ配線
とソース、ドレイン領域を構成する拡散領域との間のコ
ンタクト抵抗を低減でき、高速動作の可能な半導体装置
の製造方法を実現できる効果がある。As explained above, in the present invention, ions can be implanted into the opening with the refractory metal film grown on the entire surface, so that ESD (Ejectro -St, atic
Damage) can be almost completely prevented, and highly reliable semiconductor devices with high yields can be manufactured. Furthermore, the present invention provides A! This has the effect that the contact resistance between the 2 or Affl-3i wiring and the diffusion regions forming the source and drain regions can be reduced, and a method of manufacturing a semiconductor device capable of high-speed operation can be realized.
第１図（ａ）〜（ｆ）及び第２図（ａ）、 （ｂ）は
、本発明の第１及び第２の実施例を説明するための工程
順に示した半導体チップの断面図である。
１・・・ｐ型Ｓｉ基板、２・・・ｎ型ウェル、３・・・
フィールド酸化膜、４・・・ゲート酸化膜、５・・・ゲ
ート電極、６・・・ｐ＋型拡散領域、７・・・ｎ＋型拡
散領域、８・・・ＢＰＳＧ膜、９・・・開口部、１０・
・・Ｔｉ膜、硅化チタン膜、１２・・・ホトレジスト膜
、１３・・・Ａｓイオン、１４・・・補助ｎ＋型拡散領
域、１５・・・ホトレジスト膜、１６・・・Ｂイオン、
１７・・・補助ｐ＋型拡散領域、１８・・・配線。FIGS. 1(a) to (f) and FIGS. 2(a) and 2(b) are cross-sectional views of a semiconductor chip shown in the order of steps for explaining the first and second embodiments of the present invention. . 1...p-type Si substrate, 2...n-type well, 3...
Field oxide film, 4... Gate oxide film, 5... Gate electrode, 6... P+ type diffusion region, 7... N+ type diffusion region, 8... BPSG film, 9... Opening part , 10・
...Ti film, titanium silicide film, 12...photoresist film, 13...As ion, 14...auxiliary n+ type diffusion region, 15...photoresist film, 16...B ion,
17... Auxiliary p+ type diffusion region, 18... Wiring.
Claims (1)
散領域を設ける工程と、前記拡散領域を含む表面に設け
た絶縁膜を選択的にエッチングして前記拡散領域及び前
記拡散領域に隣接する前記シリコン基板の表面を含む開
口部を設ける工程と、前記開口部を含む表面に高融点金
属膜を堆積する工程と、熱処理により前記開口部の前記
拡散領域及び前記シリコン基板の表面に高融点金属硅化
物膜を形成する工程と、逆導電型不純物を選択的にイオ
ン注入して前記開口部の前記シリコン基板の表面に前記
拡散領域と接続する逆導電型の補助拡散領域を形成する
工程とを含むことを特徴とする半導体装置の製造方法。A step of selectively providing a diffusion region of an opposite conductivity type on one main surface of a silicon substrate of one conductivity type, and selectively etching an insulating film provided on a surface including the diffusion region to form the diffusion region and the diffusion region. a step of providing an opening including a surface of the adjacent silicon substrate; a step of depositing a high melting point metal film on the surface including the opening; and a step of depositing a high melting point metal film on the surface including the opening, a step of forming a melting point metal silicide film; and a step of selectively ion-implanting impurities of opposite conductivity type to form an auxiliary diffusion region of opposite conductivity type connected to the diffusion region on the surface of the silicon substrate in the opening. A method for manufacturing a semiconductor device, comprising:
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP63325187A JPH02170436A (en) | 1988-12-22 | 1988-12-22 | Manufacture of semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP63325187A JPH02170436A (en) | 1988-12-22 | 1988-12-22 | Manufacture of semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH02170436A true JPH02170436A (en) | 1990-07-02 |
Family
ID=18173982
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP63325187A Pending JPH02170436A (en) | 1988-12-22 | 1988-12-22 | Manufacture of semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH02170436A (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH04368122A (en) * | 1991-06-17 | 1992-12-21 | Sharp Corp | Ion implantation method of semiconductor device |
| JPH07326595A (en) * | 1994-05-31 | 1995-12-12 | Nec Kyushu Ltd | Manufacture of semiconductor device |
Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS62213277A (en) * | 1986-03-14 | 1987-09-19 | Nec Corp | Manufacture of semiconductor device |
-
1988
- 1988-12-22 JP JP63325187A patent/JPH02170436A/en active Pending
Patent Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS62213277A (en) * | 1986-03-14 | 1987-09-19 | Nec Corp | Manufacture of semiconductor device |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH04368122A (en) * | 1991-06-17 | 1992-12-21 | Sharp Corp | Ion implantation method of semiconductor device |
| JPH07326595A (en) * | 1994-05-31 | 1995-12-12 | Nec Kyushu Ltd | Manufacture of semiconductor device |
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