JP3311125B2 - Method for manufacturing semiconductor device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a method for manufacturing a semiconductor device.

[0002]

2. Description of the Related Art Regarding a conventional method of manufacturing a semiconductor device,
This will be described with reference to FIG. In this method, a silicide film is formed in a source / drain region in a self-aligned manner.

As shown in FIG. 2A, on a surface of a p-type semiconductor substrate, a field oxide film 202 is formed in an element isolation region, and a gate oxide film 203 is formed in an element region. Polycrystalline silicon is deposited on the gate oxide film 203, and is patterned to form a gate electrode 204.

[0004] A silicon oxide film or silicon nitride film is deposited on the entire surface, and reactive ion etching is performed.
As shown in FIG. 2B, the side wall 20 is formed on the side surface of the gate electrode 204.
5 are formed.

As shown in FIG. 2C, a metal film 210 is formed by sputtering a refractory metal such as titanium (Ti).

After that, a heat treatment is performed to
2 is silicided, and a silicide film 206 is formed in the source / drain region in a self-aligned manner as shown in FIG. The metal film 210 that has not been silicided is removed with sulfuric acid (H ₂ SO ₄ ) or the like.

As shown in FIG. 2E, after an interlayer insulating film 207 is formed and a contact hole 209 is opened, a metal such as aluminum (Al) is deposited and patterned to form a wiring layer 208. Is done.

However, such a conventional manufacturing method has the following problems.

When the contact hole 209 is opened, it is necessary to allow a margin of the dimensions X and Y in the element formation region as shown in FIG. As a result, the area has increased, and high integration has been hindered.

Conventionally, in order to form a silicide film in a source / drain region in a self-aligned manner, an LDD structure having the side wall 205 on the side surface of the gate electrode 204 has to be used as described above.

Next, another conventional manufacturing method will be described with reference to FIG. This method connects a wiring layer directly to the source / drain regions, and is called a direct contact. Through the same steps as in the method described above, FIG.
A field oxide film 302 and a gate oxide film 303 are formed on a p-type semiconductor substrate 301 as shown in FIG. Thereafter, a polycrystalline silicon film 304 is deposited.

As shown in FIG. 3B, a resist film 305 is formed by applying a resist and removing a portion of the contact hole 309, and etching is performed using the resist film 305 as a mask. The polycrystalline silicon film 304 is removed. Thereafter, the contact hole 30 is formed by ammonium fluoride (NH ₄ F).
The gate oxide film 303 exposed in the ninth portion is removed. Thereby, the contact hole 309 is opened.

After the resist film 305 is removed, FIG.
As shown in (c), a polycrystalline silicon film 310 is deposited on the whole. Phosphorus is diffused into polycrystalline silicon films 304 and 310. Phosphorus diffused into the polycrystalline silicon film 310
The source is diffused below the contact hole 309,
An n ⁺ -type diffusion layer 306 corresponding to the drain region is formed. This n ⁺ type diffusion layer 306 may be formed by implantation of phosphorus ions (P ⁺ ).

As shown in FIG. 3D, the polysilicon films 304 and 310 are etched using the resist film 311 as a mask. Thus, a structure is obtained in which the gate electrode 312 of the adjacent transistor is directly connected to the n ⁺ -type diffusion layer 306 of the own transistor.

However, the conventional manufacturing method has the following problems.

There is a misalignment between the mask for removing the gate oxide film 303 and the mask for forming the gate electrodes 312 and 313. Further, the gate electrode 313 of the own transistor and the n ⁺ -type diffusion layer 306 of the own transistor must have a separated structure.

Therefore, as shown in FIG. 3D, when forming the gate electrodes 312 and 313, the resist film 31 is formed.
1 has no gate oxide film 303 and has no semiconductor substrate 30.
1 has a portion where the surface is exposed. As a result, a part of the n ⁺ -type diffusion layer 306 is cut off by the etching at the time of forming the gate electrode. Thereby, the resistance value of the source / drain region increases.

Further, phosphorus ions (P.sup. ⁺ ) Are implanted into the shaved region to form an n.sup. ⁺ Type diffusion layer 307. However, the depth becomes deeper by the shaved area, and the transistor characteristics such as a decrease in operation speed are reduced. Causes a decline.

[0019]

As described above, FIG.
The conventional manufacturing method described in (1) has a problem that the dimensions of the transistor are large and that the method cannot be applied to transistors other than those having the LDD structure.

Further, the conventional manufacturing method shown in FIG. 3 has a problem that the resistance value of the source / drain region is increased, and the source / drain region is formed deeply, thereby deteriorating the transistor characteristics.

The present invention has been made in view of the above circumstances, has a large margin for mask alignment, has low resistance in the source and drain regions, prevents deterioration of transistor characteristics, and is applicable to transistors other than the LDD structure. It is an object of the present invention to provide a possible method for manufacturing a semiconductor device.

According to the method of manufacturing a semiconductor device of the present invention, a step of forming an element region and an element isolation region by performing element separation on a surface of a semiconductor substrate of one conductivity type, and a step of forming a gate oxide film on the element region Forming a gate electrode on the gate oxide film and the device isolation region; forming a nitride film on the surface of the gate electrode in a nitriding atmosphere; Removing a portion that is not covered with the above, exposing the surface of the semiconductor substrate in this portion, forming a high melting point metal film on the entire surface, and performing a heat treatment on the high melting point metal film, Forming a silicide film by silicidizing a portion of the metal film that is in contact with the surface of the semiconductor substrate; and removing a non-silicided portion of the high melting point metal film. And patterning by depositing a conductive material on the entire surface, and straddling the gate electrode on the element isolation region with the nitride film interposed in the different element regions and the surfaces of the respective semiconductor substrates in different element regions. Forming a first wiring layer including a pattern for connecting the semiconductor device with the silicide film formed on the surface of the semiconductor substrate therebetween, forming an interlayer insulating film, and forming a contact hole on the silicide film. A step of forming a hole and a step of depositing a conductive material over the entire surface and performing patterning to form a second wiring layer in contact with the surface of the first wiring layer and the surface of the silicide film in the contact hole And characterized in that:

[0023]

The silicide film can be formed in the source / drain region in a self-aligned manner even for a transistor having a structure having no side wall on the side surface of the gate electrode. When a contact is made between the opposite conductivity type diffusion layer and the second wiring layer, the interposition of the first wiring layer provides a large margin for mask misalignment, which contributes to a reduction in transistor area. Since the gate electrode and the second wiring layer are formed in different layers, the degree of freedom of wiring is high. There is no danger that the surface of the semiconductor substrate will be shaved by etching, the resistance value of this portion will not increase, and deterioration of transistor characteristics will be prevented.

[0024]

An embodiment of the present invention will be described below with reference to the drawings. FIG. 1 shows a method of manufacturing the semiconductor device according to the present embodiment step by step.

As in the conventional method described with reference to FIG. 2, first, as shown in FIG.
01, a field oxide film 102 and a gate oxide film 103
And a gate electrode 104 made of polycrystalline silicon is formed. Also, the gate electrode 105 of the same or another transistor exists on the field oxide film 102.

In a nitrogen (N ₂ ) or ammonia (NH ₃ ) atmosphere, the temperature is set to 9 degrees Celsius so that the gate electrode 104 is nitrided.
Heat treatment is performed at a temperature of 00 degrees. As a result, FIG.
As shown in (b), a silicon nitride film 106 is formed only on the surface and side surface of the gate electrode 104.

As shown in FIG. 1C, the semiconductor substrate 10 is etched with ammonium fluoride (NH ₄ F).
1 and the silicon nitride film 106 are not dissolved, but the surface is exposed. That is, only the gate oxide film 103 in a portion without a gate electrode is dissolved and removed. In this etching step, the gate oxide film 103 on the source / drain region is
Until completely removed. In this step, the field oxide film 102 is also slightly removed. However, no problem occurs if the field oxide film 102 is formed thick in advance.

As shown in FIG. 1D, titanium (Ti)
) Is sputtered to a thickness of about 500 Å to form a titanium film 107.

In a vacuum or inert gas atmosphere,
Heat treatment is performed at a temperature of 0 degrees. As a result, the titanium film 107 in direct contact with the semiconductor substrate 101 causes a silicide reaction, and a titanium silicide (TiSi ₂ ) film 108 is formed as shown in FIG.

Etching is performed with sulfuric acid (H ₂ SO ₄ ) or the like, and as shown in FIG. 1F, the titanium silicide film 108 and the field oxide film 102 are not removed.
Only the unreacted titanium film 107 is removed.

Polycrystalline silicon is deposited to a thickness of about 1000 angstroms, patterned, and
A polycrystalline silicon film 109 is formed as shown in FIG.
This polycrystalline silicon film 109 may be formed by using a high melting point metal such as titanium (Ti) or tungsten (W) instead of a metal film. In this case, it is preferable that the etching selectivity with the already formed titanium silicide film 108 and silicon oxide film is sufficient. When the film 109 is formed of polycrystalline silicon, a sufficient selectivity can be obtained by ordinary etching.

As shown in FIG. 1H, 30
A silicon oxide film is deposited to a thickness of 00 Å to form an interlayer insulating film 111. A contact hole 112 is formed at a position where the contact hole 112 is to be connected to the polycrystalline silicon film 109 and / or the titanium silicide film 108. After metal such as aluminum is deposited by sputtering,
The wiring layer 113 is formed by patterning.

Here, the ion implantation for forming the n ⁺ type diffusion layer 110 corresponding to the source / drain regions may be performed after any of the above-described steps of FIGS.

However, the process shown in FIG.
When ion implantation is performed during the step (d),
The following points need to be considered. That is, when the n ⁺ type diffusion layer 110 is formed after the step of FIG.
When the titanium film 205 is formed and silicidation is performed in the step shown in FIG. 4D, impurities in the n ⁺ type diffusion layer 110 are sucked out by the titanium silicide film 107. Thereby, the impurity concentration of the n ⁺ type diffusion layer 110 may be reduced.

[0035] In the case of forming the n ⁺ -type diffusion layer 110 by ion implantation immediately after the indicated step in FIG. 1 (a), the n ⁺ type in a nitriding atmosphere in the step shown in FIG. 1 (b) It is necessary to consider that the surface of the diffusion layer 110 may be nitrided. This step is not impossible, but in the present invention, ion implantation of the source / drain is desirable immediately after the formation of the gate electrode.

In the conventional manufacturing method shown in FIG. 2, when forming a contact hole 209 for making a contact with the drain / source region, a margin for mask misalignment is small. As a result, the element area is increased. In contrast, in this embodiment, the n ⁺ type diffusion layer 110
In the case where contact is made between the semiconductor device and the wiring layer 113, the polycrystalline silicon film 109 intervenes therebetween, so that there is a large margin for mask misalignment. This polycrystalline silicon film 10
9 may be present on the field oxide film 102 and n
The size of the ⁺ type diffusion layer 110 is not affected. For this reason, the element area can be reduced.

Also, the conventional method shown in FIG.
It can be applied only to a transistor having a structure.
However, the manufacturing method of the present embodiment does not have such restrictions,
For transistors without LDD structure sidewalls,
It is possible to form a silicide film in the source / drain region in a self-aligned manner. If the LDD side wall is formed of silicon nitride, there is no problem even if the present invention is applied to a transistor having an LDD structure.

The conventional manufacturing method shown in FIG. 3 uses the gate electrode 313 of its own transistor and the n ⁺ type diffusion layer 30.
6 are formed in the same layer. For this reason, the degree of freedom of wiring is low due to the necessity of separating them. Further, as shown in FIG. 3D, a part of the n ⁺ -type diffusion layer 306 is removed, and the resistance of the source / drain region increases.

On the other hand, in this embodiment, the gate electrode 10
4 and the wiring layer 113 are formed of different layers and have a separated structure, so that a high degree of freedom in wiring can be obtained. The gate electrode 104 is insulated by forming a silicon nitride film 106 on the surface. For this reason, the wiring layer 113 in contact with the source / drain region and the gate electrode 104 can be wired so as to intersect with each other, and higher wiring flexibility is obtained. Further, the surface of n ⁺ type diffusion layer 110 is not shaved, and the sheet resistance of the source / drain regions is low.

Further, when a part of the n ⁺ type diffusion layer 306 is cut away to form a deep diffusion region as in the prior art, the operation speed is reduced and the transistor characteristics are reduced. Is avoided.

Further, according to the present embodiment, the n ⁺ type diffusion layer 1
Since the titanium silicide film 108 is formed on the surface of the substrate 10, a low contact resistance can be obtained. The polycrystalline silicon film 109 is electrically connected to the n ⁺ -type diffusion layer 110 via the titanium silicide film 108. For this reason,
The conductivity type of the polycrystalline silicon film 109 is an n ⁺ type diffusion layer 110.
May be different from the p-type. Conversely, polycrystalline silicon is p
There is no problem if the diffusion layer is of the n-type or the same type. Further, since the patterning of the wiring layer 113 is sufficient only once, it contributes to the reduction in the number of steps.

The above embodiment is merely an example and does not limit the present invention. For example, the present invention can be similarly applied to the case where all the conductivity types shown in the embodiments are inverted. Further, the titanium film 107 in FIG. 1D may be a high melting point metal capable of forming silicide. Therefore, for example, cobalt ( _CO )
Alternatively, molybdenum ( _MO ), tungsten (W), or the like may be used.

The polycrystalline silicon film 109 shown in FIG. 1G may be formed of a metal. However, when a metal is used, it is preferable to use a high-melting-point metal so as to withstand heat treatment in a subsequent step of flattening.

[0044]

As described above, according to the method of manufacturing a semiconductor device of the present invention, a self-aligned silicide film is formed in a source / drain region even for a transistor having no side wall on the side surface of a gate electrode. Can be formed into
Even when a contact is made between the source / drain region and the second wiring layer, the first wiring layer in contact with the source / drain region is interposed therebetween, so that there is a large margin for mask misalignment. This contributes to a reduction in the area of the transistor. Further, since the gate electrode and the first and second wiring layers are formed in different layers, there is no need to separate them by etching, and a high degree of freedom in wiring can be obtained. Further, there is no possibility that the surface of the source / drain region is cut by etching, so that an increase in the resistance value in this portion and a decrease in transistor characteristics are prevented.

[Brief description of the drawings]

FIG. 1 is an element cross-sectional view illustrating a method of manufacturing a semiconductor device according to an embodiment of the present invention for each process.

FIG. 2 is an element cross-sectional view showing a conventional method of manufacturing a semiconductor device for each process.

FIG. 3 is an element cross-sectional view showing another conventional method of manufacturing a semiconductor device for each process.

[Explanation of symbols]

Reference Signs List 101 p-type semiconductor substrate 102 field oxide film 103, 103a gate oxide film 104, 105 gate electrode 106 silicon nitride film 107 titanium film 108 titanium silicide film 109 polycrystalline silicon film 110 n ⁺ type diffusion layer 111 interlayer insulating film 112 contact hole 113 Wiring layer

──────────────────────────────────────────────────続 き Continuation of front page (56) References JP-A-57-99775 (JP, A) JP-A-64-4069 (JP, A) JP-A-2-82639 (JP, A) JP-A-5-99 82470 (JP, A) Special Table Hei 5-503189 (JP, A) (58) Fields studied (Int. Cl. ⁷ , DB name) H01L 21/8234 H01L 27/088 H01L 29/78 H01L 21/336 H01L 21/28 301

Claims (3)

(57) [Claims] A step of forming an element region and an element isolation region by performing element isolation on a surface of the one conductivity type semiconductor substrate; a step of forming a gate oxide film on the element region; Forming a gate electrode on the device isolation region; forming a nitride film on the surface of the gate electrode in a nitriding atmosphere; removing a portion of the gate oxide film that is not covered with the gate electrode A step of exposing the surface of the semiconductor substrate in this portion; a step of forming a refractory metal film on the entire surface; and performing a heat treatment on the refractory metal film. Forming a silicide film by silicidizing a portion in contact with the surface; removing a non-silicided portion of the refractory metal film; Deposited to perform patterning,
The silicide film formed on the surface of the semiconductor substrate is interposed between the surfaces of the semiconductor substrates in the different element regions while straddling the gate electrode on the element isolation region with the nitride film interposed. Forming a first wiring layer including a pattern to be connected in a state of being connected, forming an interlayer insulating film, forming a contact hole on the silicide film, and depositing a conductive material on the entire surface. Perform patterning,
Forming a second wiring layer in contact with the surface of the first wiring layer and the surface of the silicide film in the contact hole. 2. The method according to claim 1, wherein said high melting point metal film is made of any one of titanium, tungsten, molybdenum and cobalt. 3. The semiconductor device according to claim 1, further comprising, after the step of forming the gate electrode on the gate oxide film, a step of introducing an impurity into an element region surface portion of the semiconductor substrate. Manufacturing method.