JPH04368122A - Ion implantation method of semiconductor device - Google Patents

Ion implantation method of semiconductor device

Info

Publication number
JPH04368122A
JPH04368122A JP14454691A JP14454691A JPH04368122A JP H04368122 A JPH04368122 A JP H04368122A JP 14454691 A JP14454691 A JP 14454691A JP 14454691 A JP14454691 A JP 14454691A JP H04368122 A JPH04368122 A JP H04368122A
Authority
JP
Japan
Prior art keywords
ion implantation
ion
uniformity
thin film
semiconductor substrate
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP14454691A
Other languages
Japanese (ja)
Inventor
Yasuhito Nakagawa
中川 泰仁
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Sharp Corp
Original Assignee
Sharp Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Sharp Corp filed Critical Sharp Corp
Priority to JP14454691A priority Critical patent/JPH04368122A/en
Publication of JPH04368122A publication Critical patent/JPH04368122A/en
Pending legal-status Critical Current

Links

Abstract

PURPOSE:To improve uniformity of through-ion implantation wherein ions are implanted in a semiconductor substrate through a thin film. CONSTITUTION:Through.ion implantation is a useful method which is resistive to impurity contamination and can reduce channeling at the time of ion implantation, because a film (insulating film or the like) protects the surface of a semiconductor substrate. Irregularity of film thickness, however, exerts an influence upon uniformity. In the case of a thin film, irregularity is reduced, but reduction effect of channeling is also decreased. In an ion implanter of parallel scan system, an ion beam enters parallel with the semiconductor substrate, and channeling is reduced. As a result, the above ion implanter is used, and ions are implanted through a thin film which reduces film thickness irregularity. Thereby uniformity is improved.

Description

【発明の詳細な説明】[Detailed description of the invention]

【0001】0001

【産業上の利用分野】本発明は、半導体素子の製造方法
、更に詳しくは半導体基板へのイオン注入方法に関する
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor device, and more particularly to a method for implanting ions into a semiconductor substrate.

【0002】0002

【従来の技術】化合物半導体、なかでもGaAsはSi
に比べて優れた物理的性質を持っているため、現在LS
I化の研究が活発に行われている。このGaAsLSI
を製作するプロセスの内で主要な技術であるイオン注入
技術は、均一性・再現性に優れていることから広く用い
られている。このイオン注入技術に求められている課題
は、大きくは (1)  FET(電界効果トランジスタ)のVth(
閾値電圧)の面内均一性向上 (2)  FETのVth(閾値電圧)の再現性向上(
3)  FETのVth(閾値電圧)の歩留まり向上の
3点である。
[Prior Art] Compound semiconductors, especially GaAs, are Si
Currently, LS
Research on integration is being actively conducted. This GaAsLSI
Ion implantation technology, which is the main technology in the manufacturing process, is widely used because of its excellent uniformity and reproducibility. The major issues faced by this ion implantation technology are (1) Vth (field effect transistor) of FET (field effect transistor);
Improved in-plane uniformity of FET Vth (threshold voltage) (2) Improved reproducibility of FET Vth (threshold voltage) (
3) There are three points to improve the yield of Vth (threshold voltage) of FET.

【0003】これらの課題はイオン注入装置の性能に依
存する所が大きい。図5にイオン注入時のイオンビーム
と半導体基板との位置関係を示す。現在用いられている
一般的な角度スキャン方式のイオン注入装置では、半導
体基板位置でのイオンビームの平行度が良くなく(3イ
ンチ基板内で±1.5°《図5のΔ》程度)、注入の入
射角度差に起因したチャネリングによるVthの分布(
片流れ分布;例えばJ.Kasahara  et  
al,“THE  EFFECT  OF  CHAN
NELING  ON  THE  LSI−GRAD
E  UNIFORMITY  OFGaAs−FET
s  BY  ION  IMPLANTATION”
,GaAsIC  Symposium,p,37.1
985)が生じる、という問題点があった。更に、通常
イオン注入の時はGaAs表面に直接レジストを塗布し
てイオン注入する。ベア注入を行うが、イオン注入用マ
スクとなるレジストの塗布・剥離工程は様々な薬品を使
用するため、GaAs表面が不純物で汚染され、均一性
・再現性が劣化する、という問題点もある。
These problems largely depend on the performance of the ion implanter. FIG. 5 shows the positional relationship between the ion beam and the semiconductor substrate during ion implantation. In the general angle scanning type ion implantation equipment currently in use, the parallelism of the ion beam at the semiconductor substrate position is not good (approximately ±1.5° (Δ in Figure 5) within a 3-inch substrate). Distribution of Vth due to channeling caused by the difference in incidence angle of injection (
Unilateral flow distribution; for example, J. Kasahara et.
al, “THE EFFECT OF CHAN
NELING ON THE LSI-GRAD
E UNIFORMITY OFGaAs-FET
s BY ION IMPLANTATION”
, GaAsIC Symposium, p, 37.1
985) occurs. Furthermore, when performing ion implantation, a resist is applied directly to the GaAs surface and ions are implanted. Bare implantation is performed, but since various chemicals are used in the process of applying and peeling off the resist that serves as the ion implantation mask, there is also the problem that the GaAs surface is contaminated with impurities, deteriorating uniformity and reproducibility.

【0004】このチャネリングの面内分布を改善するた
めの方法の一つとして、薄膜を通してイオン注入するス
ルー注入が挙げられる。この方法は、薄膜内でイオンを
散乱させることによりイオンの入射角度差を是正し、均
一なイオン注入を行うものである。また、GaAs表面
が薄膜で保護されているため、GaAs表面の汚染に関
する問題もなくなる。
One method for improving the in-plane distribution of channeling is through implantation in which ions are implanted through a thin film. This method corrects the difference in ion incidence angle by scattering ions within a thin film, and performs uniform ion implantation. Furthermore, since the GaAs surface is protected by a thin film, there is no problem with contamination of the GaAs surface.

【0005】[0005]

【発明が解決しようとする課題】前述のように、スルー
・イオン注入ではGaAs表面の汚染に関する問題はな
くなる。また、薄膜中でイオンが散乱されるため、チャ
ネリングも起こりにくい。しかし、薄膜を通してのスル
ー・イオン注入では膜厚・膜質の変化が注入分布に直接
影響を与える不安定性が懸念される。例えば、膜厚の均
一性・再現性が±5%とした時の触れ幅を表1に示す。
As mentioned above, through ion implantation eliminates the problem of contamination of the GaAs surface. Furthermore, since ions are scattered within the thin film, channeling is less likely to occur. However, with through ion implantation through a thin film, there is a concern about instability as changes in film thickness and film quality directly affect the implantation distribution. For example, Table 1 shows the contact width when the film thickness uniformity/reproducibility is ±5%.

【0006】[0006]

【表1】[Table 1]

【0007】チャネリングを防止するために必要な薄膜
の膜厚はイオン注入条件によって異なるが、1000Å
以上は必要である。仮に完全に均一なイオン注入が行え
ても、±50Åはイオン注入層の膜厚がばらつくことに
なる。ここで、高性能FETのイオン注入層の膜厚は〜
1000Åであり、またVth(イオン注入層の膜厚)
2 に比例して変化する事から、Vthのばらつきは±
10%(1.052≒1.10)変化することになる。 実際にはイオン注入のばらつきも加わるため、Vthの
ばらつきはさらに大きくなり、実用上不十分な値しか得
られない。
The thickness of the thin film required to prevent channeling varies depending on the ion implantation conditions, but is approximately 1000 Å thick.
The above is necessary. Even if completely uniform ion implantation could be performed, the thickness of the ion implanted layer would vary by ±50 Å. Here, the film thickness of the ion implantation layer of high performance FET is ~
1000 Å, and Vth (film thickness of ion implantation layer)
2, the variation in Vth is ±
This results in a change of 10% (1.052≒1.10). In reality, since variations in ion implantation are also added, the variations in Vth become even larger, resulting in a value that is insufficient for practical use.

【0008】従って、スルー注入を実用化するためには
、出来るだけ薄い膜厚でチャネリングを防止する必要が
ある。
Therefore, in order to put through injection into practical use, it is necessary to prevent channeling by making the film as thin as possible.

【0009】[0009]

【課題を解決するための手段】本発明は上記の点を鑑み
、膜厚(好ましくは100Å以下)を形成した半導体基
板に、平行スキャン方式でスキャンされるイオン注入装
置によりイオン注入する事により、性能の優れた半導体
素子を均一性・再現性良く形成する方法を提供すること
をその目的とする。
[Means for Solving the Problems] In view of the above points, the present invention implants ions into a semiconductor substrate formed with a film thickness (preferably 100 Å or less) using an ion implantation device scanned by a parallel scan method. The purpose is to provide a method for forming semiconductor elements with excellent performance with good uniformity and reproducibility.

【0010】0010

【作用】最近、イオンビームの平行度が改善された(3
インチ基板内で±0.3%以下)平行スキャン型イオン
注入装置が開発されている。発明者は、平行スキャン型
イオン注入装置によるスルー注入がこれらの問題点の解
決に有効ではないかと考えた。即ち、角度差が小さいた
め元々チャネリングが起こりにくく、薄膜の厚さは薄く
してもチャネリングの防止に充分な効果が有ることが予
想される。以下に結果を示す。
[Effect] Recently, the parallelism of the ion beam has been improved (3
(±0.3% or less within an inch substrate) A parallel scan type ion implanter has been developed. The inventor thought that through implantation using a parallel scan type ion implanter would be effective in solving these problems. That is, since the angular difference is small, channeling is difficult to occur in the first place, and it is expected that even if the thickness of the thin film is made thin, there will be a sufficient effect in preventing channeling. The results are shown below.

【0011】ここではチルト角φ,及びイオン注入時の
ターゲット・ホルダの回転数Rをパラメータとした。半
導体基板は3インチの半絶縁性GaAs基板を用い、表
面にプラズマCVD(p−CVD)により窒化ケイ素膜
(SiNx)を100Å堆積し、28Si+ を30k
eV  1×1013[cm−2 ] でイオン注入し
た。均一性の評価は熱波測定(内富ら「熱内測定による
GaAsイオン注入層評価」信学技報ED87−137
  p.19)により行った。結果を図6に示す。
Here, the tilt angle φ and the rotation speed R of the target holder during ion implantation were used as parameters. A 3-inch semi-insulating GaAs substrate was used as the semiconductor substrate, and a 100 Å silicon nitride film (SiNx) was deposited on the surface by plasma CVD (p-CVD), and 28Si+ was deposited at 30k.
Ion implantation was performed at eV 1×10 13 [cm −2 ]. Uniformity was evaluated by thermal wave measurement (Uchitomi et al. "Evaluation of GaAs ion-implanted layer by endothermal measurement" IEICE Technical Report ED87-137)
p. 19). The results are shown in FIG.

【0012】均一性はチルト角θ,方位角φ,回転数R
のいずれにも依存する。この依存性はGaAs結晶が持
っているチャネルに起因すると考えられ、変化する幅が
0.3〜0.5%と小さい(『ベア注入+角度スキャン
型イオン注入装置』による同様の実験では、3〜12%
で変動する[水谷ら「イオン注入におけるGaAsウエ
ハー面方位の最適化」1990春季応物学会29P−D
−1])。結局、チルト角θ=10°,方位角φ=20
°で最良の均一性0.3%が得られた。この値は『スル
ー注入+角度スキャン型イオン注入装置』での最良値〜
1%を凌ぐ。
[0012] Uniformity is determined by tilt angle θ, azimuth angle φ, and rotation speed R.
It depends on both. This dependence is thought to be due to the channel that the GaAs crystal has, and the width of the change is as small as 0.3 to 0.5% (in a similar experiment using a "bare implantation + angle scan type ion implanter", ~12%
[Mizutani et al. "Optimization of GaAs wafer surface orientation in ion implantation" 1990 Spring Society of Applied Physics 29P-D
-1]). After all, tilt angle θ = 10°, azimuth angle φ = 20
The best uniformity was obtained at 0.3%. This value is the best value for "through implantation + angle scan type ion implanter" ~
More than 1%.

【0013】[0013]

【実施例】以下、本発明の実施例について説明する。[Examples] Examples of the present invention will be described below.

【0014】(実施例1)図1において、1は半絶縁性
GaAs基板、2はp−CVDにより形成した厚さ10
0ÅのSiNxである。平行スキャン型イオン注入装置
により28Si+ を30keV  1×1013[c
m−2]イオン注入した。チルト角θは10°,方位角
φは20°である。この時、均一性は0.3%であった
(Example 1) In FIG. 1, 1 is a semi-insulating GaAs substrate, and 2 is a substrate with a thickness of 10 formed by p-CVD.
0 Å SiNx. 28Si+ was implanted at 30keV 1×1013 [c
m-2] ion implantation. The tilt angle θ is 10° and the azimuth angle φ is 20°. At this time, the uniformity was 0.3%.

【0015】(実施例2)図2は図1と同じ条件にて、
FETを形成するための選択イオン注入を行てる所の模
式図である。3は選択イオン注入された領域を示してい
る。実施例2のイオン注入部は実施例1と本質的な違い
が無いため、同程度の均一性が得られる。 (実施例3)図3において、4は蒸着された金属薄膜で
ある。本実施例ではTiである。図4はTiのイオン注
入素子能を示す(半導体基板の消衰係数を測定すること
によりイオン注入で導入されたダメージを評価したグラ
フ。イオン注入前の消衰係数は0.35程度)。〜40
0ÅのTiはGaAsへのイオン侵入をほぼ完全に止め
てしまうことが解る。この図から、Tiの膜厚は40Å
に設定した。薄膜として金属を用いると、イオン注入に
よるcharge  upも防止することが出来るため
、より均一性が向上する(特開平2−22817号参照
)。
(Example 2) FIG. 2 shows the results under the same conditions as FIG. 1.
FIG. 2 is a schematic diagram of a place where selective ion implantation can be performed to form an FET. 3 indicates a region into which selective ions have been implanted. Since the ion implantation part of Example 2 has no essential difference from Example 1, the same degree of uniformity can be obtained. (Example 3) In FIG. 3, 4 is a deposited metal thin film. In this example, it is Ti. FIG. 4 shows the performance of a Ti ion-implanted device (a graph that evaluates the damage introduced by ion implantation by measuring the extinction coefficient of the semiconductor substrate. The extinction coefficient before ion implantation is about 0.35). ~40
It can be seen that Ti of 0 Å almost completely stops ion penetration into GaAs. From this figure, the Ti film thickness is 40 Å.
It was set to When a metal is used as the thin film, charge up due to ion implantation can be prevented, thereby further improving the uniformity (see Japanese Patent Laid-Open No. 2-22817).

【0016】以上、いずれの実施例においても0.3%
以下の均一性が得られることが解った。これは従来のス
ルー・イオン注入では得られなかった良好な値である。
[0016] In all of the above examples, 0.3%
It was found that the following uniformity could be obtained. This is a good value that could not be obtained with conventional through ion implantation.

【0017】[0017]

【発明の効果】以上詳細に説明したように、本発明によ
る半導体基板へのイオン注入方法を用いる事により、従
来のイオン注入方法に比べて均一なイオン注入が行える
As described in detail above, by using the method of ion implantation into a semiconductor substrate according to the present invention, more uniform ion implantation can be performed than with conventional ion implantation methods.

【0018】また、スルー注入用薄膜の厚さを薄くでき
るので、低エネルギーイオン注入による注入層の高濃度
・薄層化も行えるため、形成される半導体素子の特性は
高性能である。
Furthermore, since the thickness of the through-implantation thin film can be reduced, the implanted layer can be made thinner and highly concentrated by low-energy ion implantation, so that the characteristics of the formed semiconductor element are high.

【図面の簡単な説明】[Brief explanation of drawings]

【図1】本発明の一実施例を説明するための図である。FIG. 1 is a diagram for explaining one embodiment of the present invention.

【図2】本発明の一実施例を説明するための図である。FIG. 2 is a diagram for explaining one embodiment of the present invention.

【図3】本発明の一実施例を説明するための図である。FIG. 3 is a diagram for explaining one embodiment of the present invention.

【図4】Ti薄膜の膜厚に対するイオン注入阻止能を示
す図である。
FIG. 4 is a diagram showing the ion implantation blocking ability with respect to the film thickness of a Ti thin film.

【図5】イオン注入時のイオンビームと半導体基板との
位置関係を示す図である。
FIG. 5 is a diagram showing the positional relationship between an ion beam and a semiconductor substrate during ion implantation.

【図6】チルト角,方位角,イオン注入時のターゲット
・ホルダの回転数をパラメータとした特性図である。
FIG. 6 is a characteristic diagram using the tilt angle, azimuth angle, and rotation speed of the target holder during ion implantation as parameters.

Claims (2)

【特許請求の範囲】[Claims] 【請求項1】  半導体基板にイオン注入する際に、イ
オンビームが平行スキャン方式でスキャンされるイオン
注入装置を用いることを特徴とする半導体素子の製造方
法において、イオン注入する半導体基板の表面に薄膜が
形成されていることを特徴とする半導体素子のイオン注
入方法。
1. A method for manufacturing a semiconductor device, characterized in that an ion implantation apparatus in which an ion beam is scanned in a parallel scanning manner is used when implanting ions into a semiconductor substrate. 1. A method for ion implantation of a semiconductor device, characterized in that: is formed.
【請求項2】  上記薄膜の膜厚が100Å以下である
ことを特徴とする半導体素子のイオン注入方法。
2. An ion implantation method for a semiconductor device, wherein the thickness of the thin film is 100 Å or less.
JP14454691A 1991-06-17 1991-06-17 Ion implantation method of semiconductor device Pending JPH04368122A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP14454691A JPH04368122A (en) 1991-06-17 1991-06-17 Ion implantation method of semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP14454691A JPH04368122A (en) 1991-06-17 1991-06-17 Ion implantation method of semiconductor device

Publications (1)

Publication Number Publication Date
JPH04368122A true JPH04368122A (en) 1992-12-21

Family

ID=15364814

Family Applications (1)

Application Number Title Priority Date Filing Date
JP14454691A Pending JPH04368122A (en) 1991-06-17 1991-06-17 Ion implantation method of semiconductor device

Country Status (1)

Country Link
JP (1) JPH04368122A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2004517469A (en) * 2000-10-30 2004-06-10 バリアン・セミコンダクター・エクイップメント・アソシエイツ・インコーポレイテッド Multi-mode ion implantation with non-parallel ion beams

Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS61295626A (en) * 1985-06-24 1986-12-26 Sumitomo Electric Ind Ltd Ion implantation method for compound semiconductor crystal
JPH01157047A (en) * 1987-09-30 1989-06-20 Ulvac Corp Parallel sweep device for electrostatic sweep type ion implanter
JPH01281721A (en) * 1988-05-09 1989-11-13 Sumitomo Electric Ind Ltd Method for preventing contamination of compound semiconductor wafer
JPH02170436A (en) * 1988-12-22 1990-07-02 Nec Corp Manufacture of semiconductor device
JPH02260360A (en) * 1989-03-31 1990-10-23 Ulvac Corp Ion implantation apparatus
JPH0322539A (en) * 1989-06-20 1991-01-30 Mitsubishi Electric Corp Manufacture of semiconductor device

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS61295626A (en) * 1985-06-24 1986-12-26 Sumitomo Electric Ind Ltd Ion implantation method for compound semiconductor crystal
JPH01157047A (en) * 1987-09-30 1989-06-20 Ulvac Corp Parallel sweep device for electrostatic sweep type ion implanter
JPH01281721A (en) * 1988-05-09 1989-11-13 Sumitomo Electric Ind Ltd Method for preventing contamination of compound semiconductor wafer
JPH02170436A (en) * 1988-12-22 1990-07-02 Nec Corp Manufacture of semiconductor device
JPH02260360A (en) * 1989-03-31 1990-10-23 Ulvac Corp Ion implantation apparatus
JPH0322539A (en) * 1989-06-20 1991-01-30 Mitsubishi Electric Corp Manufacture of semiconductor device

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2004517469A (en) * 2000-10-30 2004-06-10 バリアン・セミコンダクター・エクイップメント・アソシエイツ・インコーポレイテッド Multi-mode ion implantation with non-parallel ion beams

Similar Documents

Publication Publication Date Title
KR940007451B1 (en) Fabricating method of thin film transistor
US4149904A (en) Method for forming ion-implanted self-aligned gate structure by controlled ion scattering
US4144101A (en) Process for providing self-aligned doping regions by ion-implantation and lift-off
US4505023A (en) Method of making a planar INP insulated gate field transistor by a virtual self-aligned process
US4559693A (en) Process for fabricating field effect transistors
JPS61220424A (en) Manufacture of semiconductor device
JPH09320978A (en) Ion implantation
JPH04368122A (en) Ion implantation method of semiconductor device
US6596568B1 (en) Thin film transistor and fabricating method thereof
JP3555805B2 (en) Compound semiconductor device
JPH0282578A (en) Manufacture of thin film transistor
JPS5963767A (en) Semiconductor device
JPS58145168A (en) Semiconductor device
JP2798045B2 (en) Method of controlling threshold voltage of field effect transistor
Hattori et al. Noise reduction of pHEMTs with plasmaless SiN passivation by catalytic CVD
JPH03175678A (en) Manufacture of semiconductor device
JPS6142911A (en) Forming method of conductive layer by implanting ion
JP2726730B2 (en) Manufacturing method of field effect transistor
LAM et al. Lateral seeding of silicon-on-insulator[Final Report, 1 Jul.- 31 Dec. 1981]
JPS60733A (en) Semiconductor device and manufactur thereof
JPH02222547A (en) Manufacture of mos field-effect transistor
JPH06177157A (en) Compound semiconductor device and fabrication thereof
JPH04111431A (en) Manufacture of field-effect transistor
JPH0147023B2 (en)
JPH02111019A (en) Heat treatment