JPH01281721A - Method for preventing contamination of compound semiconductor wafer - Google Patents

Method for preventing contamination of compound semiconductor wafer

Info

Publication number
JPH01281721A
JPH01281721A JP11057288A JP11057288A JPH01281721A JP H01281721 A JPH01281721 A JP H01281721A JP 11057288 A JP11057288 A JP 11057288A JP 11057288 A JP11057288 A JP 11057288A JP H01281721 A JPH01281721 A JP H01281721A
Authority
JP
Japan
Prior art keywords
wafer
protective film
annealing
contamination
ion implantation
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP11057288A
Other languages
Japanese (ja)
Inventor
Makoto Kiyama
誠 木山
Shigeo Murai
重夫 村井
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Sumitomo Electric Industries Ltd
Original Assignee
Sumitomo Electric Industries Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Sumitomo Electric Industries Ltd filed Critical Sumitomo Electric Industries Ltd
Priority to JP11057288A priority Critical patent/JPH01281721A/en
Publication of JPH01281721A publication Critical patent/JPH01281721A/en
Pending legal-status Critical Current

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Abstract

PURPOSE:To enable an improved active layer to be formed with superb productivity by performing ion implantation, annealing under steam pressure of semiconductor constituting elements, and then eliminating a protection film immediately before device process after forming the protection film to a wafer whose surface is cleaned. CONSTITUTION:Ion is implanted into a chemical compound semiconductor wafer whose surface is cleaned and then annealing is performed under steam pressure of semiconductor constituting elements to allow an active layer to be formed. At this time, a protection film of 50Angstrom -1000Angstrom in thickness is formed on a wafer before and after ion implantation or after annealing and the protection film is eliminated immediately before device process. Thus, it prevents distortion or cracks from being generated, and constituting elements from being dissociated and enables ion implantation and annealing process to be performed while protecting the wafer against contamination.

Description

【発明の詳細な説明】 (産業上の利用分野) 本発明は、化合物半導体に活性層を形成する工程におけ
るウェハの汚染防止方法に関する。
DETAILED DESCRIPTION OF THE INVENTION (Field of Industrial Application) The present invention relates to a method for preventing contamination of a wafer in the process of forming an active layer on a compound semiconductor.

(従来の技術) 一般に、化合物半導体ウェハにイオン注入するときには
、注入によって生じた損傷の回復及び注入原子の活性化
のためにアニールを行う。
(Prior Art) Generally, when ions are implanted into a compound semiconductor wafer, annealing is performed to recover damage caused by the implantation and to activate the implanted atoms.

この活性層形成工程におけるウェハの汚染は、■イオン
注入時に真空ポンプなどから混入する不純物による汚染
、 ■アニール時の雰囲気ガス中の不純物による汚染、 ■ウェハの着脱時に用いるビンセットやトレイなどから
の汚染、 ■アニール後デバイスプロセスまでの保管J’JI I
fjl中にトレイなどからの汚染及びウェハ表面の劣化
、 等が予想される。その中でも、高温アニール時の汚染が
問題となる。
Contamination of the wafer during this active layer formation process is: (1) contamination due to impurities mixed in from the vacuum pump during ion implantation, (2) contamination due to impurities in the atmospheric gas during annealing, and (2) contamination from the bin sets and trays used for attaching and detaching the wafer. Contamination, ■Storage until device processing after annealing J'JI I
Contamination from trays, etc. and deterioration of the wafer surface are expected during fjl. Among these, contamination during high temperature annealing is a problem.

従来は、特開昭54−104770号公報に記載のよう
に保護膜を用いずにイオン注入及びアニールを行う方法
や、特開昭52−47675号公報に記載のようにアニ
ール時の半導体成分の解離防止のためにアニール前に保
護膜を形成する方法などが知られている。後者の方法は
、例えばGaAs半導体の保護膜として5iftやSi
、N4を用いると、高温アニール時に半導体成分が解離
して保護膜を拡散するために、GaAsの化学量論的組
成が変動することを問題とし、半導体を構成する元素を
保護膜に含有させることにより、組成変化を防止しよう
とするものである。
Conventionally, there has been a method of ion implantation and annealing without using a protective film as described in JP-A-54-104770, and a method of ion implantation and annealing without using a protective film as described in JP-A-52-47675. A method is known in which a protective film is formed before annealing to prevent dissociation. The latter method uses, for example, 5ift or Si as a protective film for GaAs semiconductors.
When N4 is used, the stoichiometric composition of GaAs changes due to the semiconductor components dissociating and diffusing into the protective film during high-temperature annealing. This is intended to prevent compositional changes.

(発明が解決しようとする課題) 上記のようにS s Ot * S 13 N a等の
保護膜を用いるときには、組成変化を十分に防止できな
いので、通常1000Å〜3000人という比較的厚い
保護膜を用いて組成変化を低く抑える方法がとられてき
た。
(Problems to be Solved by the Invention) As mentioned above, when using a protective film such as S s Ot * S 13 Na, composition changes cannot be sufficiently prevented, so a relatively thick protective film of 1000 Å to 3000 Å is usually used. A method has been used to suppress compositional changes by using

しかし、保護膜を厚(すると、ウェハと保護膜との膨張
率の違いにより、ウェハに大きな歪みを生じさせ、保護
膜にクラックや時には剥離を生じさせることもあり、そ
の結果、ウェハ表面の注入元素や不純物の異常分布が形
成されるという問題点があった。
However, the thicker the protective film (the difference in expansion rate between the wafer and the protective film) can cause large distortions in the wafer, leading to cracks and sometimes peeling of the protective film, resulting in poor implantation on the wafer surface. There was a problem in that an abnormal distribution of elements and impurities was formed.

本発明は、上記の問題点を解消し、歪・みやクラックの
発生を防止し、構成元素の解離を防ぎ、ウェハを汚染か
ら保護しながらイオン注入及びアニール処理を可能とす
るウエノ1の汚染防止方法を提供しようとするものであ
る。
The present invention solves the above-mentioned problems, prevents distortion and cracks from occurring, prevents dissociation of constituent elements, and prevents contamination of the wafer 1 by enabling ion implantation and annealing while protecting the wafer from contamination. It is intended to provide a method.

(課題を解決するための手段) 本発明は、表面を清浄化した化合物半導体ウェハに対し
てイオン注入し、半導体構成元素の蒸気圧の下でアニー
ルすることにより活性層を形成する工程の中で、イオン
注入の前後又はアニール後に、上記ウェハに膜厚50Å
〜1000人の保護膜を形成し、デバイスプロセスのB
、前に該保護膜を除くことを特徴とするウェハの汚染防
止方法である。
(Means for Solving the Problems) The present invention is directed to a step of forming an active layer by implanting ions into a compound semiconductor wafer whose surface has been cleaned and annealing it under the vapor pressure of semiconductor constituent elements. , before and after ion implantation or after annealing, a film thickness of 50 Å is applied to the above wafer.
~1000 protective film formation and device process B
, a wafer contamination prevention method characterized in that the protective film is removed before the wafer contamination is removed.

なお、保護膜はイオン注入するウェハ表面に加えてウェ
ハの側面や裏面にも形成してより完全な汚染防止をする
ことも可能である。保護膜の材質は5iOt+ Si、
lN4+ Att’3等の通常の材料を用いることがで
きる。
Note that the protective film can be formed not only on the surface of the wafer into which ions are implanted but also on the side and back surfaces of the wafer to more completely prevent contamination. The material of the protective film is 5iOt+Si,
Conventional materials such as lN4+ Att'3 can be used.

(作用) 第1図は本発明のウェハ汚染防止方法のフロー図である
。保護膜の形成時期により、次の3つの方法がある。ミ
ラー処理した化合物半導体ウェハを有機洗浄し、前処理
エツチングする工程は共通である。第1の方法は前処理
エツチング後、直ちに保護膜を形成し、それからイオン
注入し、アニールを行うものである。保護膜はデバイス
プロセスの直前まで保持することにより、汚染防止と劣
化防止の役割をする。第2の方法はイオン注入直後に保
護膜を形成するものであり、保護膜を介したイオン注入
が適当でない場合、ウェハ表面に直接イオン注入を行う
ものである。保護膜はアニール及びその後の汚染防止の
役割を果たす。第3の方法はイオン注入及びアニール後
に保護膜を形成するもので、デバイスプロセスまでの保
管期間の汚染防止と劣化防止の役割をする。
(Operation) FIG. 1 is a flow diagram of the method for preventing wafer contamination of the present invention. There are the following three methods depending on when the protective film is formed. The steps of organic cleaning and pre-etching of mirror-treated compound semiconductor wafers are common. The first method is to form a protective film immediately after pre-etching, then perform ion implantation and annealing. The protective film plays a role in preventing contamination and deterioration by maintaining it until just before device processing. The second method is to form a protective film immediately after ion implantation, and if ion implantation through the protective film is not appropriate, ion implantation is performed directly onto the wafer surface. The protective film serves to prevent annealing and subsequent contamination. The third method is to form a protective film after ion implantation and annealing, which serves to prevent contamination and deterioration during storage until device processing.

本発明に係る汚染防止用保護膜は、sQÅ〜1000人
と薄いので、ウェハと保護膜の間に膨張率の違いがあっ
ても、ウェハに大きな歪みを発生させることもなく、保
護膜にクラックができることもない。また、アニールは
半導体構成元素の蒸気圧の下で行うところから、ウエノ
)から高解離圧元素の抜けも防止される。なお、上記の
薄い保護膜は、均一なイオン注入にも好都合である。
The contamination prevention protective film according to the present invention is as thin as sQ Å~1000, so even if there is a difference in expansion coefficient between the wafer and the protective film, the wafer will not be significantly distorted and the protective film will not crack. There is nothing you can do. Furthermore, since the annealing is performed under the vapor pressure of the semiconductor constituent elements, the release of high dissociation pressure elements from the Ueno film is also prevented. Note that the above-mentioned thin protective film is also convenient for uniform ion implantation.

(実施例) 同一ロッドの近接した位置から切り出した2枚のGaA
sウェハに対して、150 KeV、2X10’雪e1
m −”でSi゛をイオン注入した。その後、1枚は表
面に500人の5isN4の保護膜を形成し、もう1枚
;ま保護膜なしで汚染状態の炉で故意にアニールし第2
図は、アニールしたウェハのc−v測定がら求めたトD
特性をグラフに示したものである。
(Example) Two pieces of GaA cut from the same rod at close positions
s wafer, 150 KeV, 2X10' snow e1
After that, one sheet was coated with a protective film of 500 5isN4 on the surface, and the second sheet was intentionally annealed in a contaminated furnace without a protective film.
The figure shows the D obtained from c-v measurements of annealed wafers.
The characteristics are shown in a graph.

LSS理論はイオン注入の条件(注入電圧、注入量、注
入元素)から決まる、注入イオンの分布であり、このL
SS理論曲線と実際のキャリア濃度分布曲線との比較で
汚染の有無、活性化の良しあしが決まる。同図から明ら
かなように、保護膜なしでアニールしたウェハは十分に
活性化されておらず、汚染され易いが、保護膜形成後に
アニールしたウェハは良好に活性化され、汚染に対して
防止効果があることが分かった。
LSS theory is the distribution of implanted ions determined by the ion implantation conditions (implantation voltage, implantation amount, implanted element), and this
The presence or absence of contamination and the quality of activation are determined by comparing the SS theoretical curve and the actual carrier concentration distribution curve. As is clear from the figure, wafers annealed without a protective film are not sufficiently activated and are susceptible to contamination, whereas wafers annealed after forming a protective film are well activated and are effective in preventing contamination. It turns out that there is.

(発明の効果) 本発明は上記構成を採用することにより、化合物半導体
に活性層を形成する工程の、イオン注入、アニール及び
その後の保管期間における汚染あるいは劣化を有効に防
止することができ、良好な活性化と高移動度を有する良
質な活性層を再現性良く形成することを可能とした。
(Effects of the Invention) By employing the above configuration, the present invention can effectively prevent contamination or deterioration during ion implantation, annealing, and the subsequent storage period in the step of forming an active layer in a compound semiconductor, resulting in a good This made it possible to form a high-quality active layer with good activation and high mobility with good reproducibility.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は本発明の汚染防止方法のフロー図であり、第2
図は実施例でGaAsウェハに形成した活性層のキャリ
ア濃度プロファイルを示した図である。
FIG. 1 is a flow diagram of the pollution prevention method of the present invention, and the second
The figure shows a carrier concentration profile of an active layer formed on a GaAs wafer in an example.

Claims (3)

【特許請求の範囲】[Claims] (1)化合物半導体に活性層を形成する工程のウェハの
汚染防止方法において、表面を清浄化したウェハに膜厚
50Å〜1000Åの保護膜を形成した後、イオン注入
し、半導体構成元素の蒸気圧の下でアニールし、デバイ
スプロセスの直前に該保護膜を除くことを特徴とするウ
ェハの汚染防止方法。
(1) In a method for preventing wafer contamination in the process of forming an active layer on a compound semiconductor, a protective film with a thickness of 50 Å to 1000 Å is formed on a wafer whose surface has been cleaned, and then ions are implanted to reduce the vapor pressure of the semiconductor constituent elements. 1. A method for preventing contamination of a wafer, the method comprising: annealing under a wafer and removing the protective film immediately before device processing.
(2)化合物半導体に活性層を形成する工程のウェハの
汚染防止方法において、表面を清浄化したウェハにイオ
ンを注入した後、膜厚50Å〜1000Åの保護膜を形
成し、次いで、半導体構成元素の蒸気圧の下でアニール
し、デバイスプロセスの直前に該保護膜を除くことを特
徴とするウェハの汚染防止方法。
(2) In a method for preventing contamination of a wafer in the process of forming an active layer on a compound semiconductor, after implanting ions into a wafer whose surface has been cleaned, a protective film with a thickness of 50 Å to 1000 Å is formed, and then semiconductor constituent elements A method for preventing contamination of a wafer, the method comprising: annealing under a vapor pressure of
(3)化合物半導体に活性層を形成する工程のウェハの
汚染防止方法において、表面を清浄化したウェハにイオ
ンを注入し、半導体構成元素の蒸気圧の下でアニールし
た後、膜厚50Å〜1000Åの保護膜を形成し、デバ
イスプロセスの直前に該保護膜を除くことを特徴とする
ウェハの汚染防止方法。
(3) In a method for preventing contamination of a wafer in the process of forming an active layer on a compound semiconductor, ions are implanted into a wafer whose surface has been cleaned, and after annealing under the vapor pressure of the semiconductor constituent elements, the film thickness is 50 Å to 100 Å. 1. A method for preventing contamination of a wafer, the method comprising: forming a protective film, and removing the protective film immediately before device processing.
JP11057288A 1988-05-09 1988-05-09 Method for preventing contamination of compound semiconductor wafer Pending JPH01281721A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP11057288A JPH01281721A (en) 1988-05-09 1988-05-09 Method for preventing contamination of compound semiconductor wafer

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP11057288A JPH01281721A (en) 1988-05-09 1988-05-09 Method for preventing contamination of compound semiconductor wafer

Publications (1)

Publication Number Publication Date
JPH01281721A true JPH01281721A (en) 1989-11-13

Family

ID=14539235

Family Applications (1)

Application Number Title Priority Date Filing Date
JP11057288A Pending JPH01281721A (en) 1988-05-09 1988-05-09 Method for preventing contamination of compound semiconductor wafer

Country Status (1)

Country Link
JP (1) JPH01281721A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH04368122A (en) * 1991-06-17 1992-12-21 Sharp Corp Ion implantation method of semiconductor device

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH04368122A (en) * 1991-06-17 1992-12-21 Sharp Corp Ion implantation method of semiconductor device

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