JPS63271923A - Heat treatment of compound semiconductor substrate - Google Patents
Heat treatment of compound semiconductor substrateInfo
- Publication number
- JPS63271923A JPS63271923A JP10526587A JP10526587A JPS63271923A JP S63271923 A JPS63271923 A JP S63271923A JP 10526587 A JP10526587 A JP 10526587A JP 10526587 A JP10526587 A JP 10526587A JP S63271923 A JPS63271923 A JP S63271923A
- Authority
- JP
- Japan
- Prior art keywords
- arsenic
- compound semiconductor
- semiconductor substrate
- heat treatment
- implanted
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000000758 substrate Substances 0.000 title claims abstract description 45
- 239000004065 semiconductor Substances 0.000 title claims abstract description 42
- 150000001875 compounds Chemical class 0.000 title claims abstract description 40
- 238000010438 heat treatment Methods 0.000 title claims abstract description 19
- 229910052785 arsenic Inorganic materials 0.000 claims abstract description 40
- RQNWIZPPADIBDY-UHFFFAOYSA-N arsenic atom Chemical compound [As] RQNWIZPPADIBDY-UHFFFAOYSA-N 0.000 claims abstract description 39
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims abstract description 20
- 229910052710 silicon Inorganic materials 0.000 claims abstract description 20
- 239000010703 silicon Substances 0.000 claims abstract description 20
- 238000000034 method Methods 0.000 claims abstract description 17
- 239000000470 constituent Substances 0.000 claims abstract description 9
- JBRZTFJDHDCESZ-UHFFFAOYSA-N AsGa Chemical compound [As]#[Ga] JBRZTFJDHDCESZ-UHFFFAOYSA-N 0.000 claims description 16
- 229910001218 Gallium arsenide Inorganic materials 0.000 claims description 16
- 235000012431 wafers Nutrition 0.000 description 17
- 239000013078 crystal Substances 0.000 description 3
- 238000000354 decomposition reaction Methods 0.000 description 3
- 238000005468 ion implantation Methods 0.000 description 3
- 238000000137 annealing Methods 0.000 description 2
- 230000007547 defect Effects 0.000 description 2
- 230000006866 deterioration Effects 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 239000000203 mixture Substances 0.000 description 2
- 230000001681 protective effect Effects 0.000 description 2
- 101100002917 Caenorhabditis elegans ash-2 gene Proteins 0.000 description 1
- GYHNNYVSQQEPJS-UHFFFAOYSA-N Gallium Chemical compound [Ga] GYHNNYVSQQEPJS-UHFFFAOYSA-N 0.000 description 1
- WLQSSCFYCXIQDZ-UHFFFAOYSA-N arsanyl Chemical compound [AsH2] WLQSSCFYCXIQDZ-UHFFFAOYSA-N 0.000 description 1
- 229910052733 gallium Inorganic materials 0.000 description 1
- 239000012535 impurity Substances 0.000 description 1
- 238000002347 injection Methods 0.000 description 1
- 239000007924 injection Substances 0.000 description 1
- 239000012212 insulator Substances 0.000 description 1
- 150000002500 ions Chemical class 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 239000000843 powder Substances 0.000 description 1
- 238000005979 thermal decomposition reaction Methods 0.000 description 1
Landscapes
- Formation Of Insulating Films (AREA)
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明は化合物半導体、特に蒸気圧の高いヒ素を４７４
成元素とするガリウムヒ素（Ｇａ ＡＳ ）などの化合
物半導体を熱処理する方法に関する。Detailed Description of the Invention [Industrial Application Field] The present invention uses compound semiconductors, particularly arsenic having a high vapor pressure,
The present invention relates to a method of heat treating a compound semiconductor such as gallium arsenide (Ga AS ) as a constituent element.
化合物半導体のうち、ヒ素（Ａｓ ＞を構成元素とする
半導体はヒ素が蒸気圧の高い元素であるため、熱処理中
にヒ素が飛散して化学量論的組成が変動し、結晶欠陥な
どの品質劣化を生じる。このため、従来より以下に示す
ような熱処理方法が提案されている。Among compound semiconductors, semiconductors with arsenic (As >) as a constituent element have a high vapor pressure, so arsenic scatters during heat treatment and the stoichiometric composition changes, resulting in quality deterioration such as crystal defects. Therefore, the following heat treatment methods have been proposed.
第１は、ＡｓＨ２を混合したガスを炉内に導入し、熱分
解でＡＳＳｉ２０ら生じるヒ素（Ａｓ ）の分圧を、そ
の分解圧以上に保つ方法（特公昭６０−４０６９４号）
である。第２の方法は、第２図に示されているものであ
る。すなわち、ガリウムヒ素などの化合物半導体基板１
０表裏両面に、基板１よりも径の大きな多結晶ガリウム
ヒ素保護板２．３をＯ〜５ＩｒｌＩｒ１の距離で対向さ
せた状態で熱処理を行う（特開昭５５−５６６３７号）
方法である。第３の方法は、第３図に示されているもの
である。すなわち、イオン注入されたガリウムヒ素基板
４をガリウムヒ素の多結晶（ガリウムヒ素単結晶、粉末
またはガリウムヒ素を含む絶縁物でもよい）からなる治
具５に載着すると共に、炉内のヒ素の分圧を一定値に維
持するように調整しなから熱処理を行う（特公昭６０−
４３６５８号）方法である。第４は、イオン注入された
ガリウムヒ素基板に対し、これ以上に多量にイオン注入
されて１１傷領域が多い別のガリウムヒ素基板を密着さ
せて熱処理を行う（特開昭５６−５０５２０号）方法で
ある。The first is a method in which a gas mixed with AsH2 is introduced into the furnace and the partial pressure of arsenic (As) produced from ASSi20 during thermal decomposition is maintained at a level higher than the decomposition pressure (Japanese Patent Publication No. 40694/1983).
It is. The second method is shown in FIG. That is, a compound semiconductor substrate 1 such as gallium arsenide
Heat treatment is performed on both the front and back surfaces of the substrate 1 with polycrystalline gallium arsenide protective plates 2.3 having a larger diameter than the substrate 1 facing each other at a distance of 0 to 5IrlIr1 (Japanese Unexamined Patent Publication No. 55-56637).
It's a method. A third method is shown in FIG. That is, the ion-implanted gallium arsenide substrate 4 is mounted on a jig 5 made of gallium arsenide polycrystal (gallium arsenide single crystal, powder, or an insulator containing gallium arsenide), and the arsenic in the furnace is removed. Heat treatment is performed after adjusting the pressure to maintain a constant value (Special Publication Act 1986-
43658) method. The fourth method is to heat-treat the ion-implanted gallium arsenide substrate by placing another gallium arsenide substrate in close contact with the ion-implanted gallium arsenide substrate, which has been implanted with a larger amount of ions and has many 11 scratch areas (Japanese Unexamined Patent Publication No. 56-50520). It is.
しかしながら、炉内をヒ素の雰囲下に調整する上記の方
法は、理論的には可能であってもその制御を実際に行う
のが難しく、現実的ではない。一方、ガリウムヒ素基板
に対して同材質のガリウムヒ素からなる保護板を使用す
る上記第２ないし第４の方法にあっては、ガリウムヒ素
が高価であるところから製造中値が高騰する。However, although the above method of adjusting the inside of the furnace to an arsenic atmosphere is theoretically possible, it is difficult to control it in practice and is not practical. On the other hand, in the second to fourth methods described above, in which a protective plate made of the same material as gallium arsenide is used for the gallium arsenide substrate, the manufacturing cost increases because gallium arsenide is expensive.
そこで本発明は、難しい制御を不要とし、しかも安価に
行うことができる化合物半導体基板の熱処理方法を提供
することを目的とする。SUMMARY OF THE INVENTION Therefore, an object of the present invention is to provide a method for heat treatment of a compound semiconductor substrate that does not require difficult control and can be performed at low cost.
本発明に係る化合物半導体基板の熱処理方法は、少なく
とも片面にヒ素（ＡＳ ＞がイオン注入されたシリコン
ウェーハのイオン注入面に、ヒ素を構成元素とする化合
物半導体（例えばガリウムヒ素）基板を密着させた状態
で熱処理することを特徴とする。The method for heat treatment of a compound semiconductor substrate according to the present invention includes closely adhering a compound semiconductor (e.g., gallium arsenide) substrate containing arsenic as a constituent element to the ion-implanted surface of a silicon wafer that has been ion-implanted with arsenic (AS) on at least one side. It is characterized by being heat treated in the state.
本発明に係る化合物半導体基板の熱処理方法は、以」こ
のように構成されるので、シリコンウェーハに注入され
たヒ素は化合物半導体基板からヒ素が飛散するのを防止
するように作用する。Since the method for heat treatment of a compound semiconductor substrate according to the present invention is configured as described above, the arsenic implanted into the silicon wafer acts to prevent arsenic from scattering from the compound semiconductor substrate.
以下、添付図面の第１図を参照して、本発明の詳細な説
明する。Hereinafter, the present invention will be described in detail with reference to FIG. 1 of the accompanying drawings.
第１図は本発明の一実施例に係る熱５１！！理状態を示
す側面図である。ガリウムヒ素のようにヒ素を−の構成
元素とする化合物半導体基板６が、シリコンウェーハ７
に密着されている。化合物半導体６は下面にはケイ素（
Ｓｉ ）などの不純物があらかじめイオン注入されてお
り、このイオン注入時のｊ１傷を回復するためアニール
処理に供されるものでおる。シリコンウェーハ７は一般
に半導体つ工−ハとして使用されているものであり、そ
の厚さは特に限定されないが、その径は少くとも化合物
半導体基板６と同径（好ましくは大径）のものが使用さ
れる。FIG. 1 shows a heat 51! according to an embodiment of the present invention. ! FIG. A compound semiconductor substrate 6 containing arsenic as a negative constituent element, such as gallium arsenide, is a silicon wafer 7.
is closely followed. The compound semiconductor 6 has silicon (
Impurities such as Si) are ion-implanted in advance, and annealing is performed to recover the j1 damage caused by the ion implantation. The silicon wafer 7 is generally used as a semiconductor wafer, and its thickness is not particularly limited, but a silicon wafer 7 having at least the same diameter as the compound semiconductor substrate 6 (preferably a large diameter) is used. be done.
このシリコンウェーハ７の片面にはヒ素がイオン注入さ
れており、そのヒ素注入面７ａは化合物半導体基板６に
密着され、密着状態でアニール処理を行う炉内に導入さ
れて熱処理が行われる。ここで、シリコンウェーハ７に
対するヒ素の注入量は特に限定されないが、化合物半導
体基板６からのヒ素の飛散を抑制する点から、少なくと
も化合物半導体基板６中のヒ素の含有量以上であること
が好ましい。しかしながら、熱処理条件、化合物半導体
基板６のイオン注入条件等により基板６からのヒ素の飛
散が容易に抑制できる場合には、化合物半導体基板６中
のヒ素含有ｍよりも少ない注人足であってもよい。Arsenic is ion-implanted into one side of the silicon wafer 7, and the arsenic-implanted surface 7a is brought into close contact with the compound semiconductor substrate 6, and the silicon wafer 7 is introduced into a furnace for annealing treatment while in close contact with the compound semiconductor substrate 6, where it is heat-treated. Here, the amount of arsenic implanted into the silicon wafer 7 is not particularly limited, but from the viewpoint of suppressing the scattering of arsenic from the compound semiconductor substrate 6, it is preferably at least the content of arsenic in the compound semiconductor substrate 6. However, if the scattering of arsenic from the substrate 6 can be easily suppressed by heat treatment conditions, ion implantation conditions of the compound semiconductor substrate 6, etc., even if the amount of arsenic is less than the arsenic content m in the compound semiconductor substrate 6. good.
このように、化合物半導体基板６がシリコンウェーハ７
のヒ素注入面７ａに密着した状態では、シリコンウェー
ハ７のＩｌ：素性入面７ａはヒ素イＡンの注入による１
１は多いので、注入面７８に：おけるヒ素の分解圧は相
対的に高く、化合物半導体基板６のヒ素の分解圧は相対
的に低くなる。そのため、化合物半導体基板６からのヒ
素の飛散が抑制されるので、基板６の化学ω論的組成の
変動を防止でき、結晶欠陥などの品質劣化を防止するこ
とができる。また、炉内にヒ素を導入して、その濃度を
調整する必要がないから熱処理操作が容易となる。また
、シリコンウェーハ７にヒ素のみをイオン注入して化合
物半導体基板６の保ｆｆｌ＋、４とし、高価なガリウム
等を用いる必要がないので、安価に熱処理することがで
きる。In this way, the compound semiconductor substrate 6 is transferred to the silicon wafer 7.
When the silicon wafer 7 is in close contact with the arsenic implanted surface 7a, the Il: elemental implanted surface 7a of the silicon wafer 7 is
1 is large, the decomposition pressure of arsenic at the injection surface 78 is relatively high, and the decomposition pressure of arsenic in the compound semiconductor substrate 6 is relatively low. Therefore, since the scattering of arsenic from the compound semiconductor substrate 6 is suppressed, it is possible to prevent variations in the schemiochemical composition of the substrate 6, and to prevent quality deterioration such as crystal defects. Furthermore, since there is no need to introduce arsenic into the furnace and adjust its concentration, the heat treatment operation becomes easier. Furthermore, only arsenic is ion-implanted into the silicon wafer 7 to stabilize the compound semiconductor substrate 6, and since there is no need to use expensive gallium or the like, heat treatment can be performed at low cost.
本発明は上記実施例に限定されるものではなく、種々の
変形が可能である。The present invention is not limited to the above embodiments, and various modifications are possible.
例えば、シリコンウェーハの両面にヒ素を注入し、この
両面に化合物半導体基板６を密着して、サンドイッチ状
態で熱処理してもよい。この場合は、シワコンウェーハ
の必要枚数は減じるから、操作性が向上しさらに安価と
することができる。For example, arsenic may be implanted into both surfaces of a silicon wafer, and the compound semiconductor substrate 6 may be closely attached to both surfaces, and the wafer may be heat-treated in a sandwich state. In this case, the required number of wrinkled wafers is reduced, so the operability is improved and the cost can be further reduced.
また、熱処理される化合物半導体基板として【よ、ヒ素
を構成元素として含むものであれば他の元素は特に限定
されない。Further, other elements are not particularly limited as long as the compound semiconductor substrate to be heat-treated contains arsenic as a constituent element.
（発明の効果）
以上、詳細に説明した通り、本発明に係る化合物半導体
基板の熱処理方法によれば、シリコンウェーハのヒ素（
Ａｓ ＞イオン注入面に化合物半導体）；を板を密若さ
けるので、化合物半導体基板からのヒ素の飛散を効果的
に抑制できると共に、熱処理操作が容易で運転経費も安
価とすることができる効果がある。(Effects of the Invention) As described above in detail, according to the method for heat treatment of a compound semiconductor substrate according to the present invention, arsenic (
Since the plate is closely spaced with As > compound semiconductor on the ion-implanted surface, scattering of arsenic from the compound semiconductor substrate can be effectively suppressed, and the heat treatment operation is easy and operating costs are low. be.
第１図は本発明に係る熱処理における側面図、第２図Ｊ
３よび第３図は従来技術の各側を示す側面図でおる。
６・・・化合物半導体基板、７・・・シリコンウェーハ
、７ａ・・・イオン注入面。
本 発 明
第１図
従 来 例
第 ２ 図
従 来 例
第 ３ 図Fig. 1 is a side view of heat treatment according to the present invention, Fig. 2 J
3 and 3 are side views showing each side of the prior art. 6... Compound semiconductor substrate, 7... Silicon wafer, 7a... Ion implantation surface. Present invention Figure 1 Conventional example Figure 2 Conventional example Figure 3
Claims (1)
ウェーハの前記イオン注入面に、ヒ素を構成元素とする
化合物半導体基板を密着させた状態で熱処理することを
特徴とする化合物半導体基板の熱処理方法。 ２、前記化合物半導体基板はガリウムヒ素基板である特
許請求の範囲第１項記載の化合物半導体基板の熱処理方
法。[Claims] 1. A compound semiconductor characterized in that a compound semiconductor substrate containing arsenic as a constituent element is heat-treated in a state in which a compound semiconductor substrate containing arsenic as a constituent element is brought into close contact with the ion-implanted surface of a silicon wafer in which arsenic is ion-implanted on at least one side. Heat treatment method for substrates. 2. The method for heat treatment of a compound semiconductor substrate according to claim 1, wherein the compound semiconductor substrate is a gallium arsenide substrate.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP10526587A JPS63271923A (en) | 1987-04-28 | 1987-04-28 | Heat treatment of compound semiconductor substrate |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP10526587A JPS63271923A (en) | 1987-04-28 | 1987-04-28 | Heat treatment of compound semiconductor substrate |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS63271923A true JPS63271923A (en) | 1988-11-09 |
Family
ID=14402829
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP10526587A Pending JPS63271923A (en) | 1987-04-28 | 1987-04-28 | Heat treatment of compound semiconductor substrate |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS63271923A (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS6454725A (en) * | 1987-08-26 | 1989-03-02 | Sony Corp | Heat treating method for compound semiconductor substrate |
| JP2006339396A (en) * | 2005-06-02 | 2006-12-14 | Kwansei Gakuin | Ion implantation annealing method, method of manufacturing semiconductor element, and semiconductor element |
-
1987
- 1987-04-28 JP JP10526587A patent/JPS63271923A/en active Pending
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS6454725A (en) * | 1987-08-26 | 1989-03-02 | Sony Corp | Heat treating method for compound semiconductor substrate |
| JP2006339396A (en) * | 2005-06-02 | 2006-12-14 | Kwansei Gakuin | Ion implantation annealing method, method of manufacturing semiconductor element, and semiconductor element |
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