JPS6043658B2 - Manufacturing method of semiconductor device - Google Patents
Manufacturing method of semiconductor deviceInfo
- Publication number
- JPS6043658B2 JPS6043658B2 JP54119881A JP11988179A JPS6043658B2 JP S6043658 B2 JPS6043658 B2 JP S6043658B2 JP 54119881 A JP54119881 A JP 54119881A JP 11988179 A JP11988179 A JP 11988179A JP S6043658 B2 JPS6043658 B2 JP S6043658B2
- Authority
- JP
- Japan
- Prior art keywords
- heat treatment
- pressure
- implanted
- gaas
- substrate
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
- 239000004065 semiconductor Substances 0.000 title claims description 17
- 238000004519 manufacturing process Methods 0.000 title claims description 4
- 238000000034 method Methods 0.000 claims description 23
- 239000000758 substrate Substances 0.000 claims description 16
- 150000001875 compounds Chemical class 0.000 claims description 15
- 239000013078 crystal Substances 0.000 claims description 8
- 239000000470 constituent Substances 0.000 claims description 7
- 239000000843 powder Substances 0.000 claims description 5
- 239000012212 insulator Substances 0.000 claims description 3
- -1 polycrystal Substances 0.000 claims 1
- 238000010438 heat treatment Methods 0.000 description 21
- JBRZTFJDHDCESZ-UHFFFAOYSA-N AsGa Chemical compound [As]#[Ga] JBRZTFJDHDCESZ-UHFFFAOYSA-N 0.000 description 16
- 229910001218 Gallium arsenide Inorganic materials 0.000 description 15
- 150000002500 ions Chemical class 0.000 description 9
- 230000001681 protective effect Effects 0.000 description 9
- 229910052785 arsenic Inorganic materials 0.000 description 8
- 238000009792 diffusion process Methods 0.000 description 8
- RQNWIZPPADIBDY-UHFFFAOYSA-N arsenic atom Chemical compound [As] RQNWIZPPADIBDY-UHFFFAOYSA-N 0.000 description 7
- 230000002159 abnormal effect Effects 0.000 description 6
- 230000007547 defect Effects 0.000 description 5
- 238000007796 conventional method Methods 0.000 description 4
- 238000010494 dissociation reaction Methods 0.000 description 4
- 230000005593 dissociations Effects 0.000 description 4
- 238000002513 implantation Methods 0.000 description 4
- 239000000203 mixture Substances 0.000 description 4
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 3
- 230000004913 activation Effects 0.000 description 3
- 229910052710 silicon Inorganic materials 0.000 description 3
- 239000010703 silicon Substances 0.000 description 3
- RBFQJDQYXXHULB-UHFFFAOYSA-N arsane Chemical compound [AsH3] RBFQJDQYXXHULB-UHFFFAOYSA-N 0.000 description 2
- 230000007423 decrease Effects 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- 229910052733 gallium Inorganic materials 0.000 description 2
- GYHNNYVSQQEPJS-UHFFFAOYSA-N Gallium Chemical compound [Ga] GYHNNYVSQQEPJS-UHFFFAOYSA-N 0.000 description 1
- 230000005355 Hall effect Effects 0.000 description 1
- UFHFLCQGNIYNRP-UHFFFAOYSA-N Hydrogen Chemical compound [H][H] UFHFLCQGNIYNRP-UHFFFAOYSA-N 0.000 description 1
- 229910052581 Si3N4 Inorganic materials 0.000 description 1
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 1
- 229910000070 arsenic hydride Inorganic materials 0.000 description 1
- LULLIKNODDLMDQ-UHFFFAOYSA-N arsenic(3+) Chemical compound [As+3] LULLIKNODDLMDQ-UHFFFAOYSA-N 0.000 description 1
- 238000006243 chemical reaction Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 229910052739 hydrogen Inorganic materials 0.000 description 1
- 239000001257 hydrogen Substances 0.000 description 1
- 238000002347 injection Methods 0.000 description 1
- 239000007924 injection Substances 0.000 description 1
- 238000005259 measurement Methods 0.000 description 1
- 229910052751 metal Inorganic materials 0.000 description 1
- 239000002184 metal Substances 0.000 description 1
- 229920006395 saturated elastomer Polymers 0.000 description 1
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 1
- 229910052814 silicon oxide Inorganic materials 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/324—Thermal treatment for modifying the properties of semiconductor bodies, e.g. annealing, sintering
- H01L21/3245—Thermal treatment for modifying the properties of semiconductor bodies, e.g. annealing, sintering of AIIIBV compounds
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Junction Field-Effect Transistors (AREA)
Description
【発明の詳細な説明】
本発明はイオン注入した半導体装置の熱処理方法に関
するものである。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a method of heat treating a semiconductor device into which ions have been implanted.
一般にイオン注入した半導体装置は注入したイオンを
活性化するため及び注入時に発生した結晶損傷を回復せ
しめるため熱処理する必要がある。Generally, a semiconductor device into which ions have been implanted needs to be subjected to heat treatment in order to activate the implanted ions and to recover from crystal damage caused during implantation.
シリコン（Ｓｉ）等の単体半導体では高温熱処理で表面
解離が起つて化学量論的組成が変化することがないため
熱処理には表面保護膜を必要としないか或は必要として
も簡単な表面保護膜で充分である。 一方、化合物半導
体は高温熱処理で表面の解離が起り化学量論的組成が変
化するので、これを防ぐためには適当な保護膜でおおう
か、或は化合物を構成する元素の雰囲気中で熱処理する
方法がとられている。Single semiconductors such as silicon (Si) do not require a surface protective film during heat treatment, or even if necessary, a simple surface protective film because surface dissociation occurs during high-temperature heat treatment and the stoichiometric composition does not change. is sufficient. On the other hand, when compound semiconductors are subjected to high-temperature heat treatment, their surface dissociation occurs and the stoichiometric composition changes, so in order to prevent this, it is necessary to cover them with an appropriate protective film, or to heat-treat them in the atmosphere of the elements that make up the compound. is taken.
化合物半導体として、ガリウム砒素（ＧａＡｓ）につい
て説明すると、ＧａＡｓの場合、保護膜としてはシリコ
ン酸化膜（Ｓｉ００）やシリコン窒化膜（Ｓｉ。Ｎ０）
が一般に用いられている。又、化合物を構成する元素の
雰囲気中で熱処理する方法としては第１図に示す様に、
反応管１内に砒素を飽和したガリウムＧａ／ＧａＡｓ２
を、基台３に試料のＧａＡｓ４を設置し、試料とほゞ平
衡に近いＭ圧を供給して、試料の化学量論的組成からの
ずれを防ぐ方法或は基板を構成する元素でイオン注入し
た基板を覆い、基板の組成変化を抑制する方法（特願昭
５０−１２４１９号明細書）等がある。 保護膜を用い
て熱処理する場合には、適当な保護膜を用いることによ
り高温熱処理（列えば９００℃）が可能となり、活性化
率が向上し、注入時の損傷を回復せしめることが可能で
あるが、保護膜と基板の熱膨脹係数の差による結晶欠陥
の発生、結晶欠陥に伴う注入イオンの異常拡散等が発生
する。 一方、化合物を構成する元素の雰囲気で熱処理
する方法は、保護膜を用いないため熱膨脹係数の差によ
る歪による結晶欠陥は発生しない。Explaining gallium arsenide (GaAs) as a compound semiconductor, in the case of GaAs, silicon oxide film (Si00) or silicon nitride film (Si.N0) is used as a protective film.
is commonly used. In addition, as shown in Figure 1, the method of heat treatment in the atmosphere of the elements constituting the compound is as follows.
Gallium Ga/GaAs2 saturated with arsenic in reaction tube 1
In this method, a GaAs4 sample is placed on the base 3 and an M pressure that is almost in equilibrium with the sample is supplied to prevent deviation from the stoichiometric composition of the sample, or ions are implanted with elements constituting the substrate. There is a method (Japanese Patent Application No. 12419/1982) of suppressing changes in the composition of the substrate by covering the substrate. When performing heat treatment using a protective film, using an appropriate protective film enables high-temperature heat treatment (for example, 900°C), improving the activation rate and making it possible to recover from damage during implantation. However, crystal defects occur due to the difference in thermal expansion coefficient between the protective film and the substrate, and abnormal diffusion of implanted ions occurs due to the crystal defects. On the other hand, the method of heat treatment in the atmosphere of the elements constituting the compound does not use a protective film, so crystal defects due to distortion due to differences in thermal expansion coefficients do not occur.
しかし、高温熱処理の場合、基板構成元素のいずれかの
空孔が発生し深い準位を形成する。 本発明は保護膜を
用いない熱処理方法の改良に関するもので上記欠点が除
去された化合物半導体の改良された熱処理方法を提供す
るもので活性化率を高め、結晶欠陥の発生を抑制し、注
入イオンの異常拡散を防止せしめる製造方法である。However, in the case of high-temperature heat treatment, vacancies are generated in one of the substrate constituent elements to form a deep level. The present invention relates to an improved heat treatment method that does not use a protective film, and provides an improved heat treatment method for compound semiconductors that eliminates the above-mentioned drawbacks, increases the activation rate, suppresses the occurrence of crystal defects, and improves the efficiency of implanted ions. This is a manufacturing method that prevents abnormal diffusion of
以下、本発明をＧａＡｓを例にとり図面と共に実施例
に基づいて説明する。実施例 １
第２図ａ−ｃは本発明の一実施例を示す製造工程断面
図である。Hereinafter, the present invention will be explained based on drawings and examples, taking GaAs as an example. Embodiment 1 FIGS. 2a-2c are sectional views showing manufacturing steps of an embodiment of the present invention.
機械的、化学的に処理した半絶縁性ＧａＡｓ基板５にシ
リコンＳｉ＋６をイオン注入する。Silicon Si+6 is ion-implanted into a mechanically and chemically treated semi-insulating GaAs substrate 5.
注入条件は１５０ＫｅＶで、注入量３×１０１２ｃ！Ｒ
ｔ−２を室温で注入した。しかる後、多結晶ＧａＡｓか
らなる治具７に、イオン注入した試料を設置し、砒素圧
（Ａｓ圧）２×１Ｃｆ！ＴＯｒｒにして８７０℃で３扮
間水素雰囲気中で熱処理した。Ｍ圧は第１図で２の部分
に金属砒素を設置し、２の部分の温度を５６０℃に設定
して砒素圧を２×１σＴＯｒｒとした。The implantation conditions were 150KeV and the implantation amount was 3×1012c! R
t-2 was injected at room temperature. Thereafter, the ion-implanted sample was placed in a jig 7 made of polycrystalline GaAs, and an arsenic pressure (As pressure) of 2×1 Cf! Heat treatment was performed at 870° C. for 3 days in a hydrogen atmosphere. For the M pressure, metal arsenic was installed in the part 2 in FIG. 1, and the temperature of the part 2 was set at 560° C., so that the arsenic pressure was 2×1σTOrr.
ホール効果により測定したキャリヤ濃度Ｎｓは（２．８
±０．１）×１０１２ｃｍ１移動度μＨは４５００ｃＩ
ｔ／Ｖ．ｓｅｃである。又注入層のキャリヤ濃度分布は
第３図の様になり、ほＳ゛論理曲線と一致した。又この
基板を用いてゲート長１μｍ１ゲート巾３００μｍのシ
ョットキゲートを有するＦＥＴを試作すると、ドレイン
−ソース間電圧■ＰＳ＝３．１Ｖ、ドレイン電流１ｃ．
＝８ｍＡで測定周波数ｆ＝４Ｇ比で雑音指数Ｎ．Ｆは１
．９ｄＢであつた。本実施例でキャリヤ濃度、移動度が
高く、キャリヤ濃度分布に異常拡散がなく、ＦＥＴのＮ
．Ｆが低いのは、基板構成元素であるＧａの解離を多結
晶ＧａＡｓの治具で防止し、Ａｓの解離を制御した砒素
圧で防止しているためと推定される。この方法は、多結
晶ＧａＡｓにより、試料とほ）゛平衡に近いＧａ圧を供
給し、外部からＭ圧を供給するものである。The carrier concentration Ns measured by the Hall effect is (2.8
±0.1)×1012cm1 Mobility μH is 4500cI
t/V. sec. Further, the carrier concentration distribution in the injection layer was as shown in FIG. 3, and almost coincided with the S' logical curve. Furthermore, when a FET having a Schottky gate with a gate length of 1 μm and a gate width of 300 μm is prototyped using this substrate, the drain-source voltage PS=3.1V and the drain current 1c.
= 8mA, measurement frequency f = 4G ratio, noise figure N. F is 1
．． It was 9dB. In this example, the carrier concentration and mobility are high, there is no abnormal diffusion in the carrier concentration distribution, and the FET N
．． The reason why F is low is presumed to be because the dissociation of Ga, which is a constituent element of the substrate, is prevented by the polycrystalline GaAs jig, and the dissociation of As is prevented by the controlled arsenic pressure. In this method, polycrystalline GaAs is used to supply Ga pressure that is close to equilibrium with the sample, and M pressure is supplied from the outside.
従来の単に多結晶ＧａＡｓ板或はＧａ，Ａｓ粉末中に設
置して熱処理する方法と比較すると、従来の方法では高
温処理で多結晶ＧａＡｓ板或はＧａＡｓ粉末から主に、
Ａｓが蒸発し損壊し、特に態圧を供給する方法（第１図
）は基板にＧａ空孔が発生しない温度範囲であれば、本
発明と同様の効果が期待できるが、高温熱処理ではＧａ
の空孔が発生し注入イオンの異常拡散及びＧａ空孔発生
に伴うＮ．Ｆの増大．をきたす。Compared to the conventional method of simply placing the polycrystalline GaAs plate or Ga, As powder in the heat treatment method, the conventional method mainly heat-treats the polycrystalline GaAs plate or GaAs powder by high-temperature treatment.
In particular, the method of supplying atmospheric pressure (Fig. 1), in which As evaporates and is destroyed, can be expected to have the same effect as the present invention as long as the temperature range does not generate Ga vacancies in the substrate.
vacancies are generated, abnormal diffusion of implanted ions and N. Increase in F. cause
第４図は実施例で熱処理９００℃で３紛間行つたときの
本発明の方法で熱処理したときのキャリヤ濃度分布を第
４図ａに、第１図の方法で行つたときのキャリヤ濃度分
布をｂに示す。Figure 4 shows the carrier concentration distribution when the heat treatment was carried out using the method of the present invention at 900°C for three times in an example, and Figure 4a shows the carrier concentration distribution when the heat treatment was carried out using the method shown in Figure 1. is shown in b.
第４図Ａ，ｂ・から明らかな様に、本発明の方法ではほ
とんどキャリヤ濃度分布は論理曲線に一致するが、第１
図の従来方法の場合はＧａ空孔を介してと椎測される増
速拡散が観測される。又ＦＥＴを実施例と同様の方法を
試作し、雑音紙数を比較すると、本発明の方法ではＮ．
Ｆ＝１．９ｄＢに対し、第１図従来方法では、Ｎ．Ｆ＝
２．５ｄＢであつた。雑音指数が本発明の方法で熱処理
することにより、減少するのは、結晶欠陥の発生、特に
Ｇａ空孔の発生を抑制しているため及び半絶縁性基板界
面近傍でのキャリヤ濃度が増速拡散がないため急峻であ
るためと考えられる。実施例では、外部から供給するＡ
ｓ圧として、７２×１ｃｆ！：ＴＯｒｒの場合について
説明したが、Ｍ圧としては２０Ｔ０ｒｒ〜５００Ｔ０ｒ
ｒが移動度、キャリヤ濃度分布ＦＥＴ（７）Ｎ．Ｆの点
で良好であつた。As is clear from FIGS. 4A and 4B, in the method of the present invention, the carrier concentration distribution almost matches the logical curve, but the first
In the case of the conventional method shown in the figure, accelerated diffusion is observed via Ga vacancies. In addition, when an FET was prototyped using the same method as in the example and the number of noise sheets was compared, it was found that the method of the present invention had N.
F=1.9 dB, whereas in the conventional method shown in FIG. F=
It was 2.5dB. The noise figure is reduced by heat treatment according to the method of the present invention because the generation of crystal defects, especially Ga vacancies, is suppressed, and the carrier concentration near the semi-insulating substrate interface is reduced by accelerated diffusion. This is thought to be due to the fact that it is steep because there is no . In the embodiment, A supplied externally
As s pressure, 72×1cf! Although the case of TOrr was explained, the M pressure is 20T0rr to 500T0r.
r is the mobility, carrier concentration distribution FET (7) N. It was good in terms of F.
Ｍ圧が２０ｒ０ｒｒ以下では、砒素空孔によると思われ
るキャリヤ濃度の減少、Ｎ．Ｆの増大及び熱処理治具に
門用いた多結晶ＧａＡｓの損壊が見られた。又Ｍ圧が５
００Ｔ０ｒｒ以上では、砒素圧過剰によりＧａ空孔の発
生によると思われるキャリヤ濃度の異常拡散、移動度の
減少、ＦＥＴを製作した場合にＮ．Ｆの増大をきたした
。ｊ 実施例では、基板としてＧａＡｓで説明したが、
他の化合物半導体、例えばＧａＰ，ＧａＡｓｌ−ＸＰｘ
，ＧａＸＡｅｌ−Ｘ，ＡｓｙＰｌ−ｙ等にも用いられる
。When the M pressure is below 20r0rr, the carrier concentration decreases, which is thought to be due to arsenic vacancies, and the N. An increase in F and damage to the polycrystalline GaAs used in the heat treatment jig were observed. Also, the M pressure is 5
At 00T0rr or more, excessive arsenic pressure causes abnormal diffusion of carrier concentration, which is thought to be caused by the generation of Ga vacancies, decreases in mobility, and N. This resulted in an increase in F. j In the example, GaAs was used as the substrate, but
Other compound semiconductors, such as GaP, GaAsl-XPx
, GaXAel-X, AsyPl-y, etc.
又多結晶ＧａＡｓを治具を用いたがＧａＡｓの粉末、Ｇ
ａ，Ａｓを含有する絶縁物を用いても良い。又外部から
供給するＡｓ圧として、金属砒素を用いたが、アルシン
（ＡｓＨ３）の流量を変化せしめてＡｓ圧を制御しても
良い。以上説明したように本発明は、イオン注入した化
合物半導体の熱処理方法に関するもので、イオン注入し
た化合物半導体を該化合物半導体の構成元素からなる単
結晶、多結晶、粉末或は構成元素を含有する絶縁物等に
設置し、前記イオン注入した化合物半導体の構成元素の
蒸気圧の高い元素の蒸気圧を外部から加えることにより
イオン注入層のイオンの電気活性化率、移動度を向上せ
しめ、キャリヤ濃度の異常拡散を防止し、この方法によ
るイオン注入した基板を用いることで雑音指数を減少せ
しめるものであり、その工業的価値は大である。In addition, polycrystalline GaAs was prepared using a jig, but GaAs powder, G
An insulator containing a, As may also be used. Further, although metallic arsenic is used as the As pressure supplied from the outside, the As pressure may be controlled by changing the flow rate of arsine (AsH3). As explained above, the present invention relates to a method for heat treatment of an ion-implanted compound semiconductor, in which the ion-implanted compound semiconductor is processed into a single crystal, a polycrystal, a powder made of the constituent elements of the compound semiconductor, or an insulator containing the constituent elements. By applying from the outside the vapor pressure of an element with a high vapor pressure among the constituent elements of the ion-implanted compound semiconductor, the electrical activation rate and mobility of ions in the ion-implanted layer are improved, and the carrier concentration is increased. By preventing abnormal diffusion and using a substrate implanted with ions using this method, the noise figure can be reduced, and its industrial value is great.
第１図は従来のＧａＡｓの構成元素からなる雰囲気での
熱処理方法の一例を示す構成図、第２図ａ〜ｃは本発明
の一実施例を示す工程図、第３図は本発明の熱処理方法
で得られるキャリヤ濃度分布図、第４図は本発明ならび
に従来の熱処理方法で得られるキャリヤ濃度分布図であ
る。
５・・・・・・半絶縁情ρＡＡｓ基板、６・・・・・シ
リコンイン、７・・・・・・多結晶ＧａＡｓ治具。Figure 1 is a block diagram showing an example of a conventional heat treatment method in an atmosphere containing constituent elements of GaAs, Figures 2 a to c are process diagrams showing an embodiment of the present invention, and Figure 3 is a heat treatment method of the present invention. FIG. 4 is a carrier concentration distribution map obtained by the present invention and the conventional heat treatment method. 5...Semi-insulating ρAAs substrate, 6...Silicon in, 7...Polycrystalline GaAs jig.
Claims (1)
元素からなる単結晶、多結晶、粉末或は化合物半導体基
板を構成する元素を含む絶縁物に設置し、前記化合物半
導体の構成元素のうち蒸気圧の高い元素の雰囲気を外部
から加えて、前記化合物半導体基板を熱処理することを
特徴とする半導体装置の製造方法。1. A compound semiconductor substrate is placed on a single crystal, polycrystal, powder, or insulator containing the elements constituting the compound semiconductor substrate, and the vapor pressure of the constituent elements of the compound semiconductor is A method for manufacturing a semiconductor device, characterized in that the compound semiconductor substrate is heat-treated by applying an atmosphere containing a high element from the outside.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP54119881A JPS6043658B2 (en) | 1979-09-18 | 1979-09-18 | Manufacturing method of semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP54119881A JPS6043658B2 (en) | 1979-09-18 | 1979-09-18 | Manufacturing method of semiconductor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS5643735A JPS5643735A (en) | 1981-04-22 |
| JPS6043658B2 true JPS6043658B2 (en) | 1985-09-30 |
Family
ID=14772541
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP54119881A Expired JPS6043658B2 (en) | 1979-09-18 | 1979-09-18 | Manufacturing method of semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS6043658B2 (en) |
Families Citing this family (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS60186014A (en) * | 1984-03-06 | 1985-09-21 | Agency Of Ind Science & Technol | Forming method of n type layer on gaas semiconductor substrate |
| JPS61210639A (en) * | 1985-03-15 | 1986-09-18 | Toshiba Corp | Method of improving quality of compound single crystal having volatile component |
Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS54104770A (en) * | 1978-02-03 | 1979-08-17 | Sony Corp | Heat treatment method for 3-5 group compound semiconductor |
-
1979
- 1979-09-18 JP JP54119881A patent/JPS6043658B2/en not_active Expired
Patent Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS54104770A (en) * | 1978-02-03 | 1979-08-17 | Sony Corp | Heat treatment method for 3-5 group compound semiconductor |
Also Published As
| Publication number | Publication date |
|---|---|
| JPS5643735A (en) | 1981-04-22 |
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