KR920004966B1 - Activating method of ion-implanted ga as substrate - Google Patents
Activating method of ion-implanted ga as substrate Download PDFInfo
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- KR920004966B1 KR920004966B1 KR1019880016680A KR880016680A KR920004966B1 KR 920004966 B1 KR920004966 B1 KR 920004966B1 KR 1019880016680 A KR1019880016680 A KR 1019880016680A KR 880016680 A KR880016680 A KR 880016680A KR 920004966 B1 KR920004966 B1 KR 920004966B1
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- gaas substrate
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- 239000000758 substrate Substances 0.000 title claims abstract description 27
- 238000000034 method Methods 0.000 title claims abstract description 26
- 230000003213 activating effect Effects 0.000 title claims abstract description 7
- 229910001218 Gallium arsenide Inorganic materials 0.000 claims abstract description 20
- 239000010409 thin film Substances 0.000 claims abstract description 18
- 238000000151 deposition Methods 0.000 claims abstract description 9
- 229910052721 tungsten Inorganic materials 0.000 claims abstract description 6
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims abstract description 4
- 229910052750 molybdenum Inorganic materials 0.000 claims abstract description 4
- 229910052710 silicon Inorganic materials 0.000 claims abstract description 4
- 239000010703 silicon Substances 0.000 claims abstract description 4
- 229910052751 metal Inorganic materials 0.000 claims description 10
- 239000002184 metal Substances 0.000 claims description 10
- 150000002500 ions Chemical class 0.000 claims description 9
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 claims description 5
- 239000010937 tungsten Substances 0.000 claims description 5
- 229910004298 SiO 2 Inorganic materials 0.000 claims description 4
- 238000005468 ion implantation Methods 0.000 claims description 4
- 238000000427 thin-film deposition Methods 0.000 claims description 4
- ZOKXTWBITQBERF-UHFFFAOYSA-N Molybdenum Chemical compound [Mo] ZOKXTWBITQBERF-UHFFFAOYSA-N 0.000 claims description 3
- 239000011733 molybdenum Substances 0.000 claims description 3
- 239000010408 film Substances 0.000 abstract description 8
- 230000008021 deposition Effects 0.000 abstract description 4
- 239000004065 semiconductor Substances 0.000 abstract description 2
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 abstract 2
- 229910052581 Si3N4 Inorganic materials 0.000 abstract 1
- 238000005234 chemical deposition Methods 0.000 abstract 1
- 229910052681 coesite Inorganic materials 0.000 abstract 1
- 229910052906 cristobalite Inorganic materials 0.000 abstract 1
- 239000000377 silicon dioxide Substances 0.000 abstract 1
- 235000012239 silicon dioxide Nutrition 0.000 abstract 1
- 229910052682 stishovite Inorganic materials 0.000 abstract 1
- 229910052905 tridymite Inorganic materials 0.000 abstract 1
- 238000001994 activation Methods 0.000 description 8
- 238000010586 diagram Methods 0.000 description 6
- 230000004913 activation Effects 0.000 description 4
- 238000005229 chemical vapour deposition Methods 0.000 description 4
- 238000004544 sputter deposition Methods 0.000 description 3
- 230000001133 acceleration Effects 0.000 description 2
- RBFQJDQYXXHULB-UHFFFAOYSA-N arsane Chemical compound [AsH3] RBFQJDQYXXHULB-UHFFFAOYSA-N 0.000 description 2
- 239000011261 inert gas Substances 0.000 description 2
- 238000001465 metallisation Methods 0.000 description 2
- 238000007789 sealing Methods 0.000 description 2
- 238000007796 conventional method Methods 0.000 description 1
- 238000009792 diffusion process Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 239000007789 gas Substances 0.000 description 1
- 238000001659 ion-beam spectroscopy Methods 0.000 description 1
- 238000010884 ion-beam technique Methods 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/26—Bombardment with radiation
- H01L21/263—Bombardment with radiation with high-energy radiation
- H01L21/265—Bombardment with radiation with high-energy radiation producing ion implantation
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- Physics & Mathematics (AREA)
- Engineering & Computer Science (AREA)
- High Energy & Nuclear Physics (AREA)
- General Physics & Mathematics (AREA)
- Toxicology (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- Health & Medical Sciences (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Formation Of Insulating Films (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
- Physical Vapour Deposition (AREA)
Abstract
Description
제 1a 도는 실리콘 이온 주입 공정도.1a or silicon ion implantation process diagram.
제 1b 도는 유전체 박막 증착 공정도.FIG. 1B is a process diagram of dielectric thin film deposition.
제 1c 도는 내열성 금속 증착후의 활성화 공정도.Figure 1c or activation process diagram after heat resistant metal deposition.
* 도면의 주요부분에 대한 부호의 설명* Explanation of symbols for main parts of the drawings
1 : 반절연 GaAs 기판 2 : n이온 주입층1: semi-insulating GaAs substrate 2: n-ion implanted layer
3 : 유전체 박막 4 : 금속박막3: dielectric thin film 4: metal thin film
본 발명은 GaAs 반도체 소자 제조시의 활성층 형성에 사용되는 활성화 공정에 관한 것이다.The present invention relates to an activation process used for forming an active layer in the manufacture of GaAs semiconductor devices.
종래에 개발된 이온 주입 GaAs 기판의 활성화 방법을 살펴보면, 크게 세종류로 구분할 수 있다. 첫째는 GaAs 기판과 열팽창 계수가 유사한 유전체 박막을 이온 주입된 GaAs 기판위에 증착한 후 불활성 가스 분위기에서 활성화시키는 방법이며, 둘째는 이온 주입된 GaAs 기판 표면에 반절연 GaAs 기판이나, 같은 조건으로 이온 주입된 GaAs 기판을 맞대어 불활성 가스 분위기에서 활성화시키며 셋째는 휘발하기 쉬운 As원소를 보충하기 위하여 밀봉막 없이 AsH3, H2의 과압(Over - pressure)에서 활성화 하는 방법이 있다. 이러한 활성화 방법을 살펴보면 첫째 방법은 GaAs 기판과 열팽창 계수가 비슷하고 밀도가 높은 박막을 선택한 후 계면 스트레스를 줄이기 위해 막의 두께를 1000Å 이하로 제한하게 된다.Looking at the activation method of the conventionally implanted ion implanted GaAs substrate can be classified into three types. First, a dielectric thin film having a similar thermal expansion coefficient to a GaAs substrate is deposited on an ion implanted GaAs substrate and then activated in an inert gas atmosphere. Second, a semi-insulated GaAs substrate is implanted on an ion implanted GaAs substrate surface under the same conditions. The GaAs substrate is then activated in an inert gas atmosphere, and the third method is to activate it at the over-pressure of AsH 3 and H 2 without a sealing film to compensate for As element, which is easily volatilized. In the activation method, the first method selects a thin film having a similar thermal expansion coefficient and high density to the GaAs substrate, and then limits the film thickness to 1000 Å or less in order to reduce interfacial stress.
이러한 방법은 각 박막마다 스트레스에 따른 최대 증착막의 두께가 제한되고 스트레스에 의한 활성화율 및 이동도의 효율이 저하하게 된다. 두번째 방법은 맞대어진 GaAs 기판으로부터 휘발되는 성분을 보충하고자 하는 의도이나, 그 효과가 확실하지 않고 양측면과 뒷면을 통하여 As 원자가 휘발되는 단점이 있다. 세번째 방법은 현재 많이 사용되고 있는 방법이나, 공정 조건이 까다롭고 아르신(Arsine : AsH3) 가스를 사용함으로 위험하며, 공정의 재현성이 불확실하다.In this method, the thickness of the maximum deposited film is limited for each thin film and the efficiency of activation and mobility due to stress is reduced. The second method is intended to replenish the volatilized components from the butted GaAs substrate, but its effect is not certain and the As atoms are volatilized through both sides and the back side. The third method is currently widely used, but the process conditions are difficult, and it is dangerous to use Arsine (Arsine: AsH 3 ) gas, and the reproducibility of the process is uncertain.
본 발명의 목적은 상기의 문제점을 해결하기 위한 이온 주입된 GaAs 기판의 활성화 방법을 제공하는데 있으며, 그 방법으로서 상기 첫번째 방법을 보완하여 다음과 같이 구성하였다. 첫째 종래의 방법에서는 As 원자의 휘발을 방지하기 위하여 일정 두께 이상의 밀봉막을 증착하였으나, 이로 인한 계면의 스트레스로 인하여 좋은 활성화 결과를 얻지 못하였으나, 본 발명에서는 유전체 박막이 GaAs 기판과 내열성 금속 사이의 반응을 저지키 위한 완충막 역할을 하도록 하여 그 두께를 100-500Å 정도로 얇게 할 수 있어 유전체막에 의한 계면 스트레스를 최소화할 수 있어서, 기판 손상을 최소화 하게 된다. 둘째 유전체 박막에 의해 휘발성 As 원자의 외부확산(out diffusion)을 일차 저지할 수 있으며, 이차로 증착된 치밀한 내열성 금속 박막에 의해 외부확산이 완전히 저지되게 된다.SUMMARY OF THE INVENTION An object of the present invention is to provide a method of activating an ion implanted GaAs substrate to solve the above problems. First, in the conventional method, a sealing film having a predetermined thickness or more is deposited to prevent volatilization of As atoms, but due to the stress at the interface, good activation results are not obtained. In the present invention, the dielectric thin film reacts between the GaAs substrate and the heat resistant metal. By acting as a buffer to prevent the thickness of the thickness can be reduced to about 100-500Å to minimize the interfacial stress caused by the dielectric film, thereby minimizing substrate damage. Second, the first thin film can prevent out-diffusion of volatile As atoms, and the second diffuse thin film is completely prevented from being diffused by the dense heat-resistant metal thin film.
이하 첨부된 도면을 참조하여 본 발명을 상세히 설명하기로 한다. 제 1a 도는 실리콘 이온 주입 공정도이고, 제 1b 도는 유전체 박막 증착 공정도이고, 제 1c 도는 내열성 금속 증착후의 활성화 공정도이며, 도면에서 1은 반절연 GaAs 기판을, 2는 n 이온 주입층을, 3은 유전체 박막을, 4는 금속박막을 각각 나타낸다.Hereinafter, the present invention will be described in detail with reference to the accompanying drawings. 1a is a silicon ion implantation process diagram, FIG. 1b is a dielectric thin film deposition process diagram, and FIG. 1c is an activation process diagram after heat-resistant metal deposition, in which 1 is a semi-insulating GaAs substrate, 2 is an ion implantation layer, and 3 is a dielectric. A thin film and 4 are metal thin films, respectively.
제 1 공정(제 1a 도)에서는 반절연 (S. I.) GaAs 기판(1)＋Si이온을 70-120KeV, 1012-1013atmos/com2의 조건으로 이온 주입한다. 제 2 공정(제 1b 도)에서는 상기 이온 주입된 기판상에 화학 증착이나 스퍼터링 방법에 의해 SiO2또는 Si3N4막(3)을 100-500Å 두께로 증착한다. 이때 플라즈마 화학 증착에 의한 SiO2나 Si3N4의 증착조건은 압력 0.5-1Torr, SiH450-100SCCM, N2O 또는 NH3300-700SCCM, 기판온도는 350-450℃ RF 전력은 100-200W이며, 이온빔에 의한 스퍼터링 공정조건은 압력 10-5-10-4Toor , Ar 7-12SCCM, 가속전압 125-500eV이다. 제 3 공정 (제 1c 도)에서는 상기 유전체 박막상에 화학증착 또는 스퍼터링 방법에 의해 내열성 금속인 텅스텐(W) 또는 몰리브덴 (Mo)을 100-500Å 두께로 증착한다. 이때의 화학증착에 의한 텅스텐의 증착 조건은 압력 0.2-1Torr, WF62-5SCCM, SiH4100-500SCCM, Ar 800-1200SCCM, 기판온도는 350℃-450℃이며, 이온빔 스퍼터링에 의한 텅스텐, 몰리브덴의 증착조건은 압력 10-5-10-4Too, Ar 7-12SCCM, 가속전압 125-500eV이다. 제 4 공정은 800-950℃ 온도범위에서 20-30분 동안 활성화하는 공정이다.In the first step (Fig. 1A), semi-insulated (SI)
상기와 같이 본 발명은 반절연 GaAs의 활성화 공정을 위해 GaAs 기판상에 유전체 박막과 금속막을 증착시킴으로써 계면의 스트레스를 최소화하여 기판손상을 최소화하고, As의 휘발을 완전히 저지할 수 있는 유용한 발명이다.As described above, the present invention is a useful invention capable of minimizing substrate damage by minimizing stress at an interface by depositing a dielectric thin film and a metal film on a GaAs substrate for an activation process of semi-insulated GaAs, and completely preventing volatilization of As.
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Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1019880016680A KR920004966B1 (en) | 1988-12-14 | 1988-12-14 | Activating method of ion-implanted ga as substrate |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1019880016680A KR920004966B1 (en) | 1988-12-14 | 1988-12-14 | Activating method of ion-implanted ga as substrate |
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| Publication Number | Publication Date |
|---|---|
| KR900010907A KR900010907A (en) | 1990-07-11 |
| KR920004966B1 true KR920004966B1 (en) | 1992-06-22 |
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| Application Number | Title | Priority Date | Filing Date |
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| KR1019880016680A KR920004966B1 (en) | 1988-12-14 | 1988-12-14 | Activating method of ion-implanted ga as substrate |
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| KR900010907A (en) | 1990-07-11 |
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