KR920007193B1 - Anealing method of semiconductor elements - Google Patents

Anealing method of semiconductor elements Download PDF

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KR920007193B1
KR920007193B1 KR1019850009649A KR850009649A KR920007193B1 KR 920007193 B1 KR920007193 B1 KR 920007193B1 KR 1019850009649 A KR1019850009649 A KR 1019850009649A KR 850009649 A KR850009649 A KR 850009649A KR 920007193 B1 KR920007193 B1 KR 920007193B1
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annealing
substrate
ion implantation
ion
implantation layer
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KR1019850009649A
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KR870006635A (en
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유상전
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금성일렉트론주식회사
문정환
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/324—Thermal treatment for modifying the properties of semiconductor bodies, e.g. annealing, sintering

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  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
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Abstract

In annealing of substrate which has an ion-implanted layer during fabrication process of compound semiconductor, the annealing method is characterized by annealing two ion-implanted substrates faced each other in high temperature resistance vessel which is charged with argon gas at high pressure. In this method, the annealing temperature can be 800-900 deg.C, and it can be annealed directly after ion implatation without coating of protection layer. It has advantages of low manufcturing cost and production of high quality semiconductor devices.

Description

반도체 소자의 어닐링 방법Annealing Method of Semiconductor Devices

제1도는 본 발명이 실시되는 어닐링 장치의 구성을 보인 개략 단면도.1 is a schematic cross-sectional view showing the configuration of an annealing apparatus according to the present invention.

제2도는 이온 주입층이 형성된 기판들을 대향되게 부착한 상태를 보인 단면도.2 is a cross-sectional view showing a state in which the substrates on which the ion implantation layer is formed are attached to face each other.

본 발명은 이온 주입층이 형성된 반도체의 어닐링 방법에 관한 것으로, 특히 이온주입층이 형성된 기판을 불활성 가스 분위기가 유지되는 반응로의 내부에 상호 겹친 상태로 장입하고 어닐링하여 기판 및 이온주입층의 화학적 구성원소의 조성이 양호하게 유지되게 한 어닐링 방법에 관한 것이다.The present invention relates to an annealing method of a semiconductor in which an ion implantation layer is formed, and in particular, the substrate and the ion implantation layer are chemically charged by charging and annealing the substrate on which the ion implantation layer is formed in an overlapping state in a reactor maintained in an inert gas atmosphere. It relates to an annealing method by which the composition of the member elements is kept well.

일반적으로 화합물 반도체를 이용한 반도체소자 가공공정 중 기판에 원하는 불순물을 주입하는 방법으로는 통상 이온 주입법이 사용되는 바, 이온주입법에 의하여 이온주입이 된 기판은 결정구조가 파괴되기 때문에 어닐링(Annealing) 공정에 의하여 파괴된 결정을 재결정화시키고 있다.In general, an ion implantation method is commonly used to inject desired impurities into a substrate during a semiconductor device processing process using a compound semiconductor, and an annealing process is performed because the crystal structure of the substrate implanted by the ion implantation method is destroyed. The crystals destroyed by the crystallization are recrystallized.

종래에는 이와같이 반도체 소자 가공공정중에 이온 주입이 된 화합물 기판을 어닐링하기 위하여 기판위에 산화규소(SiO2), 질화규소(Si3N4), 산화알루미늄(Al2O3)등의 보호박막을 화학증착법으로 코팅한 후, 소정의 온도(약 800-1000℃)에서 가열하여 어닐링을 행하고, 기판위에 코팅되어 있던 보호박막을 제거함으로써, 어닐링중에 고온으로 인하여 증가화하는 기판과 이온주입층의 구성원소들이 기판 외부로 확산되는 현상을 방지하도록 하였다.Conventionally, in order to anneal a compound substrate implanted with ions during the semiconductor device processing process, a protective thin film such as silicon oxide (SiO 2 ), silicon nitride (Si 3 N 4 ), or aluminum oxide (Al 2 O 3 ) is chemically deposited on the substrate. After coating, the annealing is performed by heating at a predetermined temperature (about 800-1000 ° C.), and by removing the protective thin film coated on the substrate, the components of the substrate and the ion implantation layer that increase due to the high temperature during the annealing The phenomenon of diffusion to the outside of the substrate was prevented.

그러나, 이러한 종래의 어닐링 기술은 어닐링 도중에 기판 및 이온주입층의 구성원소들이 상당량 보호막으로 확산되어 들어가기 때문에 어닐링 후에 기판 및 이온주입층의 구성원소 비율이 어닐링 이전과 달라지게 되어 양질의 반도체소자를 제조하지 못하는 결점이 있었다.However, in the conventional annealing technique, since the elements of the substrate and the ion implantation layer are diffused into the protective film during the annealing, the ratio of the elements of the substrate and the ion implantation layer after the annealing is different from that before the annealing, thereby producing a high quality semiconductor device. There was a flaw not to do.

본 발명은 이와같은 종래기술의 결함을 해소하기 위하여 창안한 것으로, 이온주입된 두장의 기판을 서로 마주보게 겹친 상태로 고압의 불활성 알곤가스 분위기가 유지되는 반응로에 장입하여 어닐링을 실시함으로써, 어닐링중에 기판과 이온 주입층의 구성원소들의 외부로 확산되는 현상을 방지할 수 있게 한 것인 바, 이와같은 본 발명을 첨부한 예시도면에 의하여 상세히 설명하면 다음과 같다.The present invention was devised to solve such a deficiency of the prior art, and annealing was carried out by charging an ion-injected two substrates into a reactor in which a high-pressure inert argon gas atmosphere was maintained while overlapping each other. It will be able to prevent the phenomenon of diffusion to the outside of the elements of the substrate and the ion implantation layer in the middle, as described in detail by the accompanying drawings of the present invention as follows.

제1도는 본 고안에 사용되는 어닐링 장치를 보인 개략도로서, 어닐링로(爐)의 본체(1) 외주면에는 가열수단(2)이 구비되고 본체(1)의 일측에는 공급통(3)에서 불활성인 알곤가스가 유입되는 유입구(4)가 형성되며, 타측에는 가스 배출구(5)가 구비되고 본체(1)의 내부에는 소재이송용 보우트(6)가 설치되어 있다.1 is a schematic view showing an annealing apparatus used in the present invention, the heating means (2) is provided on the outer peripheral surface of the main body 1 of the annealing furnace and the inert side of the main body (1) in the supply cylinder (3) An inlet 4 through which argon gas flows is formed, and a gas outlet 5 is provided at the other side, and a boat 6 for material transfer is installed inside the main body 1.

이와같은 어닐링로의 본체(1) 내부의 이송용 보우트(6) 위에는 열처리할 소재, 즉 제2도에 도시한 바와 같이 이온주입층(7)이 형성된 화합물 반도체 기판(8)을 서로 마주보게 겹친 상태로 일정간격을 두고 배열 장입한 후, 본체(1) 내부에 고압의 알곤가스 분위기를 유지시킴과 아울러 800-900℃의 고온을 유지하여 이온주입층(7)이 형성된 반도체기판(8)을 어닐링하게 되면, 기판(8)의 구성원소(예를들어 기판 재질이 GaAs인 경우에는 Ga 및 As)와 이온주입층(7)의 구성원소(Ge, Sn 등)들은 상기한 바와같은 어닐링 과정중 기판(8) 밖으로 증기화되어 나오고 이 증기화된 원소들은 위의 기판(8)으로 확산해 들어가며, 위의 기판(8)에서도 증기화되어 나온 원소들이 아래의 기판(8)으로 확산해 들어가므로 결국은 거의 같은 량의 원소를 위, 아래 기판(8)이 주고 받게 되어 어닐링 실시전과 후의 기판(8)내 원소 농도가 거의 동일하게 유지된다.On the transfer boat 6 inside the main body 1 of the annealing furnace, the compound semiconductor substrate 8 on which the material to be heat-treated, that is, the ion implantation layer 7 is formed as shown in FIG. After the array is charged at a predetermined interval in a state, the semiconductor substrate 8 having the ion implantation layer 7 formed thereon is maintained by maintaining a high-pressure argon gas atmosphere inside the main body 1 and maintaining a high temperature of 800-900 ° C. When annealed, the elements of the substrate 8 (eg Ga and As when the substrate material is GaAs) and the elements (Ge, Sn, etc.) of the ion implantation layer 7 are subjected to the annealing process as described above. Vaporized out of the substrate 8 and these vaporized elements diffuse into the upper substrate 8, and vaporized elements in the upper substrate 8 diffuse into the lower substrate 8 Eventually, the upper and lower substrates 8 exchange approximately the same amount of elements. The element concentration in the substrate 8 before and after the niling is kept almost the same.

이와같은 작업중에 두장의 기판(8)이 약간 떨어져 있는 경우에도 기판(8)의 재결정화 과정이 고압의 불활성 가스가 유지되는 반응로내에서 이루어지므로 증기화되어 나온 원자들이 밖으로 새어나가지 못하고 두장의 기판(8) 사이에 갇혀있다가 다시 양측 기판(8) 내로 확산해 들어가게 된다. 상기의 작업중 두장 기판(8)은 가능한대로 가깝게 겹치는게 좋다.Even when the two substrates 8 are slightly separated during this operation, the recrystallization process of the substrate 8 takes place in a reactor in which a high-pressure inert gas is maintained, so that vaporized atoms cannot leak out. It is trapped between the substrates 8 and then diffuses back into both substrates 8. During the above operation, the two substrates 8 should overlap as closely as possible.

상기한 바와같은 본 발명은 화합물 반도체의 이온주입 후 어닐링 공정에서 기판위에 보호막을 코팅하지 않고 바로 어닐링할 수 있으므로 보호막을 코팅하는 공정이 생략되어 제조원가가 절감될 뿐 아니라, 고온의 어닐링 과정에서 기판과 이온주입층의 구성원소들이 외부로 확산되는 현상이 방지되어 어닐링 전·후의 화학적 조성이 동일하게 되므로 양질의 반도체 소자를 제조하는 이점이 있다.The present invention as described above can be annealed directly without coating the protective film on the substrate in the annealing process after the ion implantation of the compound semiconductor, so that the process of coating the protective film is omitted, not only to reduce the manufacturing cost, but also with the substrate in the high temperature annealing process Since phenomena of constituent elements of the ion implantation layer are prevented from diffusing to the outside, the chemical composition before and after annealing is the same, thereby producing a high quality semiconductor device.

Claims (1)

화합물 반도체의 제조공정중 이온주입후에 이온주입층이 형성된 기판을 어닐링함에 있어서, 이온주입층이 형성된 두장의 기판을 서로 마주보게 겹친 상태로 불활성 알곤가스가 고압으로 충전되는 고온용기에 넣고 어닐링 함을 특징으로 하는 반도체 소자의 어닐링 방법.In the annealing of the substrate on which the ion implantation layer is formed after ion implantation during the compound semiconductor manufacturing process, the two substrates on which the ion implantation layer is formed are placed in a high-temperature container filled with a high-pressure inert argon gas at high pressure in a state where they overlap each other. An annealing method of a semiconductor device characterized by the above-mentioned.
KR1019850009649A 1985-12-20 1985-12-20 Anealing method of semiconductor elements KR920007193B1 (en)

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KR920007193B1 true KR920007193B1 (en) 1992-08-27

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