JPS61106500A - Method for annealing compound semiconductor substrate - Google Patents

Abstract

PURPOSE:To prevent scattering of a component element having high vapor pressure and to anneal uniformly by forming a protective film on a surface to be annealed, and giving the vapor pressure of the component element having high vapor pressure from the outside. CONSTITUTION:A protective film is provided on the surface of a compd. semiconductor substrate to be annealed. Then the vapor pressure of the element which is one of the component elements of said compd. semiconductor and having higher vapor pressure is supplied to the atmosphere. Annealing is carried out in said atmosphere. Accordingly, the scattering of the component element having high vapor pressure is prevented and the compd. semiconductor is uniformly annealed.

Description

DETAILED DESCRIPTION OF THE INVENTION [Industrial Application Field] The present invention relates to a method for improving compound semiconductors, and more particularly to an annealing method for compound semiconductors. The method of the invention can be advantageously applied to compound semiconductor and mixed crystal semiconductor substrates and devices.

[Conventional technology]

Ion implantation into compound semiconductors (when forming an active layer, it is necessary to perform heat treatment at a temperature of 800 to 1000°C for the purpose of recovering from implantation damage and activating the implanted ions), this is called annealing. In addition, in compound semiconductors, constituent elements with high vapor pressure, such as GaAa,
P for engineering nP, F for Zn %0dTs for Zn8
In order to prevent iaa etc. from scattering, ■81
0! , 8 is 14 or MutM to cover the semiconductor, and (2) preparing an atmosphere to which the vapor pressure of the constituent elements is applied.

[Problems to be Solved by the Invention] However, the above conventional methods (1) and (2) have the following disadvantages.

First, in the case of method (2) for forming a protective film, there is a problem of non-uniform annealing due to non-uniformity of the thickness and quality of the protective film in the plane, and furthermore, there is a problem of non-uniformity of annealing due to non-uniformity of the thickness and quality of the protective film within the surface. Due to thermal stress caused by differences in thermal expansion coefficients, a drawback is the problem of thermal bit generation in which semiconductor constituent elements with high vapor pressure scatter through the holding film during annealing.

Next, in the case of method (2) where an atmosphere is created where the vapor pressure of the constituent elements is applied, even if a uniform vapor pressure can be applied, dislocations that are unevenly distributed within the substrate will cause unevenness in the vicinity of the dislocations. There are drawbacks that scattering of the constituent elements occurs, and that the history of the effective applied vapor pressure has an in-plane distribution due to the in-plane non-uniformity of the cooling rate after annealing.

In view of the current situation as described above, an object of the present invention is to provide a method that eliminates the drawbacks of the conventional method and can realize uniform annealing.

[Means for solving problems]

The present inventors have discovered that by using both of the above methods (1) and (2) in combination, the drawbacks of each annealing method can be compensated for and uniform annealing can be achieved.

That is, in the present invention, in annealing a compound semiconductor substrate, a protective film is provided on at least the surface to be annealed, and the vapor pressure of the element having a higher vapor pressure among the constituent elements of the compound semiconductor is supplied. This is a compound semiconductor annealing method characterized by performing annealing in an atmosphere.

The annealing method of the present invention will be explained in detail below.

In the method of the present invention, 5101.
After forming a protective film such as 813 m, AtM, etc., annealing is performed in a concave atmosphere in which the vapor pressure of the constituent elements with high vapor pressure is applied, and it can be performed by either the closed tube method or the open tube method. good.

As the protective film for the method of the present invention, for example, 810. ．． 8 i
The protective film is formed by AVN (chemical vapor deposition), plasma OVD, or sputtering, and the thickness of the protective film is 1000 mm. ~2000X is sufficient.

FIG. 1 is a diagram illustrating a schematic configuration and a relationship between set temperatures corresponding to each portion when annealing is performed by a closed tube method according to the method of the present invention.

In the figure, 1 is the compound semiconductor substrate, 2 is the protective film, the single element with the higher vapor pressure of the compound semiconductor of the 3 samples is for vapor application, 4 is the saturated vapor pressure from the simple element 3, and the sFi protective film 2, a quartz tube in which a compound semiconductor substrate 1 and a simple element 3 are vacuum-sealed, a 6Fi reaction tube, and 7 a heater.

6'I'd temperature is shown, T1 is the saturated vapor pressure setting temperature of the element 3 for applying vapor pressure, and T2 is the annealing temperature.

In this method, a quartz tube that has been thoroughly cleaned, hydrofluoric acid etched, and degassed is loaded with a cleaned high vapor pressure element and a compound semiconductor sample with a protective film formed, and then heated to ~10-' Torr. After evacuating, seal the opening with oxyhydrogen flame. Next, the tube is inserted into a furnace with a temperature distribution of TI and T2 in advance and annealed for a predetermined period of time, after which it is taken out and cooled naturally or thrown into water for quenching. This method allows the applied vapor pressure to be clearly defined.

FIG. 2 is an explanatory diagram showing the case of annealing using the open tube method according to the method of the present invention, similar to FIG. 1, and 1.2.6 and 7 in the figure mean Similar to Figure 1, reference numeral 8 indicates a flow of gas for applying vapor pressure containing the element with the higher vapor pressure of the sample semiconductor. In this case, temperature T8 is both the annealing temperature and the decomposition temperature of D.

In this method, there is no need to enclose a sample in a quartz tube, but instead a gas containing a high vapor pressure constituent element is thermally divided by Kfi in a furnace to obtain the vapor pressure of the element. First, the prepared compound semiconductor sample with a protective film was set in the low temperature section of the inlet of a furnace kept at a temperature T8, and the gas f consisting of the high vapor pressure element:
Pour the sink, then sample! Move to section for annealing. After finishing, return to the low temperature section to cool. In this method, the applied vapor pressure is determined to be 1! No, but it saves the trouble of sealing it in a quartz tube.

T for both open tube method and closed tube method, temperature (annealing temperature #) is 8
The temperature is about 00 to 900°C. T1 in the closed tube method is T
It is arbitrarily set within a range where t<Tt and the vapor pressure of the high vapor pressure element does not lead to destruction of the quartz tube.

The features of the method of the present invention are as follows: i) By employing an image retention film,
11) Vapor pressure of constituent elements with high vapor pressure 1 As shown in Fig. 1 or 2, the dislocation-dependent dislocation-dependent constituent elements can be prevented from dispersing non-uniformly in the substrate. 1IH) By using a protective film, it is possible to suppress the scattering of the element through the film and the generation of thermal pits due to unevenness of the protective film and thermal stress between the protective film and the substrate. , it is possible to alleviate the distribution of the cooling history that occurs within the wafer surface due to the applied vapor pressure during cooling, and therefore it is possible to anneal the compound semiconductor uniformly within the wafer surface and without scattering of constituent elements with high vapor pressure. .

In the above description, the protective film was formed on one surface of the compound semiconductor substrate to show the proportionality, but it may be formed only on the surface to be annealed, or may be formed on both surfaces. moreover,
Same type of compound semiconductor substrate ft on which same type of protective film is formed
It is also possible to perform annealing by installing two sheets so that the surfaces on which the protective films are formed overlap each other (if the protective films are formed on both sides, the surfaces to be annealed overlap each other).

〔Example〕

As an experimental example, the present annealing method was compared with the conventional method by implanting 81 ions into a semi-insulating Ga 8 substrate to form a FIlfT and measuring the in-plane distribution of threshold voltage.

The Ga, Aa substrate used was
2′φ eye-doped G by the Ozochralski) method
Six wafers were cut adjacent to each other from the center of an aAs (001) crystal, and mirror-polished wafers were used. 3 pieces 1. B1゜01 is IF I T (Field ef
2. It was used for electrical evaluation of the B2,02Fi ion-implanted layer.

Ion implantation process/annealing conditions Active layer ion implantation conditions: Common.

Annealing conditions are shown in Table 1.

Table 1 FBTO Tazo source/drain electrode Au-Ge-Ni alloy 400℃
5 minutes processing Gate electrode Electrical characteristics evaluation of Ti/Au overlapping vapor deposited injection layer 2. A 5-square chip was cut out from the wafer by the arm-opening method, and mu-Go-Ni alloy electrodes were formed on the four corners of the van.
The sheet carrier density and carrier mobility were measured by the der Pauw method. Table 2 shows the measurement results of the electrical characteristics of the injection layer.

Table 2 Discrepancies in 20 samples within 0 B2 → C2 → A
The sheet carrier density increases in the order of No. 2, and the mobility also increases. This shows that by applying pressure with a protective film, the activation rate of carriers is increased and the generation of acceptors due to scattering of particles is suppressed.

In addition, the degree of variation indicating uniformity is the smallest in Mu2,
I can see that it is excellent.

Measurement of threshold voltage distribution of FICT The threshold voltage "th" for 30,000 to 40,000 F'ETs was measured on the entire surface of the wafer using a computer-driven automatic measuring device, and the results shown in Table 3 were obtained.

Table 3 Naori th is the average value, 6 vth is the standard deviation, B1-4
In the order of 01-4AI, vth shifts to the on side and the activation becomes larger. This also coincides with the increasing trend of sheet carrier density shown in 5. On the other hand, it can be seen that the variation, that is, the ratio of 6 vth to the logical amplitude, is the smallest in M1, and that the in-plane uniformity is improved.

Therefore, from the above experimental results, it can be seen that the annealing method according to the present invention is extremely effective for uniform annealing. This is a synergistically greater effect than expected from the effects obtained with each of the conventional methods.

[Effects of the Invention] The method of the present invention compensates for the drawbacks of the conventional methods, and enables uniform annealing of compound semiconductors without scattering of constituent elements with high vapor pressure.

[Brief explanation of drawings]

Figures 1 and 2 are diagrams explaining the configuration of an embodiment of the annealing method of the present invention and temperature settings corresponding to each position of the annealing furnace. Figure 1 is for the closed tube method, and Figure 2 is for the open tube method. This is the case with the law. 7:-J door horizontal axis direction value l Annealing furnace horizontal axis direction 61 P. Continuation of the correction book December 72, 1982

Claims (2)

[Claims] (1) In annealing a compound semiconductor substrate, a protective film is provided on at least the surface to be annealed, and the substrate is placed in an atmosphere supplied with the vapor pressure of the element with the higher vapor pressure among the constituent elements of the compound semiconductor. An annealing method for compound semiconductors characterized by performing annealing using (2) For each of the two compound semiconductor substrates of the same type to be annealed, provide a protective film of the same type on at least the surface to be annealed, and attach the two compound semiconductor substrates so that the surfaces to be annealed are on the outside. The method according to claim 1, wherein the semiconductor substrates are stacked and annealed.