JPS6134949A - Heat treatment for compound semiconductor substrate - Google Patents
Heat treatment for compound semiconductor substrateInfo
- Publication number
- JPS6134949A JPS6134949A JP59156094A JP15609484A JPS6134949A JP S6134949 A JPS6134949 A JP S6134949A JP 59156094 A JP59156094 A JP 59156094A JP 15609484 A JP15609484 A JP 15609484A JP S6134949 A JPS6134949 A JP S6134949A
- Authority
- JP
- Japan
- Prior art keywords
- substrate
- compound semiconductor
- protective film
- semiconductor substrate
- dielectric protective
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 239000000758 substrate Substances 0.000 title claims abstract description 94
- 239000004065 semiconductor Substances 0.000 title claims abstract description 48
- 150000001875 compounds Chemical class 0.000 title claims abstract description 46
- 238000010438 heat treatment Methods 0.000 title claims abstract description 19
- 230000001681 protective effect Effects 0.000 claims abstract description 28
- 238000000034 method Methods 0.000 claims abstract description 16
- 239000013078 crystal Substances 0.000 claims abstract description 12
- 239000012535 impurity Substances 0.000 claims abstract description 6
- 230000008018 melting Effects 0.000 claims abstract description 6
- 238000002844 melting Methods 0.000 claims abstract description 6
- 238000000265 homogenisation Methods 0.000 claims description 3
- 229910001218 Gallium arsenide Inorganic materials 0.000 abstract description 28
- 239000000470 constituent Substances 0.000 abstract description 17
- 230000008020 evaporation Effects 0.000 abstract description 17
- 238000001704 evaporation Methods 0.000 abstract description 17
- 230000003247 decreasing effect Effects 0.000 abstract 1
- 239000006185 dispersion Substances 0.000 abstract 1
- 238000000137 annealing Methods 0.000 description 7
- 235000012431 wafers Nutrition 0.000 description 6
- 238000004020 luminiscence type Methods 0.000 description 4
- 239000007789 gas Substances 0.000 description 3
- 229910052581 Si3N4 Inorganic materials 0.000 description 2
- 238000005136 cathodoluminescence Methods 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- 239000000463 material Substances 0.000 description 2
- 101100215641 Aeromonas salmonicida ash3 gene Proteins 0.000 description 1
- BLRPTPMANUNPDV-UHFFFAOYSA-N Silane Chemical compound [SiH4] BLRPTPMANUNPDV-UHFFFAOYSA-N 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000010894 electron beam technology Methods 0.000 description 1
- 238000005468 ion implantation Methods 0.000 description 1
- 230000007774 longterm Effects 0.000 description 1
- 239000007787 solid Substances 0.000 description 1
- 230000003746 surface roughness Effects 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/324—Thermal treatment for modifying the properties of semiconductor bodies, e.g. annealing, sintering
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Formation Of Insulating Films (AREA)
Abstract
Description
【発明の詳細な説明】 ０）発明の属する技術分野 本発明は化合物半導体基板の熱処理方法に関する。[Detailed description of the invention] 0) Technical field to which the invention belongs The present invention relates to a method for heat treating a compound semiconductor substrate.
（ロ）従来技術とその′問題点
化合物半導体基板の電気的性質の均一化をはかるための
熱処理として長時間アニールが行なわれる。この場合、
化合物半導体基板の蒸気圧の高い一部構成元素の蒸発を
抑制するため化合物半導体基板をＳｉ３Ｎ４ のよう
な誘電体保護膜で表面を被覆するか、あるいは保護膜を
用いない方法の場合には雰囲気制御を行なって、ＧａＡ
ｓ半導体基板の場合で７００〜１２００℃にて数十時間
にわたりアニールが行なわれていた、
しかしながら上記従来の方法では誘電体保護膜が長時間
のアニールに耐えられず、ひび、破れ、穴などを生じて
しまい、これらを通じて化合物半導体基板の蒸気圧の高
い一部構成元素の大量の蒸発が生じていた。しかもこの
蒸発は不均一に生ずるため化合物半導体基板の電気的特
性が基板面内で不均一になってしまうという不具合を生
じていた。また雰囲気制御法の場合は上記の不具合は生
じないものの、ＧａＡｓ半導体基板のアニールの場合に
はＡｓ４やＡＳＨ３ガス等を扱う必要があり、ガス圧制
御に精度を要するとともに安全性、作業性等の点で問題
があった。(b) Prior art and its 'problems' Long-time annealing is performed as a heat treatment to uniformize the electrical properties of a compound semiconductor substrate. in this case,
In order to suppress the evaporation of some constituent elements with high vapor pressure of the compound semiconductor substrate, the surface of the compound semiconductor substrate is coated with a dielectric protective film such as Si3N4, or in the case of a method that does not use a protective film, the atmosphere is controlled. GaA
In the case of semiconductor substrates, annealing was performed at 700 to 1200°C for several tens of hours. However, in the conventional method described above, the dielectric protective film could not withstand long-term annealing, resulting in cracks, tears, holes, etc. This causes a large amount of evaporation of some of the constituent elements of the compound semiconductor substrate, which have a high vapor pressure. Moreover, this evaporation occurs non-uniformly, resulting in a problem that the electrical characteristics of the compound semiconductor substrate become non-uniform within the substrate surface. In addition, although the above-mentioned problems do not occur in the case of the atmosphere control method, in the case of annealing GaAs semiconductor substrates, it is necessary to handle As4 and ASH3 gases, etc., which requires precision in gas pressure control and poses problems such as safety and workability. There was a problem with that.
（ハ）発明の目的
本発明は上記従来の事情に鑑みなされたものであって、
化合物半導体基板の構成元素の不均一な蒸発を防止する
ことにより化合物半導体基板面内での電気的特性のばら
つき発生を防止するとともに安全性、作業性等の点で問
題を生じない化合物半導体基板のための熱処理方法を提
供することを目的としている。(c) Purpose of the invention The present invention has been made in view of the above-mentioned conventional circumstances, and includes:
By preventing non-uniform evaporation of the constituent elements of the compound semiconductor substrate, variations in electrical properties within the surface of the compound semiconductor substrate can be prevented, and the compound semiconductor substrate can be manufactured without causing problems in terms of safety, workability, etc. The purpose is to provide a heat treatment method for
に）発明の構成
本発明による化合物半導体基板の熱処理方法においては
熱処理すべき化合物半導体基板の表面に誘電体保護膜を
設け、上記熱処理すべき化合物半導体基板を２枚の上記
熱処理すべき化合物半導体基板と同種の基板の間にはさ
み、上記化合物半導体の不純物原子および空格子が拡散
しはじめる温度から結晶の融点までの温度範囲で均質化
のための熱処理を行なうことを特徴としている。B) Structure of the Invention In the method for heat treatment of a compound semiconductor substrate according to the present invention, a dielectric protective film is provided on the surface of the compound semiconductor substrate to be heat treated, and the compound semiconductor substrate to be heat treated is combined with the two compound semiconductor substrates to be heat treated. The compound semiconductor is sandwiched between substrates of the same type as the compound semiconductor, and heat treatment is performed for homogenization at a temperature ranging from the temperature at which impurity atoms and vacancies of the compound semiconductor begin to diffuse to the melting point of the crystal.
これにより、化合物半導体基板の構成元素の不均一な蒸
発が防止されて化合物半導体基板面内での電気的特性の
ばらつき発生が防止され、かつ安全性、作業性の点で問
題の発生を防止することができる。This prevents non-uniform evaporation of constituent elements of the compound semiconductor substrate, prevents variations in electrical characteristics within the surface of the compound semiconductor substrate, and prevents problems in terms of safety and workability. be able to.
（ホ）発明の実施例
以下、図面を参照して本発明の好ましい実施例について
説明する。第１図は本発明の方法を示す図であって、化
合物半導体基板であるＧａＡｓ基板１は熱処理後研厘し
てイオン注入をしたりデバイス用基板として用いるため
のものであり、したがって厚い板状結晶をなし、表面は
必らずしも鏡面である必要はない。このＧａＡｓ基板１
の表面に誘電体保護膜２を形成し□、ＧａＡ、基板′１
を別の２枚のＣｒａＡｓ基板３．４で上下忙はさんだ状
態で熱処理する。熱処理はＧａＡＳ基板の結晶内部の均
質化を目的としたアニールであり、不純物原子および空
格子が拡散しはじめる温度から結晶の融点までの間の温
度範囲内で、通常ＧａＡｓ基板の場合で７００〜１２０
０℃にて、１〜４０時間にわたるものである。なお熱処
理するＧａＡｓ基板１をはさむ２枚のＧａＡＳ基板３．
４はＧａＡＳ基板１と同様誘電体保獲膜を形成したもの
でも、また誘電体保護膜を有しないものでも良い。(E) Embodiments of the Invention Preferred embodiments of the invention will now be described with reference to the drawings. FIG. 1 is a diagram illustrating the method of the present invention, in which a GaAs substrate 1, which is a compound semiconductor substrate, is polished after heat treatment and used for ion implantation or as a device substrate, and is therefore in the form of a thick plate. It forms a crystal, and the surface does not necessarily have to be mirror-like. This GaAs substrate 1
A dielectric protective film 2 is formed on the surface of □, GaA, and substrate '1.
is heat-treated with two other CraAs substrates 3.4 sandwiched between top and bottom. Heat treatment is annealing for the purpose of homogenizing the inside of the crystal of the GaAs substrate, and is performed within the temperature range from the temperature at which impurity atoms and vacancies begin to diffuse to the melting point of the crystal.
The duration is 1 to 40 hours at 0°C. Note that two GaAs substrates 3 sandwich the GaAs substrate 1 to be heat treated.
The substrate 4 may have a dielectric protection film formed thereon like the GaAS substrate 1, or may have no dielectric protection film.
このように配置することにより、熱処理されるＧａＡｓ
基板１０表側および裏側面を被覆し蒸気圧の高い一部構
成元素の蒸発を抑制するための誘電体保護膜２が別のＧ
ａＡ、基板３．４と密着するため温度上昇、下降時に誘
電体保護膜にかかる温度差ひずみか小さくなり、したが
って誘電体保護膜の破れ等の恐れが小さくなる。特にＧ
ａＡ３基板３．４が誘電体保護膜で被覆されている場合
はＧ２ＬＡｓ基板どうしの接触面間の熱膨張係数が同じ
となるため、誘電体保護膜の破れ等の恐れは最小となる
。By arranging it in this way, the GaAs to be heat treated is
A dielectric protective film 2 that covers the front and back sides of the substrate 10 and suppresses evaporation of some constituent elements with high vapor pressure is formed by another G.
aA, since it is in close contact with the substrate 3.4, the temperature difference strain applied to the dielectric protective film when the temperature rises or falls becomes small, and therefore the risk of breakage of the dielectric protective film is reduced. Especially G
When the aA3 substrate 3.4 is covered with a dielectric protective film, the coefficient of thermal expansion between the contact surfaces of the G2LAs substrates is the same, so the risk of breakage of the dielectric protective film is minimized.
また、たとえ熱処理中に誘電体保護膜の破れ等が生じて
も熱処理されるＧａＡｓ基板１をはさむ別のＧａＡｓ基
板６．４から発生する構成元素の蒸気圧によりＧ、Ａ、
基板１の表面には高い圧力がかけられるため、誘電体保
護膜の破れ等を通じての構成元素の蒸発が防止される。Furthermore, even if the dielectric protective film is torn during the heat treatment, the vapor pressure of the constituent elements generated from the other GaAs substrate 6.4 sandwiching the GaAs substrate 1 to be heat treated will cause G, A,
Since high pressure is applied to the surface of the substrate 1, evaporation of constituent elements through breakage of the dielectric protective film or the like is prevented.
なお、ＧａＡ、基板３．４が誘電体保護膜で被覆されて
いる場合でも、誘電体保護膜には極めて微細なピンホー
ルが概ね均一に存在しているため、これらピンホールを
通じてＧａＡｓ基板３．４からある程度の構成元素の蒸
発は生じ得る。このため、ＧａＡ、基板１０表面にはＧ
ａＡｓ基板１からの構成元素の蒸発を防止するための必
要最小限の蒸気圧が供給され、かくしてＧａＡｓ基板１
からの構成元素の蒸発が防止される。Note that even when the GaAs substrate 3.4 is covered with a dielectric protective film, extremely fine pinholes are generally uniformly present in the dielectric protective film, so that the GaAs substrate 3.4 is coated with the GaAs substrate 3.4 through these pinholes. 4, some evaporation of the constituent elements may occur. Therefore, GaA, G on the surface of the substrate 10
The minimum necessary vapor pressure to prevent evaporation of the constituent elements from the aAs substrate 1 is supplied, and thus the GaAs substrate 1
evaporation of constituent elements from the
このようにして、熱処理すべきＧａＡＳ基板１から蒸気
圧の高い構成元素の不均一な蒸発が防止され、同時に表
面の荒れが防止されるため熱処理すべきＧａＡｓ基板面
内における電気的特性のばらつき発生が減少される。In this way, uneven evaporation of constituent elements with high vapor pressure from the GaAs substrate 1 to be heat-treated is prevented, and at the same time, surface roughness is prevented, resulting in variations in electrical characteristics within the surface of the GaAs substrate to be heat-treated. is reduced.
さらに、熱処理すべきＧａＡｓ基板１をはさむ２枚のＧ
ａＡｓ基板６．４から構成元素が蒸発してほぼ必要な蒸
気圧を発生させるので、熱処理中雰囲気制御を精密に行
なう必要がない。そしてこの場合、蒸発源が固体のＧａ
Ａｓ基板であるので取扱いが簡便で作業性、安全性が向
上される。Furthermore, two G plates sandwiching the GaAs substrate 1 to be heat-treated
Since the constituent elements evaporate from the aAs substrate 6.4 to generate approximately the required vapor pressure, there is no need to precisely control the atmosphere during the heat treatment. In this case, the evaporation source is solid Ga
Since it is an As substrate, it is easy to handle and improves workability and safety.
本発明による熱処理方法は化合物半導体およびそれらの
混晶に対して適用可能である。The heat treatment method according to the present invention is applicable to compound semiconductors and mixed crystals thereof.
以下に本発明の実験例を示す。Experimental examples of the present invention are shown below.
アンドープＬＥＣ結晶から切り出し鏡面仕上した直径５
１謂のＧａＡｓウェハの表側面および裏側面に２７５℃
でＳｉＨ４とＮＨ３の混合ガスからプラズマＣＩ／Ｄ法
により５ｉ３Ｎ４Ｊｉを形成し、直径７６ｘｘのＧａＡ
ｓウェハ２枚ではさみ、８２０℃で１５時間にわたりＮ
２ 雰囲気中でアニールした後沸酸でＳｉ ３Ｎ４
膜を除去し、さらに試料表面を鏡面研磨した。また、上
記ＧａＡｓウェハと同様に作成した試料であつソ、アニ
ールの際２枚のＧａＡｓ ９エハテはさまなかったもの
を対照資料として用意した。Diameter 5 cut from undoped LEC crystal with mirror finish
275°C on the front and back sides of the so-called GaAs wafer.
5i3N4Ji was formed from a mixed gas of SiH4 and NH3 by the plasma CI/D method, and GaA with a diameter of 76xx was formed.
Sandwiched between two s wafers, N was heated at 820°C for 15 hours.
2 After annealing in an atmosphere, Si3N4 is
The film was removed and the sample surface was mirror polished. In addition, a sample prepared in the same manner as the GaAs wafer described above but in which the two GaAs 9 wafers were not sandwiched during annealing was prepared as a control material.
これら資料の表面の一直線上を電子線照射しカンーｙル
ミネセンス強度の分布を測定した。本発明の方法でアニ
ールを行った試料のカソードルミネセンス強度分布の一
例を第２図に示す。発光強度の平均値をａ１発光強度の
変動幅をｂとし、δＥＥ ｂ ／ ａで定義した発光強
度のばらつきを比較したデータを下表に示す。なお下表
には参考までに前述の１５時間のアニールを行なわなか
った試料のデータも含めている。A straight line on the surface of these materials was irradiated with an electron beam, and the distribution of luminescence intensity was measured. FIG. 2 shows an example of the cathodoluminescence intensity distribution of a sample annealed by the method of the present invention. The table below shows data comparing the variation in the luminescence intensity defined by δEE b / a, where the average value of the luminescence intensity is a1 and the variation width of the luminescence intensity is b. For reference, the table below also includes data for samples that were not annealed for 15 hours.
光強度のばらつきが小さく、試料の均質化アニールが効
果的に行なわれたことが証明されている。It was proven that the variation in light intensity was small, and that the sample was homogenized and annealed effectively.
さらに本発明の方法で熱処理されたウェハにＦＥＴ を
形成し、そのしきい値電圧のばらつきを調べた結果、２
枚のＧａＡｓウェハにはさんでアニールしなかったもの
に比べしきい値電圧の標準偏差値が１０６ｍＶから８１
ｍＶＫ減少し、電気的性質の均一化が向上されているこ
とが証明された。Furthermore, as a result of forming FETs on wafers heat-treated by the method of the present invention and investigating the variation in threshold voltage, it was found that 2
Compared to the one sandwiched between two GaAs wafers and not annealed, the standard deviation value of the threshold voltage ranged from 106 mV to 81 mV.
It was proved that the mVK was reduced and the uniformity of electrical properties was improved.
（へ）発明の効果
以上のように本発明によれば熱処理すべき化合物半導体
基板の表面に誘電体保護膜を設け、上記熱処理すべき化
合物半導体基板を２枚の上記熱処理すべき化合物半導体
基板とｆ８Ｊｍの基板の間にはさみ、上記化合物半導体
の不純物原子および空格子が拡散しはじめる温度から結
晶の融点までの温度範囲で均質化のための熱処理が行な
われる。(f) Effects of the Invention As described above, according to the present invention, a dielectric protective film is provided on the surface of the compound semiconductor substrate to be heat-treated, and the compound semiconductor substrate to be heat-treated is combined with the two compound semiconductor substrates to be heat-treated. It is sandwiched between substrates of f8Jm, and heat treatment for homogenization is performed in a temperature range from the temperature at which impurity atoms and vacancies of the compound semiconductor begin to diffuse to the melting point of the crystal.
これにより、熱処理される化合物半導体基板の表側およ
び裏側面を被覆し蒸気圧の高い一部構成元素の蒸発を抑
制するための誘電体保護膜が熱処理される化合物半導体
基板と同種の別の基板と密着するため、温度上昇下降時
に誘電体保護膜にかかる温度差ひずみが小さくなり、し
たがって誘電体保護膜の破れ等の恐れがホさくなる。ま
た、たとえ熱処理中に破れ等が生じても熱処理される化
金物半導体基板をはさむ別の同種の基板から発生する構
成元素の蒸気圧により熱処理される化合物半導体基板衣
ｍＫは高い圧力がかけられるため誘電体保護膜の破れ等
を通じての構成元素の蒸発が防止される。かくして化合
物半導体基板の構成元素の不均一蒸発が防止されるため
化合物半導体基板面内での電気的特性のばらつきが防止
される。As a result, a dielectric protective film that covers the front and back sides of the compound semiconductor substrate to be heat-treated and suppresses evaporation of some constituent elements with high vapor pressure is applied to another substrate of the same type as the compound semiconductor substrate to be heat-treated. Because of the close contact, the temperature difference strain applied to the dielectric protective film when the temperature rises and falls is reduced, and therefore the risk of breakage of the dielectric protective film is reduced. In addition, even if breakage or the like occurs during heat treatment, high pressure is applied to the compound semiconductor substrate coat mK that is heat-treated due to the vapor pressure of the constituent elements generated from other substrates of the same type sandwiching the heat-treated compound semiconductor substrate. Evaporation of constituent elements through breakage of the dielectric protective film is prevented. In this way, non-uniform evaporation of the constituent elements of the compound semiconductor substrate is prevented, thereby preventing variations in electrical characteristics within the plane of the compound semiconductor substrate.
さらに、熱処理中に熱処理される化合物半導体基板表面
に蒸気圧を生じさせる蒸発源が熱処理される化合物半導
体基板と同種の２枚の基板であるため取扱いが簡便で作
業性、安全性上の問題ななくすことができる。Furthermore, since the evaporation source that generates vapor pressure on the surface of the compound semiconductor substrate to be heat-treated during heat treatment is two substrates of the same type as the compound semiconductor substrate to be heat-treated, handling is simple and there are no problems with workability or safety. It can be eliminated.
第１図は本発明による化合物半導体基板の熱処理方法を
示す図、第２図は本発明方法でアニールを行った試料の
カソードルミネセンス強度分布の一例を示すグラフであ
る。
１・・・熱処理すべき化合物半導体基板２・・・誘電体
保護膜
６．４・・・熱処理すべき化合物半導体基板と同種の基
板
特許出願人 住友電気工業株式会社
同 日本電信電話公社
幕７図
葬２２図FIG. 1 is a diagram showing a heat treatment method for a compound semiconductor substrate according to the present invention, and FIG. 2 is a graph showing an example of the cathodoluminescence intensity distribution of a sample annealed by the method of the present invention. 1...Compound semiconductor substrate to be heat treated 2...Dielectric protective film 6.4...Substrate of the same type as the compound semiconductor substrate to be heat treated Patent applicant Sumitomo Electric Industries, Ltd. Nippon Telegraph and Telephone Public Corporation (Maku 7) Funeral 22 illustrations
Claims (3)
護膜を設け、該熱処理すべき化合物半導体基板を２枚の
該熱処理すべき化合物半導体基板と同種の基板の間には
さみ、該化合物半導体の不純物原子および空格子が拡散
しはじめる温度から結晶の融点までの温度範囲で均質化
のための熱処理を行なうことを特徴とする化合物半導体
基板の熱処理方法。(1) A dielectric protective film is provided on the surface of the compound semiconductor substrate to be heat-treated, and the compound semiconductor substrate to be heat-treated is sandwiched between two substrates of the same type as the compound semiconductor substrate to be heat-treated. A method for heat treatment of a compound semiconductor substrate, characterized by performing heat treatment for homogenization in a temperature range from the temperature at which impurity atoms and vacancies begin to diffuse to the melting point of the crystal.
の基板が誘電体保護膜を有しないことを特徴とする特許
請求の範囲第１項に記載の化合物半導体基板の熱処理方
法。(2) The method for heat-treating a compound semiconductor substrate according to claim 1, wherein the two substrates of the same type as the compound semiconductor substrates to be heat-treated do not have a dielectric protective film.
の基板が誘電体保護膜を有することを特徴とする特許請
求の範囲第１項に記載の化合物半導体基板の熱処理方法
。(3) The method for heat-treating a compound semiconductor substrate according to claim 1, wherein the two substrates of the same type as the compound semiconductor substrates to be heat-treated have a dielectric protective film.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP59156094A JPH0638418B2 (en) | 1984-07-26 | 1984-07-26 | Heat treatment method for compound semiconductor substrate |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP59156094A JPH0638418B2 (en) | 1984-07-26 | 1984-07-26 | Heat treatment method for compound semiconductor substrate |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS6134949A true JPS6134949A (en) | 1986-02-19 |
| JPH0638418B2 JPH0638418B2 (en) | 1994-05-18 |
Family
ID=15620175
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP59156094A Expired - Lifetime JPH0638418B2 (en) | 1984-07-26 | 1984-07-26 | Heat treatment method for compound semiconductor substrate |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0638418B2 (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS62265717A (en) * | 1986-05-13 | 1987-11-18 | Nippon Telegr & Teleph Corp <Ntt> | Heat treating method for substrate for gallium arsenide integrated circuit |
| JPH0518377U (en) * | 1991-08-30 | 1993-03-09 | マルホ産業株式会社 | Hanger |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5556637A (en) * | 1978-10-20 | 1980-04-25 | Matsushita Electric Ind Co Ltd | Preparation of semiconductor device |
| JPS5642334A (en) * | 1979-09-13 | 1981-04-20 | Sumitomo Electric Ind Ltd | Heat treatment of compound semiconductor |
| JPS57166025A (en) * | 1981-04-06 | 1982-10-13 | Matsushita Electric Ind Co Ltd | Heat treatment method for compound semiconductor device |
-
1984
- 1984-07-26 JP JP59156094A patent/JPH0638418B2/en not_active Expired - Lifetime
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5556637A (en) * | 1978-10-20 | 1980-04-25 | Matsushita Electric Ind Co Ltd | Preparation of semiconductor device |
| JPS5642334A (en) * | 1979-09-13 | 1981-04-20 | Sumitomo Electric Ind Ltd | Heat treatment of compound semiconductor |
| JPS57166025A (en) * | 1981-04-06 | 1982-10-13 | Matsushita Electric Ind Co Ltd | Heat treatment method for compound semiconductor device |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS62265717A (en) * | 1986-05-13 | 1987-11-18 | Nippon Telegr & Teleph Corp <Ntt> | Heat treating method for substrate for gallium arsenide integrated circuit |
| JPH0518377U (en) * | 1991-08-30 | 1993-03-09 | マルホ産業株式会社 | Hanger |
Also Published As
| Publication number | Publication date |
|---|---|
| JPH0638418B2 (en) | 1994-05-18 |
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