JPS603124A - Annealing method of compound semiconductor - Google Patents

Annealing method of compound semiconductor

Info

Publication number
JPS603124A
JPS603124A JP11065883A JP11065883A JPS603124A JP S603124 A JPS603124 A JP S603124A JP 11065883 A JP11065883 A JP 11065883A JP 11065883 A JP11065883 A JP 11065883A JP S603124 A JPS603124 A JP S603124A
Authority
JP
Japan
Prior art keywords
infrared rays
compound semiconductor
lamp
wavelength
substrate
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP11065883A
Other languages
Japanese (ja)
Inventor
Toshiki Ehata
敏樹 江畑
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Sumitomo Electric Industries Ltd
Original Assignee
Sumitomo Electric Industries Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Sumitomo Electric Industries Ltd filed Critical Sumitomo Electric Industries Ltd
Priority to JP11065883A priority Critical patent/JPS603124A/en
Publication of JPS603124A publication Critical patent/JPS603124A/en
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/26Bombardment with radiation
    • H01L21/263Bombardment with radiation with high-energy radiation
    • H01L21/265Bombardment with radiation with high-energy radiation producing ion implantation

Landscapes

  • Physics & Mathematics (AREA)
  • High Energy & Nuclear Physics (AREA)
  • Engineering & Computer Science (AREA)
  • Health & Medical Sciences (AREA)
  • Toxicology (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Crystals, And After-Treatments Of Crystals (AREA)

Abstract

PURPOSE:To prevent a compound semiconductor from thermal decomposition, and to suppress laterally directional diffusion at the same time by a method wherein an inorganic compound film is formed on the surface on the ion implanted side of the compound semiconductor to be heated by a lamp having the wavelength region of infrared rays and the region shorter than wavelength thereof. CONSTITUTION:A GaAs substrate 15 formed with Si3N4 films 14 is put on a carbon graphite plate 13 placing the ion implanted surface to the top side at the inside center of a quartz tube 11 filled with N2 gas, and heated by irradiating from the outside of the quartz tube 11 using a lamp heater 16. At this case, not only the infrared rays radiated from the lamp 16, but also light having shorter wavelength than the infrared rays is utilized. The compound semiconductor has large transmission to the light beam of the infrared region. Thereupon the substrate is heated directly according to light having shorter wavelength than the infrared rays, and at the same time, by heating the plate 13 according to the infrared rays, heating efficiency can be enhanced remarkably. Moreover, by forming the protective films according to the films 14, and by performing annealing, evaporation of a component having high vapor pressure can be obstructed.

Description

【発明の詳細な説明】 〔技術分野〕 不発明はGaAs * I nP 等の化合物半導体に
N型もしくはP型の不純物となり得るイオンを注入した
後、化合物半導体を高温にてアニールし、イオン注入層
を活性化させる方法に関するものである。
[Detailed Description of the Invention] [Technical Field] The invention is a method of implanting ions that can become N-type or P-type impurities into a compound semiconductor such as GaAs*InP, and then annealing the compound semiconductor at a high temperature to form an ion-implanted layer. This relates to a method for activating.

〔背景技術〕[Background technology]

GaAs 等の化合物半導体結晶基板を用いイオン注入
によってトランジスタや集積回路を製作する場合、アニ
ールの工程は導電層を形成する上で不可欠である。アニ
ールは一般にイオン注入された化合物半導体基板を抵抗
加熱炉セ数十分間高温加熱処理するものである。加熱温
度は基板に含まれる蒸気圧の高い成分例えばAsやP 
が蒸発を開始する温度より高いため基板が熱分解を生じ
るという問題があった。このためアニールによって基板
表面に形成する導電層の電気的性質が変動し、バラツキ
が太きいという問題があった。
When manufacturing transistors or integrated circuits by ion implantation using a compound semiconductor crystal substrate such as GaAs, an annealing process is essential for forming a conductive layer. Annealing generally involves subjecting the ion-implanted compound semiconductor substrate to high-temperature heat treatment for several tens of minutes in a resistance heating furnace. The heating temperature is determined by the components with high vapor pressure contained in the substrate, such as As and P.
There is a problem in that the substrate thermally decomposes because the temperature is higher than the temperature at which evaporation begins. For this reason, there is a problem in that the electrical properties of the conductive layer formed on the substrate surface vary due to annealing, resulting in large variations.

これを防ぐため蒸気圧の高い成分の蒸気圧下でアニール
したり蒸発を防ぐための保護膜例えば、SiO2膜やS
i3N4 膜を基板表面に形成した後にアニールする方
法が採られている。しかしながら前者の方法では蒸気圧
の高い成分を含むガスが有毒であるため操作や処理が複
雑なプロセスとなり、生産性が著しく低いという問題が
残る。一方、後者では保護膜の形成法、形成条件によっ
て膜の性質が異なるkめ安定性、再現性が低くアニール
中に保護膜が割れる等の問題がある。
To prevent this, a protective film such as SiO2 film or S
A method is adopted in which an i3N4 film is formed on the substrate surface and then annealed. However, in the former method, the problem remains that the gas containing components with high vapor pressure is toxic, making the process complicated to operate and processing, and resulting in extremely low productivity. On the other hand, the latter has problems such as low stability and low reproducibility, and cracking of the protective film during annealing, as the properties of the film vary depending on the method and conditions for forming the protective film.

また、従来のアニール法は電気炉で数十分′間高温熱処
理するため基板結晶内の残留不純物であるCr ’p 
Mnが拡散や表面近傍での高濃度化等を起こし、イオン
注入された原子と相互に影響を及ぼすことが知られてい
る。このためアニールによる活性化率が不安定となり、
l−ランジスクや集積回路の電気特性を制御することが
困Mllfとなっている。
In addition, in the conventional annealing method, high-temperature heat treatment is performed for several tens of minutes in an electric furnace, so residual impurities in the substrate crystal, Cr'p
It is known that Mn causes diffusion, high concentration near the surface, etc., and interacts with ion-implanted atoms. For this reason, the activation rate due to annealing becomes unstable,
It has become difficult to control the electrical characteristics of l-range disks and integrated circuits.

さらに従来のアニール法では注入された原子がアニール
中に表面と平行な方向に十分の数ミクロンも拡散する横
方向拡散も知られている。このため注入領域、例えば実
効ゲート長が変化することになり1μmという微細加工
が必要な素子製造の面からは重大な問題となる。
Furthermore, in conventional annealing methods, lateral diffusion is also known, in which implanted atoms diffuse several tenths of a micrometer in a direction parallel to the surface during annealing. This causes a change in the implanted region, for example, the effective gate length, which poses a serious problem in terms of device manufacturing, which requires microfabrication of 1 μm.

これに対し、近年赤外線ランプによるアニール法が報告
されている。基板を急速に加熱できるという特徴から従
来法のアニールより約2桁短いアニール時間が可能であ
り、従って横方向拡散も抑制できると共に蒸気圧の高い
AsjeP の威容の蒸発も最小限に低減できると報告
されている。しかしながら、AsやP の蒸発は原理的
に皆無にできない。例えば、800℃で10秒間熱処理
しただけでも鏡面研磨されたGaAs 基板表面の全面
にわたつて微小な斑点が生じ、いわゆるAs 抜けが観
察され、AsやP の蒸発については依然問題が残って
いる。
In contrast, an annealing method using an infrared lamp has been reported in recent years. Due to its ability to rapidly heat the substrate, the annealing time is approximately two orders of magnitude shorter than that of conventional annealing methods, and it is reported that lateral diffusion can be suppressed and the evaporation of AsjeP, which has a high vapor pressure, can be reduced to a minimum. has been done. However, evaporation of As and P cannot be completely eliminated in principle. For example, even after heat treatment at 800° C. for 10 seconds, minute spots appear over the entire surface of a mirror-polished GaAs substrate, and so-called As drop-out is observed, and problems still remain regarding the evaporation of As and P.

〔発明の開示〕[Disclosure of the invention]

本発明はこのような従来法の欠点を解消し、化合物半導
体の熱分解を防ぐと同時に横方向の拡散を抑制し得るア
ニール方法を提供・するものである。
The present invention eliminates the drawbacks of the conventional methods and provides an annealing method capable of preventing thermal decomposition of a compound semiconductor and at the same time suppressing lateral diffusion.

以下、実施例に即して、本発明を説明する。第1図は化
合物半導体としてGaAs 基板を用いる場合の本発明
によるアニール法の借成を図示したものである。一度真
空排気された後、N2 ガスを満たした石英管11の内
部中央に石英治具12を介して保持された厚さ数理のカ
ーボングラファイト板13上に両面に厚さ1ooo X
のSi3N+膜14・をプラズマCVD法で形成したG
aAs 基板15をイオン注入された面を上にして置き
、石英管]]、の外部よりGaAs 基板15の両面か
らランプヒーク16を用いて照射して加熱させる。アニ
ール温度は、GaAs 基板15の近傍に設置した熱電
対により測定し、これを基準にしてランプに印加する電
力をPID制御することにエリ、加熱速度、アニール温
′度を一定にした。本発明になるアニール法で900’
C10秒間アニールした試料は従来の電気炉で、800
°C20分アニールした試料と同等のキャリア濃度プロ
ファイルを示した。
Hereinafter, the present invention will be explained based on examples. FIG. 1 illustrates the use of the annealing method according to the present invention when a GaAs substrate is used as a compound semiconductor. Once evacuated, a carbon graphite plate 13 with a thickness of 100 X is placed on both sides on a carbon graphite plate 13 with a mathematical thickness held in the center of the quartz tube 11 filled with N2 gas via a quartz jig 12.
G in which Si3N+ film 14 was formed by plasma CVD method.
The aAs substrate 15 is placed with the ion-implanted side facing upward, and the GaAs substrate 15 is heated by irradiation from the outside of the quartz tube from both sides using a lamp heater 16. The annealing temperature was measured by a thermocouple placed near the GaAs substrate 15, and the power applied to the lamp was controlled by PID based on this value, and the heating rate and annealing temperature were kept constant. 900' by the annealing method of the present invention.
The sample annealed for C10 seconds was heated at 800 C in a conventional electric furnace.
It showed a carrier concentration profile equivalent to that of the sample annealed at °C for 20 minutes.

本発明を+1η成する要件の一つはランプからの熱線と
して赤外線のみならず、赤外線よりも波長の短い光をも
利用することにある。化合物半導体は赤外領域の光線に
対して大きな透過率を有しているため赤外線による化合
物半導体基板の加熱は実・賃上効率が極めて小さくなる
。そこで本発明ては赤外線より短波長な光で基板を直接
加熱すると同時に赤外線で基板を載せたカーボングラフ
ァイト治具を加熱することにより、加熱効率を著しく向
上することにある。
One of the requirements for achieving +1η of the present invention is that not only infrared rays but also light with a wavelength shorter than infrared rays is used as the heat rays from the lamp. Since compound semiconductors have a high transmittance to light in the infrared region, the actual and wage efficiency of heating compound semiconductor substrates with infrared rays is extremely low. Therefore, the present invention aims to significantly improve heating efficiency by directly heating the substrate with light having a wavelength shorter than infrared rays and at the same time heating the carbon graphite jig on which the substrate is mounted with infrared rays.

さらにもう一つの要件は化合物半導体基板の少なくとも
イオン注入された面に無機化合物の保護膜を形成してア
ニールすることにある。これにより蒸気圧の高い成分の
蒸発を完全に阻止することが可能となる。この目的から
考えるに無機化合物膜としては実施例のSi3N4膜や
プラズマCVD法に何ら限定されるものではなく、他に
5i02膜、A12!03膜AI!N膜等を周知の製法
で形成することも可能である。
Yet another requirement is that a protective film of an inorganic compound be formed on at least the ion-implanted surface of the compound semiconductor substrate and then annealed. This makes it possible to completely prevent evaporation of components with high vapor pressure. Considering this purpose, the inorganic compound film is not limited to the Si3N4 film of the embodiment or the plasma CVD method, but also the 5i02 film, A12!03 film, AI! It is also possible to form an N film or the like using a well-known manufacturing method.

さらにアニールは化合物半導体基板に高温で不必要な化
学反応を生じないために不活性ガス中で行なえば本発明
の目的を苛たずことから雰囲気は実施例のN2 ガスに
何ら限定されるものではなく、N2の他にAr、He 
等の不活性ガスやN2 ガス及び
Furthermore, the object of the present invention will not be impaired if annealing is performed in an inert gas to avoid unnecessary chemical reactions at high temperatures on the compound semiconductor substrate, so the atmosphere is not limited to the N2 gas used in the example. No, in addition to N2, Ar, He
Inert gas such as N2 gas and

【図面の簡単な説明】[Brief explanation of drawings]

図1は本発明の詳細な説明するための図である。 11・・・石英管 ■2・・・石英治具 13・・・カーボングラファイト板 14・・・無機化合物膜 15・・・化合物半導体基板 16・・・ランプヒータ FIG. 1 is a diagram for explaining the present invention in detail. 11...Quartz tube ■2...Quartz jig 13...Carbon graphite plate 14...Inorganic compound film 15... Compound semiconductor substrate 16...Lamp heater

Claims (1)

【特許請求の範囲】[Claims] (1)N型またはP型となりうるイオンを注入された化
合物半導体の少なくともイオン注入された側の表面に無
機化合物膜を形成し、赤外線及びそれより短い波長域に
スペクトルをもつランプにて該化合物半導体を照射して
加熱することを特徴とする化合物半導体のアニール法。
(1) An inorganic compound film is formed on at least the ion-implanted side surface of a compound semiconductor implanted with ions that can be N-type or P-type, and the compound is treated with a lamp having a spectrum in the infrared and shorter wavelength ranges. A compound semiconductor annealing method characterized by heating the semiconductor by irradiating it.
JP11065883A 1983-06-20 1983-06-20 Annealing method of compound semiconductor Pending JPS603124A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP11065883A JPS603124A (en) 1983-06-20 1983-06-20 Annealing method of compound semiconductor

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP11065883A JPS603124A (en) 1983-06-20 1983-06-20 Annealing method of compound semiconductor

Publications (1)

Publication Number Publication Date
JPS603124A true JPS603124A (en) 1985-01-09

Family

ID=14541213

Family Applications (1)

Application Number Title Priority Date Filing Date
JP11065883A Pending JPS603124A (en) 1983-06-20 1983-06-20 Annealing method of compound semiconductor

Country Status (1)

Country Link
JP (1) JPS603124A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH03146614A (en) * 1989-10-31 1991-06-21 Tokyo Gas Denro Kk Device for recovering hardening salt from washing tank of hardening device
US5970213A (en) * 1993-03-02 1999-10-19 Balzers Und Leybold Deutschland Holding Aktiengesellscaft Apparatus for heating a transparent substrate utilizing an incandescent lamp and a heating disk emitting infrared wavelengths

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH03146614A (en) * 1989-10-31 1991-06-21 Tokyo Gas Denro Kk Device for recovering hardening salt from washing tank of hardening device
US5970213A (en) * 1993-03-02 1999-10-19 Balzers Und Leybold Deutschland Holding Aktiengesellscaft Apparatus for heating a transparent substrate utilizing an incandescent lamp and a heating disk emitting infrared wavelengths

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