JPS60148129A - Heat treatment of compound semiconductor substrate - Google Patents
Heat treatment of compound semiconductor substrateInfo
- Publication number
- JPS60148129A JPS60148129A JP59004053A JP405384A JPS60148129A JP S60148129 A JPS60148129 A JP S60148129A JP 59004053 A JP59004053 A JP 59004053A JP 405384 A JP405384 A JP 405384A JP S60148129 A JPS60148129 A JP S60148129A
- Authority
- JP
- Japan
- Prior art keywords
- compound semiconductor
- semiconductor substrate
- substrate
- heat
- treated
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000000758 substrate Substances 0.000 title claims abstract description 95
- 150000001875 compounds Chemical class 0.000 title claims abstract description 50
- 239000004065 semiconductor Substances 0.000 title claims abstract description 49
- 238000010438 heat treatment Methods 0.000 title claims abstract description 26
- 230000001681 protective effect Effects 0.000 claims abstract description 27
- 238000000034 method Methods 0.000 claims abstract description 21
- 238000005468 ion implantation Methods 0.000 claims abstract description 8
- 230000004913 activation Effects 0.000 claims abstract description 7
- 230000003213 activating effect Effects 0.000 claims 1
- 239000004020 conductor Substances 0.000 claims 1
- 239000002356 single layer Substances 0.000 claims 1
- 239000000470 constituent Substances 0.000 abstract description 27
- 239000006185 dispersion Substances 0.000 abstract 2
- 230000008016 vaporization Effects 0.000 abstract 2
- 238000009834 vaporization Methods 0.000 abstract 2
- 229910001218 Gallium arsenide Inorganic materials 0.000 description 28
- 230000008020 evaporation Effects 0.000 description 21
- 238000001704 evaporation Methods 0.000 description 21
- 235000012431 wafers Nutrition 0.000 description 17
- 238000009826 distribution Methods 0.000 description 6
- 238000010586 diagram Methods 0.000 description 5
- 230000003746 surface roughness Effects 0.000 description 4
- 150000002500 ions Chemical class 0.000 description 2
- 238000005268 plasma chemical vapour deposition Methods 0.000 description 2
- 101100215641 Aeromonas salmonicida ash3 gene Proteins 0.000 description 1
- 241000257465 Echinoidea Species 0.000 description 1
- 239000002253 acid Substances 0.000 description 1
- 239000012080 ambient air Substances 0.000 description 1
- RBFQJDQYXXHULB-UHFFFAOYSA-N arsane Chemical compound [AsH3] RBFQJDQYXXHULB-UHFFFAOYSA-N 0.000 description 1
- 229910000070 arsenic hydride Inorganic materials 0.000 description 1
- 238000004140 cleaning Methods 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 238000005336 cracking Methods 0.000 description 1
- 239000013078 crystal Substances 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 239000003960 organic solvent Substances 0.000 description 1
- 239000007787 solid Substances 0.000 description 1
- 238000010025 steaming Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/324—Thermal treatment for modifying the properties of semiconductor bodies, e.g. annealing, sintering
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Testing Or Measuring Of Semiconductors Or The Like (AREA)
Abstract
Description
【発明の詳細な説明】 （イ） 発明の属する技術分野 本発明は化合物半導体基板の熱処理方法に関する。[Detailed description of the invention] (b) Technical field to which the invention belongs The present invention relates to a method for heat treating a compound semiconductor substrate.
（口） 従来技術とその問題点
半絶縁性の化合物半導体基板上に活性層を形成する際、
イオン注入法により注入した原子を電気的に活性化する
ための熱処理が行なわれる。しかし化合物半導体におい
てはその構成元素各々の蒸気圧が異なるため、そのまま
熱処理したのでは構成元素の不均一蒸発およびそれにと
もなう基板面内の電気的特性のばらつき発生を防ぐこと
ができないので、その対策として下記のいずれかの方法
がとられていた。(Expression) Conventional technology and its problems When forming an active layer on a semi-insulating compound semiconductor substrate,
Heat treatment is performed to electrically activate atoms implanted by ion implantation. However, in compound semiconductors, the vapor pressures of each of the constituent elements are different, so if heat treatment is performed as is, it will not be possible to prevent non-uniform evaporation of the constituent elements and the resulting variation in electrical properties within the substrate surface. One of the following methods was used.
（ＩＩ フエイスツーフエイス法
熱処理すべき化合物半導体基板を別の同一の化合物半導
体基板と対向接触させた状態で熱処理することにより、
対向接触する別の化合物半導体基板から発生する構成元
素の蒸気工匠より熱処理すべき化合物半導体基板の表面
に高い圧力をかけ、熱処理すべき化合物半導体基板の構
成元素の蒸発を防ぎながら熱処理する方法。(II Face-to-Face Method By heat-treating the compound semiconductor substrate to be heat-treated in a state where it is in facing contact with another identical compound semiconductor substrate,
A method of heat-treating the surface of a compound semiconductor substrate to be heat-treated while preventing evaporation of the constituent elements of the compound semiconductor substrate to be heat-treated, by applying high pressure to the surface of the compound semiconductor substrate to be heat-treated by steaming the constituent elements generated from another compound semiconductor substrate in opposing contact with each other.
（２＋ 、、、誘電体保護膜法
熱処理すべき化合物半導体基板の表側および裏側面にプ
ラズマＣＶＤ法などにより誘電体保護膜を設け、表面か
ら蒸気圧の高い一部構成元素の蒸発を抑制しながら熱°
処理する方法。(2+, Dielectric protective film method) A dielectric protective film is provided on the front and back sides of the compound semiconductor substrate to be heat-treated using a plasma CVD method, etc., while suppressing the evaporation of some constituent elements with high vapor pressure from the surface. heat °
How to process.
（３） 揮発性構成元素のガス圧印加法化合物半導体基
板の揮発性構成元素を含むガス圧雰囲気内で熱処理する
方法で、たとえばＧａＡｓ基板の場合であればＡｓ 圧
雰囲気としてＡｓ４又はＡｓＨ３等を用いる。(3) Gas pressure application method for volatile constituent elements A method of heat-treating a compound semiconductor substrate in a gas pressure atmosphere containing volatile constituent elements. For example, in the case of a GaAs substrate, As4 or AsH3 is used as the pressure atmosphere. .
しかしながら上記従来の方法は下記の問題点を有してい
た。すなわち、以下に上記（１）〜（３）に対応させて
記述すると：
（１１化合物半導体基板を別の同一の基板と対向接触さ
せただけでは化合物半導体基板表面から高蒸気圧の構成
元系の蒸発を完全に抑えることができないため基板面内
での構成元素の不均一蒸発が生じ、したがって基板面内
での′電気的特性のばらつきが生じてしまう。However, the above conventional method had the following problems. That is, the following description corresponds to (1) to (3) above: Since evaporation cannot be completely suppressed, non-uniform evaporation of constituent elements occurs within the plane of the substrate, resulting in variations in electrical characteristics within the plane of the substrate.
（２）誘電体保護膜と化合物半導体基板との熱膨張係数
のちがいにより誘電体保護膜にひび、はがれ、破れ等が
生じてしまい、これらを通じて化合物半導体基板の蒸気
圧の高い一部構成元素が大量に蒸発し、しかも不均一に
蒸発するため基板表面に歪みや傷が生ずるとともに基板
面内で電気的特性か不均一になってしまう。(2) Due to the difference in thermal expansion coefficient between the dielectric protective film and the compound semiconductor substrate, cracks, peeling, and tears occur in the dielectric protective film, and through these, some constituent elements with high vapor pressure of the compound semiconductor substrate are released. Since a large amount of evaporation occurs and it evaporates non-uniformly, distortions and scratches occur on the substrate surface, and the electrical characteristics become non-uniform within the substrate surface.
（３）＃囲気制御のためＡｓ４やＡＳＨ３ガスを使用す
る必要があるためガス圧制御に精度を要するとともに安
全性、作業性等の点で問題がある。(3) # Because it is necessary to use As4 or ASH3 gas for ambient air control, precision is required for gas pressure control and there are problems in terms of safety, workability, etc.
（）ｊ 発明の目的
本発明は上記従来の事情に鑑みなされたものであって化
合物半導体基板の構成元系の不均一な蒸発を防止するこ
とにより化合物半導体基板面内での電気的特性のばらつ
き発生を防止するとともに安全性、作業性等の点で問題
を生じない化合物半導体基板のための熱処理方法を提供
することを目的としている。()j Purpose of the Invention The present invention has been made in view of the above-mentioned conventional circumstances, and is intended to reduce the variation in electrical characteristics within the plane of a compound semiconductor substrate by preventing uneven evaporation of the constituent elements of the compound semiconductor substrate. The object of the present invention is to provide a heat treatment method for compound semiconductor substrates that prevents the occurrence of such problems and does not cause problems in terms of safety, workability, etc.
に）発明の構成
本発明による化合物半導体基板の熱処理方法においては
イオン注入済の熱処理すべき化合物半導体基板の表面に
誘電体保護膜を設け、上記熱処理すべき化合物半導体基
板を２枚の上記熱処理すべき化合物半導体基板と同種の
基板の間にはさみ、上記イオン注入による注入原子の活
性化温度にて上記注入原子の活性化のための熱処理を行
なうことを特徴としている。B) Structure of the Invention In the heat treatment method for compound semiconductor substrates according to the present invention, a dielectric protective film is provided on the surface of the ion-implanted compound semiconductor substrate to be heat-treated, and two compound semiconductor substrates to be heat-treated are subjected to the heat treatment. It is characterized in that it is sandwiched between a compound semiconductor substrate and a substrate of the same type, and heat treatment is performed to activate the implanted atoms at the activation temperature of the implanted atoms by the ion implantation.
これにより、化合物半導体基板の構成元素の不均一な蒸
発が防止されて化合物半導体基板面内での電気的特性の
ばらつき発生が防止され、かつ安全性、作業性の点で問
題の発生を防止することができる。This prevents non-uniform evaporation of constituent elements of the compound semiconductor substrate, prevents variations in electrical characteristics within the surface of the compound semiconductor substrate, and prevents problems in terms of safety and workability. be able to.
（ホ）発明の実施例
以下、図面を参照して本発明の好ましい実施例について
説明する。第１図は本発明の方法を示す図であって、化
合物半導体基板であるＧａＡｓ基板１は表面を鏡面状に
仕立げられイオン注入が施されている。このＧａＡｓ基
板１０表面に誘電体保護膜２を形成し、ＧａＡｓ基板１
を別の２枚のＧａＡｓ基板ろ、４でと下にはさんだ状態
で熱処理する。(E) Embodiments of the Invention Preferred embodiments of the invention will now be described with reference to the drawings. FIG. 1 is a diagram showing the method of the present invention, in which a GaAs substrate 1, which is a compound semiconductor substrate, has a mirror-finished surface and is ion-implanted. A dielectric protective film 2 is formed on the surface of this GaAs substrate 10, and
is sandwiched between two other GaAs substrates, 4 and below, and heat treated.
！処理はイオン注入による注入原子の活性化を目的とし
たものであり注入原子の活性化温度て、通常ＧａＡｓ基
板の場合で７００〜９０Ｑ℃にて行ない熱処理時間は１
時間以内である。なお熱処理するＣａＡｓ基板１をはさ
む２枚＋７） ＧａＡｓ 基板３．４はＣａＡｓ基板１
と同様誘電体保護膜を形成したものでも、また誘電体保
護膜を有しないものでも良（−０
このように配置することにより、熱処理されるＧａＡｓ
基板１０表側および裏側面を被覆し蒸気圧の高℃・一部
構成元累の蒸発を抑制するための誘電体保護膜２が別の
ＧａＡｓ基板６．４と密着するため温度と昇、下降時に
誘電体保護１厘にかかる温度差ひずみが小さくなり、し
たがって誘電体保護膜の破れ等の恐れが小さくなる。特
にＧａＡｓ基板ろ。! The purpose of the treatment is to activate the implanted atoms by ion implantation, and the activation temperature of the implanted atoms is usually 700 to 90Q°C in the case of a GaAs substrate, and the heat treatment time is 1.
Within hours. Note that 2 sheets sandwiching the CaAs substrate 1 to be heat treated + 7) GaAs substrate 3.4 is the CaAs substrate 1.
It may be a type with a dielectric protective film formed thereon or a type without a dielectric protective film (-0) By arranging it in this way, the GaAs to be heat treated can be
The dielectric protective film 2, which covers the front and back sides of the substrate 10 and suppresses evaporation of some of the constituent elements due to high vapor pressure, is in close contact with another GaAs substrate 6.4, so that when the temperature rises or falls, The temperature difference strain applied to one layer of dielectric protection is reduced, and therefore the risk of breakage of the dielectric protection film is reduced. Especially GaAs substrates.
４が誘電体保護膜で被覆されている場合はＧａＡｓ基板
どうしの接触面間の熱膨張係数が同じとなるため、誘電
体保護膜の破れ等の恐れは最小となる。When the GaAs substrates 4 are covered with a dielectric protective film, the coefficient of thermal expansion between the contact surfaces of the GaAs substrates is the same, so the risk of breakage of the dielectric protective film is minimized.
また、たとえ熱処理中に誘電体保護膜の破れ等が生じて
も熱処理されるＧａＡｓ基板１をはさむ別のＧａＡｓ基
板６．４から発生する構成元素の蒸気圧によりＧａＡｓ
基板１０表面には高い圧力がかけられるため、誘電体保
護膜の破れ等を通じての構成元素の蒸発が防止される。Furthermore, even if the dielectric protective film is torn during the heat treatment, the vapor pressure of the constituent elements generated from the other GaAs substrate 6.4 sandwiching the GaAs substrate 1 to be heat treated will cause the GaAs to
Since high pressure is applied to the surface of the substrate 10, evaporation of constituent elements through breakage of the dielectric protective film or the like is prevented.
なお、ＧａＡｓ基板６゜４が誘電体保護膜で被覆されて
いる場合でも、誘電体保護膜には極めて微細なピンホー
ルが概ね均一に存在しているため、これらピンホールを
通じてＧａＡｓ基板６．４からある程度の構成元素の蒸
発は生じ得る。このため、ＧａＡｓ基板１０表面にはＧ
ａＡｓ基板１からの構成元素の蒸発を防止するための必
要最小限の蒸気圧が供給され、か（してＧａＡｓ基板１
からの構成元素の蒸発が防止される。Note that even when the GaAs substrate 6.4 is covered with a dielectric protective film, extremely fine pinholes are generally uniformly present in the dielectric protective film. Evaporation of the constituent elements to some extent may occur. Therefore, G on the surface of the GaAs substrate 10
The minimum necessary vapor pressure to prevent the evaporation of the constituent elements from the aAs substrate 1 is supplied, and the GaAs substrate 1
evaporation of constituent elements from the
このようにして、熱処理すべきｃａＡｓ基板１から蒸気
圧の高い構成元素の不均一な蒸発が防止され、同時に表
面の荒れが防止されるため熱処理すべきＧａＡｓ基板面
内における電気的特性のばらつき発生が減少される。In this way, non-uniform evaporation of constituent elements with high vapor pressure from the caAs substrate 1 to be heat-treated is prevented, and at the same time, surface roughness is prevented, resulting in variations in electrical characteristics within the surface of the GaAs substrate 1 to be heat-treated. is reduced.
さらに、熱処理すべきＧａＡｓ基板１をはさむ２枚のＧ
ａＡＳ基板ろ、４から構成元素が蒸発してほぼ必要な蒸
気圧を発生させるので、熱処理中雰囲気制御を精密に行
なう必要がない。そしてこの場合、蒸発源が固体のＧａ
Ａｓ基板であるので取扱いが簡便で作業性、安全性が自
主される。Furthermore, two G plates sandwiching the GaAs substrate 1 to be heat-treated
Since the constituent elements evaporate from the aAS substrate 4 to generate approximately the required vapor pressure, there is no need to precisely control the atmosphere during heat treatment. In this case, the evaporation source is solid Ga
Since it is an As substrate, it is easy to handle and has high workability and safety.
本発明による熱処理方法は化合物半樽体およびそれらの
混晶に対して適用可能である。The heat treatment method according to the present invention is applicable to half-barrel bodies of compounds and mixed crystals thereof.
以下に本発明の実験例を示す。Experimental examples of the present invention are shown below.
Ｓｉ イオンを１８０ ＫｅＶで１．５Ｘ１０１２個／
ｃｍ注入したＧａＡ Ｓウエノ・表面を有機溶媒で洗
浄の後２７Ｄ〜２８０℃の温度で５ＩＨ４とＮＨ３の混
合ガスよりプラズマＣＶＤ法により１ｏｏｏ〜２ｏｏｏ
ｉの均一な５１３Ｎ４膜をウェハの表側面および裏側面
に形成した。次いでこの試料を２枚のＧａＡｓウェハで
はさみＮ２ ガス中で８２０°Ｃで２０分間にわたり活
性化のための熱処理を施した。その際、上記と同様に作
成した別の試料を２枚の（−７ａＡＳウエハではさまな
い状態で同時に熱処理を施した。熱処理後、冷却した各
試料から佛酸で８１３１ｉ４１ｇを除去して表面を顕微
鏡観察した。第２図は２枚のＧａＡｓウェハではさまな
かった場合、第６図は本発明の方法により２枚のＧａＡ
ｓウェハではさんだ場合の熱処理後のウェハ表面状態を
概略的に示した図である。第２図、第６図から分るよう
に、２枚のＧａＡｓウェハで試料をはさんで熱処理する
ことにより表面荒れが大幅に減少していることがわかる
。すなわち、第２図では８１３Ｎ４膜のひび割れ５、小
さなスポット状の破れろ、大きなはがれ７および全面に
わたる小さな抜は穴８等に対応した表面荒れが見られる
のに対し、第６図では小さなスポット状の破れ９が数点
見られるだけで表面は概ね鏡面が保たれており、Ｓｉ３
Ｎ、、膜のひび、はがれ等の発生はほとんどなかった。1.5×1012 Si ions at 180 KeV/
After cleaning the surface of GaAs injected with an organic solvent, it was heated to 1ooo to 2ooo by plasma CVD using a mixed gas of 5IH4 and NH3 at a temperature of 27D to 280℃.
A uniform 513N4 film of i was formed on the front and back sides of the wafer. This sample was then sandwiched between two GaAs wafers and subjected to a heat treatment for activation at 820°C for 20 minutes in N2 gas. At that time, another sample prepared in the same manner as above was heat-treated at the same time without being sandwiched between two (-7aAS wafers. After the heat treatment, 8131i41g was removed from each cooled sample with Butsu acid, and the surface was examined using a microscope. Figure 2 shows the case where the wafers were not sandwiched between two GaAs wafers, and Figure 6 shows the case where the wafers were not sandwiched between the two GaAs wafers.
FIG. 3 is a diagram schematically showing the state of the wafer surface after heat treatment when the wafer is sandwiched between S wafers. As can be seen from FIGS. 2 and 6, surface roughness is significantly reduced by heat-treating the sample while sandwiching it between two GaAs wafers. That is, in Fig. 2, surface roughness corresponding to cracks 5, small spot-like tears, large peeling 7, and small holes 8 over the entire surface of the 813N4 film can be seen, whereas in Fig. 6, small spot-like tears are observed. The surface is generally mirror-like, with only a few cracks 9 visible, and Si3
There was almost no occurrence of cracking or peeling of the N film.
したがって、第６図の試料では試料表面からの構成元素
の不均一蒸発が概ね防止されており、これにより試料面
内での電気的特性のばらつき発生が防止されていること
が判断される。Therefore, in the sample shown in FIG. 6, non-uniform evaporation of the constituent elements from the sample surface is generally prevented, and it is thus determined that variations in electrical characteristics within the sample surface are prevented.
次に、注入したＳｌ イオンの活性化の状！川を見るた
め容量−電圧法でＧａＡｓウェハの表面から深さ方向へ
のキャリヤ分布を測定した。第４図はキャリヤ分布を示
すグラフであって横軸は表面からの深さ、縦軸はキャリ
ヤ濃度を示す。曲線１はＬＳＳ曲線とよばれる理論曲線
である。本発明の方法で熱処理した場合曲線２のキャリ
ヤ分布が得られた。このキャリヤ分布はウニ・・全面に
わたりほぼ均一でかつ曲線１に近似坪ており、全面にわ
たって良く活性化されたことが示されている。一方、誘
電体保護膜付のｃａＡｓウェハを別の２枚のＧａＡｓウ
ェハではさまずに熱処理した場合のキャリヤ分布はウェ
ハ面内にて均一でなく変動がちであり、また曲線乙に示
すように理論曲線からのずれが太きい。この実験データ
から、本発明の熱処理方法を実施した場合化合物半導体
基板の構成元素の不均一蒸発の防止による電気的特性の
ばらつき発生防止の効果がイ准認される。Next, let's look at the activation status of the implanted Sl ions! In order to observe the flow, the carrier distribution in the depth direction from the surface of the GaAs wafer was measured using the capacitance-voltage method. FIG. 4 is a graph showing the carrier distribution, where the horizontal axis shows the depth from the surface and the vertical axis shows the carrier concentration. Curve 1 is a theoretical curve called an LSS curve. When heat-treated by the method of the present invention, a carrier distribution of curve 2 was obtained. This carrier distribution was almost uniform over the entire surface of the sea urchin and approximated curve 1, indicating that the entire surface was well activated. On the other hand, when a caAs wafer with a dielectric protective film is heat-treated without being sandwiched between two other GaAs wafers, the carrier distribution is not uniform within the wafer surface and tends to fluctuate, and the theoretical The deviation from the curve is large. From this experimental data, it is confirmed that when the heat treatment method of the present invention is carried out, it is effective in preventing uneven evaporation of the constituent elements of the compound semiconductor substrate, thereby preventing variations in electrical characteristics.
（へ）発明の効果
以上のように本発明によれはイオン注入済の熱処理すべ
き化合物半導体基板の表面に誘電体保護膜を設け、上記
熱処理すべき化合物半導体基板を２枚の上記熱処理すべ
き化合物半導体基板と同種の基板の間にはさみ、上記イ
オン注入による注入原子の活性化温度にて上記注入原子
の活性化のための熱処理が行なわれる。(F) Effects of the Invention As described above, according to the present invention, a dielectric protective film is provided on the surface of the ion-implanted compound semiconductor substrate to be heat-treated, and the two compound semiconductor substrates to be heat-treated are It is sandwiched between a compound semiconductor substrate and a substrate of the same type, and heat treatment is performed to activate the implanted atoms at the activation temperature of the implanted atoms by the ion implantation.
これにより、熱処理される化合物半導体基板の表側およ
び裏側面を被覆し蒸気圧の高い一部構成元素の蒸発を抑
制するための誘電体保護膜が熱処理される化合物半導体
基板と同種の別の基板と密着するため、温度上昇下降時
に誘電体保護膜にかかる温度差ひずみが小さくなり、し
たがって誘電体保護膜の破れ等の恐れが小さくなる。ま
た、たとえ熱処理中に破れ等が生じても熱処理される化
合物半導体基板をはさむ別の同種の基板から発生する構
成元素の蒸気圧により熱処理される化合物半導体基板表
面には高い圧力がかけられるため誘電体保護膜の破れ等
を通じての構成元素の蒸発が防止される。かくして化合
物半導体基板の構成元素の不均一蒸発か防止されるため
化合物半導体基板面内での電気的特性のばらつきが防止
される。As a result, a dielectric protective film that covers the front and back sides of the compound semiconductor substrate to be heat-treated and suppresses evaporation of some constituent elements with high vapor pressure is applied to another substrate of the same type as the compound semiconductor substrate to be heat-treated. Since they are in close contact, the temperature difference strain applied to the dielectric protective film when the temperature rises and falls is reduced, and therefore the risk of breakage of the dielectric protective film is reduced. In addition, even if breakage occurs during heat treatment, high pressure is applied to the surface of the compound semiconductor substrate to be heat-treated due to the vapor pressure of constituent elements generated from other substrates of the same type sandwiching the compound semiconductor substrate to be heat-treated, so dielectric Evaporation of the constituent elements through breakage of the body protective film is prevented. In this way, non-uniform evaporation of the constituent elements of the compound semiconductor substrate is prevented, thereby preventing variations in electrical characteristics within the plane of the compound semiconductor substrate.
さらに、熱処理中に熱処理される化合物半導体基板表面
に蒸気圧を生じさせる蒸発源が熱処理される化合物半導
体基板と同種の２枚の基板であるため、取扱いが簡便で
作業性、安全性上の問題をなくすことができる。Furthermore, since the evaporation source that generates vapor pressure on the surface of the compound semiconductor substrate to be heat-treated during heat treatment is two substrates of the same type as the compound semiconductor substrate to be heat-treated, handling is simple and there are problems with workability and safety. can be eliminated.
第１図は本発明の化合物半導体基板の熱処理方法を示す
図、第２図はＧａＡｓウエノ・を２枚のＧａ、Ａ ｓ基
板ではさまず冗熱処理した後の表面荒れを示す説明図、
第６図はＧａＡｓウエノ・を本発明の方法に従って熱処
理した後の表面状態を示す説明図、第４図はキャリア分
布の比較を示すグラフである。
１・・熱処理すべき化合物半導体基板
２・・誘電体保護膜
ろ、４・・熱処理すべき化合物半導体基板と同種の基板
特許出願人住友電気工業株式会社
（外４名）
第２図
第４図
表面ｐ゛燵蛤ｔ、ａｍ）FIG. 1 is a diagram showing the heat treatment method for a compound semiconductor substrate of the present invention, and FIG. 2 is an explanatory diagram showing surface roughness after redundant heat treatment of GaAs wafer sandwiched between two Ga and As substrates.
FIG. 6 is an explanatory diagram showing the surface state of GaAs wafer after heat treatment according to the method of the present invention, and FIG. 4 is a graph showing a comparison of carrier distribution. 1. Compound semiconductor substrate to be heat treated 2. Dielectric protective film 4. Substrate of the same type as the compound semiconductor substrate to be heat treated Patent applicant Sumitomo Electric Industries, Ltd. (4 others) Figure 2 Figure 4 surface p゛燵蛤t, am)
Claims (1)
表面に誘電体保護膜を設け、該熱処理すべき化合物半導
体基板を２枚の該熱処理すべき化合物半導体基板と同種
の基板の間にはさみ、該イオン注入による注入原子の活
性化温度にて該注入原子の活性化のための熱処理を行な
うことを特徴とする化合物半導体基板の熱処理方法。 （２）該２枚の該熱処理すべき化合物半導体基板と同種
の基板が一蹴体保護膜を有しないことを特徴とする請求 導体基板の熱処理方法。 （３）該２枚の該熱処理すべき化合物半導体基板と同種
の基板が誘電体保護膜を有することを特徴とする特許請
求の範囲第１項に記載の化合物半導体基板の熱処理方法
。[Claims] (11) A dielectric protective film is provided on the surface of the compound semiconductor substrate to be heat-treated in the ion implantation tube, and the compound semiconductor substrate to be heat-treated is separated from two substrates of the same type as the compound semiconductor substrates to be heat-treated. A method for heat treatment of a compound semiconductor substrate, characterized by performing heat treatment for activating the implanted atoms at the activation temperature of the implanted atoms by the ion implantation. (2) The heat treatment of the two substrates. A heat treatment method for a conductor substrate, characterized in that the substrate of the same type as the compound semiconductor substrate to be heat-treated does not have a single-layer protective film. (3) The two substrates of the same type as the compound semiconductor substrate to be heat-treated are dielectric. 2. The method of heat treating a compound semiconductor substrate according to claim 1, further comprising a protective film.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP59004053A JPS60148129A (en) | 1984-01-12 | 1984-01-12 | Heat treatment of compound semiconductor substrate |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP59004053A JPS60148129A (en) | 1984-01-12 | 1984-01-12 | Heat treatment of compound semiconductor substrate |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS60148129A true JPS60148129A (en) | 1985-08-05 |
Family
ID=11574139
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP59004053A Pending JPS60148129A (en) | 1984-01-12 | 1984-01-12 | Heat treatment of compound semiconductor substrate |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS60148129A (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP0216285A2 (en) * | 1985-09-20 | 1987-04-01 | Sumitomo Electric Industries, Ltd. | Method of annealing a compound semiconductor substrate |
| JP2011176336A (en) * | 2005-06-20 | 2011-09-08 | Nippon Telegr & Teleph Corp <Ntt> | Diamond semiconductor element and method for forming the same |
-
1984
- 1984-01-12 JP JP59004053A patent/JPS60148129A/en active Pending
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP0216285A2 (en) * | 1985-09-20 | 1987-04-01 | Sumitomo Electric Industries, Ltd. | Method of annealing a compound semiconductor substrate |
| JP2011176336A (en) * | 2005-06-20 | 2011-09-08 | Nippon Telegr & Teleph Corp <Ntt> | Diamond semiconductor element and method for forming the same |
| JP2011176337A (en) * | 2005-06-20 | 2011-09-08 | Nippon Telegr & Teleph Corp <Ntt> | Diamond semiconductor element and method for manufacturing the same |
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