JPS60227416A - Annealing method of semiconductor substrate - Google Patents
Annealing method of semiconductor substrateInfo
- Publication number
- JPS60227416A JPS60227416A JP8459084A JP8459084A JPS60227416A JP S60227416 A JPS60227416 A JP S60227416A JP 8459084 A JP8459084 A JP 8459084A JP 8459084 A JP8459084 A JP 8459084A JP S60227416 A JPS60227416 A JP S60227416A
- Authority
- JP
- Japan
- Prior art keywords
- annealing
- gaas substrate
- implanted
- ions
- atmosphere
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/26—Bombardment with radiation
- H01L21/263—Bombardment with radiation with high-energy radiation
- H01L21/265—Bombardment with radiation with high-energy radiation producing ion implantation
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明はイオン注入したガリウム砒素(GaAsと記す
)基板のアニール方法に関するものである。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a method of annealing a gallium arsenide (hereinafter referred to as GaAs) substrate into which ions have been implanted.
近年、半導体集積回路の高速化を目的として、GaAs
半導体を動作層に用いるGaAs集積回路の開発が活発
に行われている。GaAs集積回路の基本素子としては
電界効果トランジスタが一般に用いられているが、かか
る素子の動作層の形成方法として、その均一性、制御性
、量産的見地からイオン注入法が用いられている。イオ
ン注入法においては、注入時に導入された結晶欠陥の回
復および注入不純物の電気的活性化のためにイオン注入
後に熱処理工程を必要とし、GmAs+の場合には、G
aAsが熱分解を起こす700〜900℃の温度で数十
分間の熱処理が通常行われている。かかる熱処理中のG
aAsの熱分解を抑える方法として、現在大別して2通
シの方法が用いられている。ひとつはGaAa表面を保
護膜で覆って熱処理する所謂キヤツジ・アニール法、も
うひとつはKasahara et al、がJ、Ap
pl、Phys、50 。In recent years, GaAs has been used for the purpose of speeding up semiconductor integrated circuits.
GaAs integrated circuits using semiconductors as active layers are being actively developed. Field effect transistors are generally used as basic elements of GaAs integrated circuits, and ion implantation is used as a method for forming the active layer of such elements from the viewpoints of uniformity, controllability, and mass production. In the ion implantation method, a heat treatment step is required after ion implantation to recover crystal defects introduced during implantation and to electrically activate implanted impurities.
Heat treatment for several tens of minutes is usually performed at a temperature of 700 to 900° C. at which aAs undergoes thermal decomposition. G during such heat treatment
Currently, two methods are used to suppress the thermal decomposition of aAs. One is the so-called cage annealing method, in which the GaAa surface is covered with a protective film and heat-treated, and the other is Kasahara et al.
pl, Phys, 50.
P、541(1979)で述べている様にアニール雰囲
気中にAs圧を印加する所謂キャラブレス・アニール法
である。前者の方法は、GaAa表面からのAsの蒸発
を表面に被着した保護膜によって物理的に防止しようと
するものであシ、熱分解の防止法としては最も簡便に行
える利点を有するが、その反面、集積回路製造上の見地
からみると、保護膜の形成および除去工程が余分に必要
となシ、製造工程が複雑になるという欠点を有している
。As described in P., 541 (1979), this is the so-called Charabres annealing method in which As pressure is applied in the annealing atmosphere. The former method attempts to physically prevent the evaporation of As from the GaAa surface by using a protective film attached to the surface, and has the advantage of being the simplest method for preventing thermal decomposition. On the other hand, from the viewpoint of manufacturing integrated circuits, this method has the disadvantage that it requires an extra process of forming and removing a protective film, which complicates the manufacturing process.
また、イオン注入層の特性についても使用する保護膜の
性質によシ影響を受けることが知られておシ、例えば保
護膜として二酸化シリコン(sio□)を用いた場合に
は、熱処理工程中にGaAs構成元素であるGaが5I
O2中を外部拡散し、GaAsのストイキオメ) IJ
が大きくずれるために注入された不純物の活性化率が高
くならないという欠点を有しておシ、保護膜として窒化
シリコン(5t3N4)を用いた場合には、GaAsと
S i 、N4の間の大きな熱膨張係数の違いにより界
面に熱応力が生じ、これが注入不純物やGaA*結晶中
に添加されたCr原子の異常拡散を生じ、注入不純物分
布の均一性、制御性を悪化させるという欠点を有してい
た。一方、後者の方法であるキャップレス・アニール法
では、キャップ・アニール法でみられた様な保護膜/G
aAs界面で生じる種々の問題を回避でき、しかも保護
膜の形成や除去のための工程を必要としないため、集積
回路の製造工程が簡略化できる長所を有しているが、ア
ニール雰囲気中へのAsの供給源として、通常猛毒ガス
であるアルシン(AsH3)を多量に用いる必要があり
、量産性の見地からみるとその安全性に大きな問題を残
しているのが現状である。It is also known that the characteristics of the ion-implanted layer are affected by the properties of the protective film used. For example, when silicon dioxide (SIO□) is used as the protective film, during the heat treatment process, Ga, a constituent element of GaAs, is 5I
GaAs stoichiometry (IJ) by external diffusion in O2
However, when silicon nitride (5t3N4) is used as a protective film, there is a large gap between GaAs, Si, and N4. Thermal stress occurs at the interface due to the difference in thermal expansion coefficients, which causes abnormal diffusion of implanted impurities and Cr atoms added to the GaA* crystal, which has the disadvantage of deteriorating the uniformity and controllability of the implanted impurity distribution. was. On the other hand, in the latter method, the capless annealing method, the protective film/G
It has the advantage of simplifying the manufacturing process of integrated circuits because various problems that occur at the aAs interface can be avoided, and there is no need for a process for forming or removing a protective film. As a source of As, it is usually necessary to use a large amount of arsine (AsH3), which is a highly poisonous gas, and from the standpoint of mass production, there are currently major safety issues.
本発明の目的は、キャップレス・アニールにおける上記
安全性に関する欠点を取シ除き、アニール雰囲気KAg
圧を印加することなく、GaAs基板のキャップレス・
アニールを実現する方法を提供することにある。The purpose of the present invention is to eliminate the above-mentioned safety defects in capless annealing, and to
Capless production of GaAs substrates without applying pressure
The objective is to provide a method for realizing annealing.
本発明は少なくともアンモニアガスを含む雰囲気中でイ
オン注入し九GaA−基板に熱処理を施すことを特徴と
する半導体基板のアニール方法である。The present invention is a method of annealing a semiconductor substrate, which is characterized by performing ion implantation in an atmosphere containing at least ammonia gas and subjecting the GaA substrate to heat treatment.
以下に本発明を実験事実とともに実施例を用いて説明す
る。使用した基板は面方位(100)のLEC(Lig
uid Ineapaulat+al Czoahra
lakl )法アンドープGaAs基板でオシ、室温で
Siイオンを100に・■でドース量5 X 101
2cm−2注入した。本発明の実施例として、このイオ
ンを注入した試料に100チの純アンモニアガス、おる
いは窒素と純アンモニアの混合ガス(体積比5:l)雰
囲気中で800℃、15分間の熱処理を施す実験を行っ
た。上記アニール条件の下では、アニール後のGILA
11表面にAsの蒸発による熱ピットの発生や表面窒化
物の生成は認められなかった。800℃での純アンモニ
ア、あるいは窒素/アンモニア混合ガス雰囲気でのアニ
ールにおいて、表面に反応生成物やAaの熱分解が生じ
ない原因は現在のところ不明であるが、アンモニアガス
の熱分解によシ生じたV族元素である窒素(N)が同じ
くv族元素であるAsの蒸発を抑える効果があることが
予想される。The present invention will be explained below using experimental facts and examples. The substrate used was LEC (Lig) with plane orientation (100).
uid Ineapaulat+al Czoahra
Lakl ) method Si ions were added to an undoped GaAs substrate at room temperature at a dose of 5 x 101.
2 cm −2 was injected. As an example of the present invention, a sample implanted with these ions is subjected to heat treatment at 800°C for 15 minutes in an atmosphere of 100 cm of pure ammonia gas, or a mixed gas of nitrogen and pure ammonia (volume ratio 5:l). We conducted an experiment. Under the above annealing conditions, the GILA after annealing
No thermal pits or surface nitrides were observed on the surface of No. 11 due to evaporation of As. The reason why reaction products and thermal decomposition of Aa do not occur on the surface during annealing at 800°C in a pure ammonia or nitrogen/ammonia mixed gas atmosphere is currently unknown. It is expected that the generated nitrogen (N), which is a group V element, has the effect of suppressing the evaporation of As, which is also a group V element.
純アンモニアガス雰囲気でアニールした試料についてホ
ール測定を行った結果、シートキャリア濃度3.13X
1012am−2、シート移動度3620cm2/V、
escが得られ、アンモニアガス雰囲気におけるキヤ。As a result of Hall measurement on a sample annealed in a pure ammonia gas atmosphere, the sheet carrier concentration was 3.13X.
1012 am-2, sheet mobility 3620 cm2/V,
esc was obtained, and the air in an ammonia gas atmosphere was obtained.
ルス・アニールによシ、従来のキャ+、+ f・アニー
ルやAs圧印加のキャップレス・アニールに比較しても
遜色のない特性が得られることが確認された。It has been confirmed that the rus annealing provides comparable characteristics compared to conventional capless annealing, +f annealing, and capless annealing that applies As pressure.
以上説明したように、本発明によるアニール法によれば
、従来のキャップ・アニール法に比べて製造工程の大幅
な短縮が可能であj’、As圧印加のキャップレス・ア
ニール法のもつ長所を保有したまま、AsHsガスに比
べて極めて安全度の高いアニール雰囲気ガスの使用によ
り同様の効果を期待することができる効果を有するもの
である。As explained above, the annealing method according to the present invention can significantly shorten the manufacturing process compared to the conventional cap annealing method, and has the advantages of the capless annealing method using As pressure application. Similar effects can be expected by using an annealing atmosphere gas which is extremely safe compared to AsHs gas.
Claims (1)
オン注入したガリウム砒素基板に熱処理を施すことを特
徴とする半導体基板のアニール方法。(1) A method for annealing a semiconductor substrate, which comprises subjecting a gallium arsenide substrate into which ions have been implanted to heat treatment in an atmosphere containing at least ammonia gas.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP8459084A JPS60227416A (en) | 1984-04-26 | 1984-04-26 | Annealing method of semiconductor substrate |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP8459084A JPS60227416A (en) | 1984-04-26 | 1984-04-26 | Annealing method of semiconductor substrate |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS60227416A true JPS60227416A (en) | 1985-11-12 |
Family
ID=13834886
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP8459084A Pending JPS60227416A (en) | 1984-04-26 | 1984-04-26 | Annealing method of semiconductor substrate |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS60227416A (en) |
Cited By (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS6482619A (en) * | 1987-09-25 | 1989-03-28 | Nec Corp | Heat treatment |
JPS6482618A (en) * | 1987-09-25 | 1989-03-28 | Nec Corp | Heat treatment |
US5616947A (en) * | 1994-02-01 | 1997-04-01 | Matsushita Electric Industrial Co., Ltd. | Semiconductor device having an MIS structure |
-
1984
- 1984-04-26 JP JP8459084A patent/JPS60227416A/en active Pending
Cited By (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS6482619A (en) * | 1987-09-25 | 1989-03-28 | Nec Corp | Heat treatment |
JPS6482618A (en) * | 1987-09-25 | 1989-03-28 | Nec Corp | Heat treatment |
US5616947A (en) * | 1994-02-01 | 1997-04-01 | Matsushita Electric Industrial Co., Ltd. | Semiconductor device having an MIS structure |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
US4615766A (en) | Silicon cap for annealing gallium arsenide | |
US6436848B1 (en) | Method for forming nitrogen-rich silicon oxide-based dielectric materials | |
US3556879A (en) | Method of treating semiconductor devices | |
JPS618931A (en) | Manufacture of semiconductor device | |
JPS60227416A (en) | Annealing method of semiconductor substrate | |
US4820651A (en) | Method of treating bodies of III-V compound semiconductor material | |
JPS6164126A (en) | Heat treatment of group iii-v compound semiconductor | |
JPH0480880B2 (en) | ||
JPS6130030A (en) | Method of annealing multi-element semiconductor | |
JPH0513408A (en) | Manufacture of semiconductor device | |
EP0023925B1 (en) | Method of producing insulating film for semiconductor surfaces and semiconductor device with such film | |
JPH0697664B2 (en) | Compound semiconductor annealing method | |
JPS6039825A (en) | Formation of semiconductor active layer | |
JPS58103122A (en) | Manufacture of compound semiconductor device | |
JPH01235333A (en) | Heat treatment of iii-v compound semiconductor | |
JPH0480878B2 (en) | ||
JPH0494120A (en) | Manufacture of semiconductor device | |
JPS60173844A (en) | Manufacture of semiconductor element | |
JPS6195515A (en) | Forming of semiconductor active layer | |
JPS607715A (en) | Manufacture of compound semiconductor device | |
JPS62177930A (en) | High speed oxidation method for semiconductor substrate | |
JPS603124A (en) | Annealing method of compound semiconductor | |
JPH02291119A (en) | Heat treatment method for compound semiconductor substrate | |
JPH0131291B2 (en) | ||
JPS62277736A (en) | Heat treatment method for compound semiconductor |