JPS6039825A - Formation of semiconductor active layer - Google Patents
Formation of semiconductor active layerInfo
- Publication number
- JPS6039825A JPS6039825A JP58147531A JP14753183A JPS6039825A JP S6039825 A JPS6039825 A JP S6039825A JP 58147531 A JP58147531 A JP 58147531A JP 14753183 A JP14753183 A JP 14753183A JP S6039825 A JPS6039825 A JP S6039825A
- Authority
- JP
- Japan
- Prior art keywords
- implanted
- gaas
- ion
- active layer
- layer
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/26—Bombardment with radiation
- H01L21/263—Bombardment with radiation with high-energy radiation
- H01L21/265—Bombardment with radiation with high-energy radiation producing ion implantation
Abstract
Description
【発明の詳細な説明】
本発明は化合物半導体中にイオン注入せしめた後これを
活性化して半導体活性層を形成する方法に関するもので
ある。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a method for forming a semiconductor active layer by implanting ions into a compound semiconductor and activating the same.
近年、半導体集積回路(ICと略す)の高速化を目的と
して、化合物半導体例えばガリウム砒素(GaAsと略
す)を半導体として用いたいわゆる化合物半導体ICの
開発が各所で活発に行なわれている。かかる化合物半導
体ICの一例として(bAsIcについて説明する。G
aAsICの製作においては、GaAs I Cの基本
素子である電界効果トランジスタ、ダイオード等の高性
能化を図るために、高い移動度を有する動作層および低
抵抗を実現する高キャリア濃度層の形成方法の開発に大
きな努力が注がれている。従来、かかる動作層、高キャ
リア濃度層の形成方法として、その均一性、制御性、量
産的見地から、イオン注入法が用いられている。一般に
イオン注入法においては、注入した不純物を活性化する
ために、熱処理工程を必要とし、GaAsの場合には、
GaAsが熱分解する700℃から900℃の温度で5
分間から20分間の熱処理を必要とする。かかる熱分解
を押えるため、GaAsの表面にシリコンナイト2イド
(8i0yと略す)やシリコンナイト2イド(B j
a N4と略す)等の絶R膜を被着して熱処理すること
が行なわれているが5insを保護膜として用いた場合
には、熱処理工程の間にGaが510wを通りぬけて拡
散し、飛散し、 GaAsのストイキオメトリが大きく
ずれるだめに注入された不純物の活性化率が高くならな
い欠点を有しておシ、一方、Sis N4を保穫膜とし
て用いた場合、GaAsと5isN+との間の大きな熱
膨張係数の違いによυこれらの間に大きな歪を生じ、同
様に注入され/C不純物の活性化率が高くならない欠点
を有していた。In recent years, with the aim of increasing the speed of semiconductor integrated circuits (abbreviated as IC), so-called compound semiconductor ICs using compound semiconductors, such as gallium arsenide (abbreviated as GaAs), have been actively conducted in various places. As an example of such a compound semiconductor IC (bAsIc will be explained.
In the production of aAs IC, in order to improve the performance of field effect transistors, diodes, etc., which are the basic elements of GaAs IC, we have developed a method for forming an active layer with high mobility and a high carrier concentration layer that achieves low resistance. Great efforts are being put into development. Conventionally, an ion implantation method has been used as a method for forming such active layers and high carrier concentration layers from the viewpoint of uniformity, controllability, and mass production. Generally, ion implantation requires a heat treatment process to activate the implanted impurities, and in the case of GaAs,
5 at temperatures between 700°C and 900°C, where GaAs thermally decomposes.
Requires heat treatment for 20 minutes to 20 minutes. In order to suppress such thermal decomposition, siliconite 2ide (abbreviated as 8i0y) and siliconite 2ide (B j
A heat treatment is performed by depositing an absolute R film such as N4), but when 5ins is used as a protective film, Ga diffuses through 510W during the heat treatment process. This has the drawback that the activation rate of the implanted impurity cannot be increased unless the stoichiometry of GaAs is scattered and the stoichiometry of GaAs is greatly shifted. Due to the large difference in thermal expansion coefficient between υ, a large strain occurs between them, and the activation rate of the /C impurity implanted in the same manner cannot be increased.
本発明の目的は前記化合物半尋体中にイオン注入された
不純を高い活性化率をもって活性化することができる半
導体活性層の形成方法を提供するととKある。An object of the present invention is to provide a method for forming a semiconductor active layer that can activate impurities ion-implanted into the compound semiconducting body with a high activation rate.
本発BAKよれば化合物牛導体基板に不純物をイオン注
入せしめた後これを熱処理によって活性化せしめて半導
体活性層を形成する方法において、少なくともイオン注
入後の前記熱処理時に前記化合物半導体基板表面がシリ
コンオキシナイトライド膜で覆われている状態で熱処理
を行なうことを特徴とする半導体活性層の形成方法が得
られる。According to the BAK of the present invention, in a method of forming a semiconductor active layer by implanting impurity ions into a compound semiconductor substrate and activating it by heat treatment, at least during the heat treatment after ion implantation, the surface of the compound semiconductor substrate is exposed to silicon oxide. A method for forming a semiconductor active layer is obtained, which is characterized in that heat treatment is performed while covered with a nitride film.
前記本発明は本発明者の新しい実験事実に基づいてなさ
れたものである。次に本発明について第】図、第2図を
用いて具体的に説明する。第1図、(a)〜(c)は本
発明の一実施例を説明するだめの図である。寸ず、第1
図(a)に示すように、半絶縁性G a As基板1に
、該GaAs基板1中で−4,電形不計り物となシうる
不純物例えばシリコン(Siと略す)をある条件で注入
し、イオン注入層2を形成する。The present invention has been made based on new experimental findings by the inventor. Next, the present invention will be specifically explained using FIGS. FIG. 1, (a) to (c) are diagrams for explaining one embodiment of the present invention. Sunzu, 1st
As shown in Figure (a), an impurity, such as silicon (abbreviated as Si), which can become a -4, electrically undesirable substance in the GaAs substrate 1, is implanted under certain conditions into a semi-insulating GaAs substrate 1. Then, an ion implantation layer 2 is formed.
次に、第1図(b)に示すように、イオン注入層2を覆
うように例えを;rモノシラン(S目14と略す)−ア
ンモニアIIH,と略す)−酸素(Oz!:FP’lす
)なる反応系において、熱分解法により、例えばGaA
s基板温度650℃でシリコンオキシナイトライド(S
IOxNy)膜3を形成した後、B o o ”c、1
5分閥の熱処理を行ない、第x+v(aに示すように注
入された不純物Siを活性化させてイオン注入層(第1
図(al、(b12)をGaAs活性層4に変える。前
記シリコンオキシナイト2イド(SiOxNy)を形成
する8iH4NHs Osなる反応系においては5iH
L、[13に対する0、の流旦比を変えることによ、j
)8i0xNyのX・、yの値をそ′れぞれ0がら2ま
で、0がら−iまで変えることができ、この時、それぞ
れ形成されたSiOxNyの屈折率は1.45より2.
0まで変化する。Next, as shown in FIG. 1(b), the ion-implanted layer 2 is covered with monosilane (abbreviated as S 14) - ammonia IIH) - oxygen (Oz!: FP'l). In the reaction system, for example, GaA
s Silicon oxynitride (S) at a substrate temperature of 650°C
After forming the IOxNy) film 3, B o o ”c, 1
Heat treatment is performed in 5 sections to activate the implanted impurity Si as shown in x+v (a) and form the ion-implanted layer (first
Figures (al and b12) are changed to GaAs active layer 4. In the reaction system of 8iH4NHsOs that forms silicon oxynitride (SiOxNy), 5iH
By changing the flux ratio of 0 to L, [13, j
) The values of X and y of 8i0xNy can be changed from 0 to 2 and from 0 to -i, respectively, and at this time, the refractive index of the formed SiOxNy will be from 1.45 to 2.
Changes to 0.
そこでS i i(a −NHs −Oxなる反応系に
より成長されたシリコンオキシナイトライド(SIOx
Ny)膜を用いてGaAs基板中に形成されたSiイオ
ン注入層を活性化させた場合の注入不純物Stの活性化
率のSiOxNyの屈折率依存性を第2図に示す、第2
図において縦軸は活性化率、横軸はA11Fr率nであ
シ、’8i0xNy中の0(酸素)に対するN(窒紫)
の割合が大きくなるに従って屈折率nは大きくなる。Therefore, silicon oxynitride (SIOx
Figure 2 shows the dependence of the activation rate of the implanted impurity St on the refractive index of SiOxNy when a Si ion-implanted layer formed in a GaAs substrate is activated using a Ny) film.
In the figure, the vertical axis is the activation rate, the horizontal axis is the A11Fr rate n, and N (nitrogen purple) for 0 (oxygen) in '8i0xNy.
As the ratio of n increases, the refractive index n increases.
810tの屈折本社1,45、aimN番の屈折率は2
.0である。第2図において、曲線Aは半絶縁性GaA
s基板に5aSH+を150 keyのエネルギーで、
ドース量7 X 10”tyn→注入した場合の注入不
純物S1の活性化率の保護膜のM折率n依存性を、曲線
Bは同様100kevのエネルギーで、ドースft5X
10’!cn1→注入した場合のものであり、曲線Aは
、GaAsICにおいては高キヤリア濃度層形成に、曲
線Bは動作層形成に用いられる6第2図の実a事実が示
すように、シリコンオキシナイトライド(8i 0xN
y)KよってGaAs基板面を覆って熱処理した場合注
入された81は高い活性率を示し、例えば、屈折率18
のシリコ;/オキシナイトライド(S i 0xNy
)を用いた場合には、従来の報告された最高ピークキャ
リア濃度2 X 10 ”cm ’に比べて50’16
高い3X101’cm−”を得たつかかる高い活性化率
が得られる原困としては次の4丁項が考えられる。810t refraction head 1, 45, aimN number refractive index is 2
.. It is 0. In Figure 2, curve A is semi-insulating GaA
5aSH+ on s substrate with 150 key energy,
Curve B shows the dependence of the activation rate of the implanted impurity S1 on the M refraction index n of the protective film when implanted at a dose of 7 x 10" tyn. Similarly, at an energy of 100 kev, the dose ft5
10'! cn1 → injection, curve A is used for forming a high carrier concentration layer in GaAs IC, and curve B is used for forming an active layer. (8i 0xN
y) When the GaAs substrate surface is covered with K and heat treated, the implanted 81 exhibits a high activity rate, for example, a refractive index of 18
silico;/oxynitride (S i 0xNy
), compared to the previously reported maximum peak carrier concentration of 2
The following four conditions can be considered as the reasons why such a high activation rate can be obtained.
(1) 8i0=はOaを通し熱処理中GaAsのスト
イキオメトリ−を大きく変えるだめG a A sの結
晶性が劣化し、また、8 i 0xはτ!(処理中G
RA sに用層1−1応カを生じせしめ、枚伯シ、てL
l:、入不純物であるSiの活性化率が土がら外い。(1) 8i0= does not significantly change the stoichiometry of GaAs during heat treatment through Oa, which deteriorates the crystallinity of GaAs, and 8i0x has τ! (Processing G
This causes a layer 1-1 stress on the RA s, and the
l: The activation rate of Si, which is an impurity, is higher than that of soil.
(2) S is N4はOa:b・よひAsを熱処理
中Kngを通して拡散させることはないだめ、GaAs
の結晶性を劣化させることLl、ないが、5raNaは
熱処理中GaAsK引張9応力を生じ、1勺しめて、注
入不hqtDであるSlの活性化率が上がら丘い。(2) S is N4 should not diffuse Oa:b/yohi As through Kng during heat treatment; GaAs
Although it does not degrade the crystallinity of Ll, 5raNa causes tensile stress in GaAsK during heat treatment, which increases the activation rate of Sl, which is not implanted.
(3)一方SiOxNyは5iO−と5rsNaの両方
の中間の性質すなわち、S i OwよシGaの膜中拡
散を押えることがてきGaAs中のGaの空孔を適度に
生じせしめるため、Gaサイトに入って11形不純物ど
なるSiの活性化を助けると共に、SiOxNyの熱膨
張率がGaA、sと近くなυ圧縮応力および引張り応力
を共に生じせしめることがないために81の活性化率が
高くなる。このよう(先本発明(でよれば化合1−半導
体中にイオン注入せしめた不純物を高い活性化率をもっ
て活性化することができ、従来の欠点を完全に解決せし
めた半導体活性層の形成方法が実現される。前記本発明
は化合物半導体として、GaAsだけでなく、他の化合
物半導体に対しても適用可能でちる。(3) On the other hand, SiOxNy has properties intermediate between both 5iO- and 5rsNa, i.e., SiOx can suppress the diffusion of Ga in the film, and generates an appropriate amount of Ga vacancies in GaAs. The activation rate of 81 is increased because SiOxNy has a coefficient of thermal expansion similar to that of GaA, and does not cause both υ compressive stress and tensile stress. As described above, according to the present invention (Compound 1), there is a method for forming a semiconductor active layer that can activate impurities ion-implanted into a semiconductor with a high activation rate and completely solves the conventional drawbacks. The present invention is applicable not only to GaAs but also to other compound semiconductors.
理した場合について示したがこれ以外に例えば、最初に
基板表面を覆うようにシリコンオキシナイトライド膜を
形成し、該シリコンオキシナイトライド膜を通してイオ
ン注入を行ない、そのままシリコンオキシナイトライド
膜で覆った状態で熱処理を行う、いわゆるスルー注入に
おいても同様な効果を得た。In addition to this, for example, a silicon oxynitride film is first formed to cover the substrate surface, ions are implanted through the silicon oxynitride film, and the substrate is then covered with a silicon oxynitride film. A similar effect was obtained in so-called through implantation, in which heat treatment is performed in the state.
でキ図において、1は半絶縁性GaAs、S板、2はイ
オン注入層、3は保W5m、4はG a As活性層を
示す。In the diagram, 1 is a semi-insulating GaAs, S plate, 2 is an ion implantation layer, 3 is a holding W5m, and 4 is a GaAs active layer.
第2図は本発明の効果を示す図で、図においてAは”S
i+を150KeVで7 X 10” Crn−”注入
した場合Bは100KeVで5×101!cd注入した
g合の活性化率の屈折率依存性を示す。FIG. 2 is a diagram showing the effect of the present invention. In the diagram, A is “S”.
When i+ is implanted at 150 KeV and 7 x 10"Crn-", B is 5 x 101 at 100 KeV! The dependence of the activation index on the refractive index of the CD-implanted g compound is shown.
/“
(す1人ブ団11 内 原 +jjf(”、 、1範1
図
第 2 図/“ (S1 person group 11 Uchihara +jjf(”, , 1 range 1
Figure 2
Claims (1)
れを熱処理によって活性化せしめて半導体活性層を形成
する方法において、少なく七もイオン注入後の前記熱処
理時に前記化合物半導体基板表面がシリコンオキシナイ
トライド膜で覆われている状態で熱処理を行なうことを
特徴とする半導体活性層の形成方法。In a method for forming a semiconductor active layer by ion-implanting impurities into a compound semiconductor substrate and then activating the impurities by heat treatment, at least seven times the surface of the compound semiconductor substrate is formed into a silicon oxynitride film during the heat treatment after ion implantation. 1. A method for forming a semiconductor active layer, the method comprising performing heat treatment while covered with a semiconductor active layer.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP58147531A JPS6039825A (en) | 1983-08-12 | 1983-08-12 | Formation of semiconductor active layer |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP58147531A JPS6039825A (en) | 1983-08-12 | 1983-08-12 | Formation of semiconductor active layer |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS6039825A true JPS6039825A (en) | 1985-03-01 |
Family
ID=15432414
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP58147531A Pending JPS6039825A (en) | 1983-08-12 | 1983-08-12 | Formation of semiconductor active layer |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS6039825A (en) |
Cited By (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS63170253A (en) * | 1986-04-08 | 1988-07-14 | デンツプライ リミテッド | Glass/poly(carboxylic acid) cement composition |
JPH0496232A (en) * | 1990-08-04 | 1992-03-27 | Sumitomo Electric Ind Ltd | Heat treatment method for compound semiconductor wafer |
US5141879A (en) * | 1989-08-28 | 1992-08-25 | Herbert Goronkin | Method of fabricating a FET having a high trap concentration interface layer |
-
1983
- 1983-08-12 JP JP58147531A patent/JPS6039825A/en active Pending
Cited By (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS63170253A (en) * | 1986-04-08 | 1988-07-14 | デンツプライ リミテッド | Glass/poly(carboxylic acid) cement composition |
US5141879A (en) * | 1989-08-28 | 1992-08-25 | Herbert Goronkin | Method of fabricating a FET having a high trap concentration interface layer |
JPH0496232A (en) * | 1990-08-04 | 1992-03-27 | Sumitomo Electric Ind Ltd | Heat treatment method for compound semiconductor wafer |
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