JPS607715A - Manufacture of compound semiconductor device - Google Patents
Manufacture of compound semiconductor deviceInfo
- Publication number
- JPS607715A JPS607715A JP11554383A JP11554383A JPS607715A JP S607715 A JPS607715 A JP S607715A JP 11554383 A JP11554383 A JP 11554383A JP 11554383 A JP11554383 A JP 11554383A JP S607715 A JPS607715 A JP S607715A
- Authority
- JP
- Japan
- Prior art keywords
- compound semiconductor
- substrate
- group
- vapor phase
- impurity
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 150000001875 compounds Chemical class 0.000 title claims abstract description 22
- 239000004065 semiconductor Substances 0.000 title claims abstract description 22
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 8
- 239000000758 substrate Substances 0.000 claims abstract description 41
- 238000000034 method Methods 0.000 claims abstract description 21
- 238000010438 heat treatment Methods 0.000 claims abstract description 13
- 238000005530 etching Methods 0.000 claims abstract description 12
- 238000001947 vapour-phase growth Methods 0.000 claims abstract description 10
- 239000007789 gas Substances 0.000 claims description 18
- 229920006395 saturated elastomer Polymers 0.000 claims description 7
- 229910021478 group 5 element Inorganic materials 0.000 claims description 5
- 238000005468 ion implantation Methods 0.000 claims description 5
- 238000006243 chemical reaction Methods 0.000 claims description 4
- UFHFLCQGNIYNRP-UHFFFAOYSA-N Hydrogen Chemical compound [H][H] UFHFLCQGNIYNRP-UHFFFAOYSA-N 0.000 claims description 3
- 239000001257 hydrogen Substances 0.000 claims description 3
- 229910052739 hydrogen Inorganic materials 0.000 claims description 3
- VEXZGXHMUGYJMC-UHFFFAOYSA-M Chloride anion Chemical compound [Cl-] VEXZGXHMUGYJMC-UHFFFAOYSA-M 0.000 claims description 2
- 238000011144 upstream manufacturing Methods 0.000 claims description 2
- 239000012535 impurity Substances 0.000 abstract description 22
- 229910001218 Gallium arsenide Inorganic materials 0.000 abstract description 17
- 238000009826 distribution Methods 0.000 abstract description 7
- 150000002500 ions Chemical class 0.000 abstract description 6
- 230000004913 activation Effects 0.000 abstract description 3
- OEYOHULQRFXULB-UHFFFAOYSA-N arsenic trichloride Chemical compound Cl[As](Cl)Cl OEYOHULQRFXULB-UHFFFAOYSA-N 0.000 abstract description 3
- 239000012808 vapor phase Substances 0.000 abstract description 3
- 229910017009 AsCl3 Inorganic materials 0.000 abstract 1
- JBRZTFJDHDCESZ-UHFFFAOYSA-N AsGa Chemical compound [As]#[Ga] JBRZTFJDHDCESZ-UHFFFAOYSA-N 0.000 description 16
- 239000011651 chromium Substances 0.000 description 6
- 238000002513 implantation Methods 0.000 description 4
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 3
- 230000001681 protective effect Effects 0.000 description 3
- 230000001133 acceleration Effects 0.000 description 2
- 230000003213 activating effect Effects 0.000 description 2
- RBFQJDQYXXHULB-UHFFFAOYSA-N arsane Chemical compound [AsH3] RBFQJDQYXXHULB-UHFFFAOYSA-N 0.000 description 2
- VYZAMTAEIAYCRO-UHFFFAOYSA-N Chromium Chemical compound [Cr] VYZAMTAEIAYCRO-UHFFFAOYSA-N 0.000 description 1
- GPXJNWSHGFTCBW-UHFFFAOYSA-N Indium phosphide Chemical compound [In]#P GPXJNWSHGFTCBW-UHFFFAOYSA-N 0.000 description 1
- 229910052581 Si3N4 Inorganic materials 0.000 description 1
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 1
- 229910052785 arsenic Inorganic materials 0.000 description 1
- RQNWIZPPADIBDY-UHFFFAOYSA-N arsenic atom Chemical compound [As] RQNWIZPPADIBDY-UHFFFAOYSA-N 0.000 description 1
- 229910000070 arsenic hydride Inorganic materials 0.000 description 1
- 229910052804 chromium Inorganic materials 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 239000013078 crystal Substances 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 238000009792 diffusion process Methods 0.000 description 1
- 238000010494 dissociation reaction Methods 0.000 description 1
- 230000005593 dissociations Effects 0.000 description 1
- 238000002474 experimental method Methods 0.000 description 1
- 150000002258 gallium Chemical class 0.000 description 1
- 239000007943 implant Substances 0.000 description 1
- 229910052738 indium Inorganic materials 0.000 description 1
- APFVFJFRJDLVQX-UHFFFAOYSA-N indium atom Chemical compound [In] APFVFJFRJDLVQX-UHFFFAOYSA-N 0.000 description 1
- 238000002347 injection Methods 0.000 description 1
- 239000007924 injection Substances 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 230000003647 oxidation Effects 0.000 description 1
- 238000007254 oxidation reaction Methods 0.000 description 1
- 231100000614 poison Toxicity 0.000 description 1
- 230000007096 poisonous effect Effects 0.000 description 1
- 239000002244 precipitate Substances 0.000 description 1
- 238000012827 research and development Methods 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
- 235000012239 silicon dioxide Nutrition 0.000 description 1
- 239000000377 silicon dioxide Substances 0.000 description 1
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Junction Field-Effect Transistors (AREA)
- Recrystallisation Techniques (AREA)
Abstract
Description
【発明の詳細な説明】
本発明は、特に化合物半導体基板へイオン注入によシ形
成した不純物注入層を活性化するための熱処理方法に関
する。DETAILED DESCRIPTION OF THE INVENTION The present invention particularly relates to a heat treatment method for activating an impurity implantation layer formed by ion implantation into a compound semiconductor substrate.
近年、化合物半導体とりわけ■−ｖ族化族化合物半導体
−用電子デバイスの生産は急激に増加して２シ、また最
近ではＩＣ化への要請が急速に高まり、特に砒化ガリウ
ム（ＧｏＡｓ）のＩＣ化の研究開発が世界的にすすめら
れている。In recent years, the production of electronic devices for compound semiconductors, especially ■-V group compound semiconductors, has rapidly increased.Recently, the demand for ICs has increased rapidly, especially for gallium arsenide (GoAs). Research and development is being promoted worldwide.
ＩＣ製造のためには半導体基板中に導電性もしくは絶縁
性の層全厚さ及び濃度を制御性よく形成する必要がめ９
、そのためには不純物のイオン注入を行い、注入された
不純物層を電気的に活性化させるための熱処理技術が不
可欠である。例えば、クロム（Ｃｒ）ドープ半絶縁性Ｇ
ａＡｓ基板にＮ温感電層全形成するには、不純物イオン
としてシリコン（Ｓ ｉ＋） ｋ １００ｋｅｖ程度の
加速エネルギーで注入して不純物注入層を形成し、注入
時に生じた結晶欠陥の回復及びドナーの活性化のために
８００℃。In order to manufacture ICs, it is necessary to form a conductive or insulating layer in a semiconductor substrate with good control over the total thickness and concentration9.
For this purpose, it is essential to implant impurity ions and to use a heat treatment technique to electrically activate the implanted impurity layer. For example, chromium (Cr) doped semi-insulating G
To form a complete N-temperature electrosensitive layer on an aAs substrate, silicon (Si+) is implanted as an impurity ion with an acceleration energy of about 100 keV to form an impurity implantation layer, and the crystal defects generated during implantation are recovered and the donor is activated. 800℃ for oxidation.
３０分程度の熱処理を行う。しかしながら、ＧａＡｓは
熱的に不安定すなわち高温では分解しやすく、熱処理時
に砒素（Ａｓ）の蒸発が起きるという性質がめる。そこ
で、Ａｓの解離を抑制するために、従来、 ＧａＡｓ表
面に二酸化ケイ素（８１０ｚ ） ＊窒化ケイ素（８ｉ
ｘＮｙ ）等の保護膜を設けて熱処理する方法、もし
くはアルシン（ＡｓＨｌ）ガスを導入してＡｓ分圧を形
成した雰囲気中で熱処理する方法がとられてきた。Heat treatment is performed for about 30 minutes. However, GaAs is thermally unstable, that is, it easily decomposes at high temperatures, and arsenic (As) evaporates during heat treatment. Therefore, in order to suppress the dissociation of As, silicon dioxide (810z) *silicon nitride (8i) was conventionally applied to the GaAs surface.
A method has been adopted in which a protective film such as xNy) is provided and heat treatment is performed, or a method is performed in which arsine (AsHl) gas is introduced to create an As partial pressure.
しかしながら、前者の方法の場合、ＧａＡｓ基板と保護
膜とで熱膨張係数が異なるために基板と保護膜との界面
にストレスが生じ、この結果、界面に向って拡散係数の
大きいＣｒ が析出してくるといういわゆるＣｒの再分
布が生ずる。この様にドナー補償型不純物でろるＣｒの
基板中での再分布が生じると、活性化された注入ドナー
不純物の濃度分布のバラツキと深さ方向のダレ、特に基
板表面での濃度低下が顕著となる。しかも、Ｏｒの再分
布程度は基板中のＣｒ量、ストレスの大きさ等制御困難
な要因に支配されているため、イオン注入層の不純物濃
度分布は再現性の乏しいものであった。一方、後者の方
法の場合、上述の問題は小さいがＡｓＨ３という極めて
猛毒なガス七使用するため安全性上問題があるので好ま
しくない。However, in the case of the former method, stress occurs at the interface between the substrate and the protective film because the thermal expansion coefficients of the GaAs substrate and the protective film are different, and as a result, Cr with a large diffusion coefficient precipitates toward the interface. A so-called redistribution of Cr occurs. When redistribution of Cr occurs in the substrate due to the donor compensation type impurity, the concentration distribution of the activated implanted donor impurity varies and sag in the depth direction, especially the concentration decrease at the substrate surface becomes noticeable. Become. Moreover, since the degree of redistribution of Or is controlled by factors that are difficult to control, such as the amount of Cr in the substrate and the magnitude of stress, the impurity concentration distribution in the ion-implanted layer has poor reproducibility. On the other hand, in the case of the latter method, although the above-mentioned problem is small, it is not preferable because it uses a very poisonous gas called AsH3, which poses a safety problem.
本発明はかかる従来法の欠点？除去し、化合物半導体基
板中の不純物イオン注入層の活性化に２いて、不純物濃
度分布の不均一性をなくシ、かつ安全性上においても極
めて有効な熱処理方法を提供すること全目的としている
。Is the present invention a drawback of such conventional methods? The overall purpose of the present invention is to provide a heat treatment method that is extremely effective in removing and activating an impurity ion implanted layer in a compound semiconductor substrate, eliminating non-uniformity in impurity concentration distribution, and also in terms of safety.
すなわち、本発明は化合物基板上への気相成長および基
板のエツチングが２こらない状態にしてイオン注入層を
熱処理によシ活性化することｖｉ：％徴とする。That is, the present invention is characterized in that the ion-implanted layer is activated by heat treatment without vapor phase growth on the compound substrate and etching of the substrate.
本発明に係る化合物半導体基板の熱処理方法は、また、
イオン注入法により形成された区−ｖ族化合物半導体基
板中の不純物注入層を熱処理する方法において、ガス送
入管を有する反応容器のガス上流側ｌＣｖ族元素を飽和
させた■族元素、ガス下流側に前記■−ｖ族化合９勿半
導体基板ｔそれぞれ配置し、前記Ｖ族元素全飽和させた
ｌ族元素の温度を前記■−ｖ族化合物半導体基板のそれ
とほぼ等しくした状態で前記ガス送入管よりｖ族元素の
塩化物と水素の混合ガスを導入することを特徴とする。The method for heat treatment of a compound semiconductor substrate according to the present invention also includes:
In a method of heat treating an impurity implanted layer in a group V compound semiconductor substrate formed by an ion implantation method, a group III element saturated with an ICv group element on the gas upstream side of a reaction vessel having a gas inlet pipe, and a gas downstream The above ■-V group compound semiconductor substrate t is placed on the side, and the gas is introduced while the temperature of the I group element, which is fully saturated with the V group element, is approximately equal to that of the above ■-V group compound semiconductor substrate. It is characterized by introducing a mixed gas of chloride of group V elements and hydrogen through a tube.
以下図にもとづいて本発明を詳述する。The present invention will be explained in detail below based on the figures.
第１図は本発明に係るＣｒ ドープ半絶縁性ＧａＡｓ基
板に不純物イオンｓｉ＋２加速エネルギー８Ｑｋｅｖ。FIG. 1 shows an impurity ion Si+2 acceleration energy of 8 Qkev on a Cr-doped semi-insulating GaAs substrate according to the present invention.
ドース量２Ｘ１０’ｃｌｓ で注入して形成した不純物
注入層を熱処理する方法の一実施例ケ説明するための装
置の縦断面図全示しｆｃものである。同図で、１１はガ
ス送入管、１２は反応容器、１３はＡｓｉ飽和させたガ
リウム（Ｑａ）、 １４は８ｉ＋に注入したＧ ａＡｓ
基板、１５は框気炉、そして１６は三塩化砒素（ＡｓＣ
ｔａ ）と水素（Ｈ２）の混合ガスである。This is a vertical cross-sectional view of an apparatus for explaining an embodiment of a method for heat treating an impurity implanted layer formed by implanting at a dose of 2×10'cls. In the figure, 11 is a gas supply pipe, 12 is a reaction vessel, 13 is Asi-saturated gallium (Qa), and 14 is GaAs injected into 8i+.
15 is a frame furnace, and 16 is arsenic trichloride (AsC).
ta) and hydrogen (H2).
ここで、Ｇａ１３とＧａＡｓ基板１４の温度はほぼ等し
く８００℃にと９トータルガス流量は１５００ν分。Here, the temperatures of the Ga 13 and the GaAs substrate 14 are approximately equal to 800°C, and the total gas flow rate is 1500ν.
ＧａＡｓ基板１４上に３けるＡｓのモル分圧はｔｘｔｏ
、’熱処理時間は３０分である。第１図に明らかな様
に、本方法は通常のＧａ／Ａｓ Ｃ１３／Ｈ２系の気相
成長装置ｉｃ９いて、Ｇａ１３とＧａＡｓ基板１４の温
度？はぼ等しく設定することによってＧ ａ Ａｓ基板
１４上に気相成長も気相エツチングも起らない状態が出
現することを利用して熱処理を行うものでおる。The molar partial pressure of As on the GaAs substrate 14 is txto
, 'The heat treatment time is 30 minutes. As is clear from FIG. 1, this method uses an ordinary Ga/As C13/H2 type vapor phase growth apparatus IC9, and the temperature of the Ga13 and GaAs substrate 14 is 1. The heat treatment is performed by taking advantage of the fact that by setting the values to be approximately equal, a state appears on the GaAs substrate 14 in which neither vapor phase growth nor vapor phase etching occurs.
すなわち、本方法の同容を詳しく説明するために示した
のが第２図であって、ＧａＡｓ基板の温度上８００℃と
８５０℃とにした場合のＧａ温度と気相成長速度もしく
はエツチング速度の関係を示したものである。ここで、
トータルガス流量は１５０田ン分。That is, Fig. 2 is shown to explain the content of this method in detail, and shows the relationship between the Ga temperature and the vapor phase growth rate or etching rate when the temperature of the GaAs substrate is 800°C and 850°C. This shows the relationship. here,
The total gas flow rate is 150 tons.
Ｇ ａＡｓ基板上のＡｓのモル分圧１ｃ ０．５〜１．
５Ｘ１０″でめる。Molar partial pressure of As on GaAs substrate 1c 0.5-1.
Measure 5X10''.
第２図に示した様にＧａ温度上昇と共にエツチングから
成長へと変化し、ＧａＡｓ基板温度とほぼ等しい時成長
及びエツチング速度が０．すなわち成長もエツチングも
起らなくなる。この成長も工ッチングも起らない時のＧ
ａ温度は、Ｑａ中へのＡｓの飽和が不完全であると高い
温度の方向へずれるが、我々の芙験の結果２〜３℃ずれ
るだけであって再現性よく条件設定が可能でめった。As shown in FIG. 2, as the Ga temperature rises, etching changes to growth, and when the temperature is approximately equal to the GaAs substrate temperature, the growth and etching rates are 0. In other words, neither growth nor etching occurs. G when neither growth nor etching occurs
If the saturation of As in Qa is incomplete, the a temperature shifts toward a higher temperature, but as a result of our experiments, it only shifts by 2 to 3 degrees Celsius, making it possible to set the conditions with good reproducibility.
以上説明した様に本方法で用いることによってＧａＡｓ
基板中のイオン注入層（５Ａｓ分圧約ｔｘ１ｏ−３゜
温度８００Ｃ乃至８５０℃で熱処理することが出来、こ
の様にして形成したＮ型導電層の不純物濃度分布は理論
的に予測されるり、 Ｓ、 Ｓ、分布に近く、又注入し
た不純物の電気的な活性化割合に低下はなく、基板面内
の濃度分布の均−性及び再現性が大幅に同上した。As explained above, by using this method, GaAs
The ion-implanted layer (5As) in the substrate can be heat-treated at a partial pressure of about tx1o-3° and a temperature of 800°C to 850°C, and the impurity concentration distribution of the N-type conductive layer formed in this way can be predicted theoretically. There was no decrease in the electrical activation rate of the implanted impurities, and the uniformity and reproducibility of the concentration distribution within the substrate surface were significantly improved.
以上、本方法忙用いてイオン注入により形成したＧａＡ
ｓ基板中の不純物注入層を効果的に熱処理することが
出来、（３ａＡｓｌＣの製造歩留向上への寄与は極めて
顕著である。As described above, GaA formed by ion implantation using this method
The impurity implantation layer in the s-substrate can be effectively heat-treated, and the contribution to improving the manufacturing yield of 3aAslC is extremely significant.
以上、本発明はＧａＡｓ ’（例にとって説明したが、
他のＩ−Ｖ 族化合物半導体燐化インジウム（ｘｎｐ）
。As described above, the present invention has been explained using GaAs' (for example,
Other group IV compound semiconductors indium phosphide (xnp)
.
Ａ重化インジウム（ＩｎＡｓ）等ｉｃｙいても同様であ
ることは本発明の原理から明らかである。It is clear from the principle of the present invention that the same applies to icy materials such as A-weighted indium (InAs).
第１図は本発明に係る不純物ｔイオン注入しＩＣＧａＡ
ｓ基板の熱処理する方法の一例を説明するための装置の
縦断面図を示したもので、１１はガス送入管、１２は反
応容器、１３はＡｓ ｆ飽和させたＧａ、１４は不純物
全注入したＧ ａ Ａ ｓ基板、１５は電気炉、１６は
Ａ ｓ Ｃ１３とＨ２の混合ガスである。
第２図はＧ ａ Ａ ｓ基板の温度’２ ｓｏｏ℃、８
５０℃にした場合のＧａ温度と気相成長速度もしくはエ
ツチング速度の関係を示したものである。
、 ９＼
代理人 弁理士 内 原 晋 −）Figure 1 shows ICGaA with impurity t ion implantation according to the present invention.
s A vertical cross-sectional view of an apparatus for explaining an example of a method for heat-treating a substrate, 11 is a gas feed pipe, 12 is a reaction vessel, 13 is As f-saturated Ga, and 14 is a total impurity injection tube. 15 is an electric furnace, and 16 is a mixed gas of As C13 and H2. Figure 2 shows the temperature of the GaAs substrate at '2 soo℃, 8
This figure shows the relationship between Ga temperature and vapor phase growth rate or etching rate when the temperature is 50°C. , 9\Representative Patent Attorney Susumu Uchihara -)
Claims (1)
る化合物半導体基板を熱処理して該不純物注入層を活性
化させる工程上官む化合物半導体装置の製造方法におい
て、前記化合物半導体基板上への気相成長２よび前記化
合物半導体基板のエツチングが実質的に行わない状態に
して、前記熱処理？施すこと全特徴とする化合物半導体
装置の製造方法。 Ｚ 前記化合物半導体基板はｌ−Ｖ族化合物半導体基板
であり、さらにガス送入管を有する反応容器のガス上流
側にＶ族元素上飽和させた狙族元素、ガス下流側に前記
■−■族化合物半導体基板をそれぞれ配置し、前記Ｖ族
元素を飽和させた■族元素の温度を前記Ｉ−ｖ族化合物
半導体基板のそれとほぼ等しくした状態で前記ガス送入
管より■族元素の塩化物と水素の混合ガスを導入するこ
とにより、前記気相成長および前記エツチングが実質的
に行わない状態にすることを特徴とする特許請求の範囲
第１項記載の化合物半導体装置の製造方法。[Scope of Claims] 1. A method for manufacturing a compound semiconductor device which includes a step of heat-treating a compound semiconductor substrate having an impurity-implanted layer formed by an ion implantation method to activate the impurity-implanted layer. The heat treatment is carried out in a state in which vapor phase growth 2 and etching of the compound semiconductor substrate are not substantially performed. A method for manufacturing a compound semiconductor device, which is characterized by: Z The compound semiconductor substrate is a l-V group compound semiconductor substrate, and further includes a group element saturated with a group V element on the gas upstream side of a reaction vessel having a gas feed pipe, and a group element saturated with the group V element on the gas downstream side, and a group element saturated with the group V element on the gas downstream side. Compound semiconductor substrates are each arranged, and the temperature of the group (I) element saturated with the group V element is made approximately equal to that of the group I-V compound semiconductor substrate, and a chloride of the group (I) element is supplied from the gas inlet pipe. 2. The method of manufacturing a compound semiconductor device according to claim 1, wherein said vapor phase growth and said etching are substantially not performed by introducing a mixed gas of hydrogen.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP11554383A JPS607715A (en) | 1983-06-27 | 1983-06-27 | Manufacture of compound semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP11554383A JPS607715A (en) | 1983-06-27 | 1983-06-27 | Manufacture of compound semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS607715A true JPS607715A (en) | 1985-01-16 |
Family
ID=14665133
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP11554383A Pending JPS607715A (en) | 1983-06-27 | 1983-06-27 | Manufacture of compound semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS607715A (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4713354A (en) * | 1985-02-28 | 1987-12-15 | Oki Electric Industry Co., Ltd. | Method of heat treatment for reduction of dislocation density near III-V substrate surface |
| US5203975A (en) * | 1991-10-29 | 1993-04-20 | E. I. Du Pont De Nemours And Company | Process for cathodic electrodeposition of a clear coating over a conductive paint layer |
-
1983
- 1983-06-27 JP JP11554383A patent/JPS607715A/en active Pending
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4713354A (en) * | 1985-02-28 | 1987-12-15 | Oki Electric Industry Co., Ltd. | Method of heat treatment for reduction of dislocation density near III-V substrate surface |
| US5203975A (en) * | 1991-10-29 | 1993-04-20 | E. I. Du Pont De Nemours And Company | Process for cathodic electrodeposition of a clear coating over a conductive paint layer |
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