JPH01283919A - Plasma doping method - Google Patents

Plasma doping method

Info

Publication number
JPH01283919A
JPH01283919A JP11416888A JP11416888A JPH01283919A JP H01283919 A JPH01283919 A JP H01283919A JP 11416888 A JP11416888 A JP 11416888A JP 11416888 A JP11416888 A JP 11416888A JP H01283919 A JPH01283919 A JP H01283919A
Authority
JP
Japan
Prior art keywords
semiconductor substrate
oxide film
doping
crystal defects
layer
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP11416888A
Other languages
Japanese (ja)
Inventor
Osamu Ishiwatari
石渡 統
Atsushi Ueda
厚 植田
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fuji Electric Co Ltd
Original Assignee
Fuji Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fuji Electric Co Ltd filed Critical Fuji Electric Co Ltd
Priority to JP11416888A priority Critical patent/JPH01283919A/en
Publication of JPH01283919A publication Critical patent/JPH01283919A/en
Pending legal-status Critical Current

Links

Abstract

PURPOSE:To prevent the occurrence of crystal defects such as breakdown of crystal lattices, by forming an oxide film having the thickness of 10nm or more on the surface of each semiconductor substrate which is placed in a vacuum container beforehand. CONSTITUTION:An oxide film having the thickness of 10nm or more is formed on the surface of each semiconductor substrate 3 which is placed in a vacuum container 1. A region wherein defects occur due to doping is an SiO2 layer whose depth is 30nm from the surface. Crystal defects such as dislocation seldom occur in an Si layer beneath the SiO2 layer. The very thin oxide film of 10nm or more is formed on the surface of each semiconductor substrate beforehand, and plasma doping characterized by the less occurrences of the crystal defects in the surface during the doping is performed through the oxide film. In this way, the occurrences of the crystal defects in the surface layer of the semiconductor can be suppressed to the Iow rate only by said doping.

Description

【発明の詳細な説明】 〔産業上の利用分野〕 本発明は、不純物を含む雰囲気内にプラズマを発生させ
、400℃以下に保持された半導体基体に不純物を導入
するプラズマドーピング方法に関する。
DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a plasma doping method in which plasma is generated in an atmosphere containing impurities and impurities are introduced into a semiconductor substrate maintained at 400° C. or lower.

〔従来の技術〕[Conventional technology]

半導体基体にドナーまたはアクセプタとしての不純物を
導入して、所定の導電型と不純物濃度を有する半導体領
域を形成するための方法としては熱拡散法が古くから用
いられ、最近はイオン注入法も用いられるようになった
。しかし熱拡散法では、不純物濃度の均一性が良好でな
いこと、あるいは製造工程が複雑で工程時間が長いこと
などの欠点があり、またイオン注入法は、装置が高価で
あること、あるいは後工程として高温熱処理が必要であ
ることなどの欠点がある。これらの欠点を解消して、所
定の不純物を含む雰囲気を有する真空容器内に400℃
以下の所定の温度に保持された半導体基体を置き、容器
内にグロー放電を発生させて気体内に不純物を導入する
プラズマドーピング法は、本件出願人らの特許出願に係
る特開昭59−218727号公報により公知である。
Thermal diffusion has long been used as a method for introducing impurities as donors or acceptors into a semiconductor substrate to form a semiconductor region with a predetermined conductivity type and impurity concentration, and recently ion implantation has also been used. It became so. However, the thermal diffusion method has drawbacks such as poor uniformity of impurity concentration and the complicated manufacturing process, which takes a long time, while the ion implantation method has expensive equipment and There are disadvantages such as the need for high temperature heat treatment. By eliminating these drawbacks, the temperature of 400°C in a vacuum container with an atmosphere containing specified impurities was improved.
The following plasma doping method, in which a semiconductor substrate maintained at a predetermined temperature is placed and a glow discharge is generated in a container to introduce impurities into the gas, is disclosed in Japanese Patent Application Laid-Open No. 59-218727, which was filed by the applicant and others. It is known from the publication no.

〔発明が解決しようとする課題〕[Problem to be solved by the invention]

前記公報に記載されているように、プラズマドーピング
方法によればイオン注入法と異なり、導入された不純物
の濃度は半導体基体表面において最も高く、深さ方向に
減少するプロフィルを示し、その深さも500〜150
0人と極めて浅い、そのため浅い接合や浅いオーム性接
触層の形成に適している、深い接合も適切な熱処理条件
によられる。さらに、この方法はドーピング時のエネル
ギが小さいため、半導体基体表面層に結晶格子が破壊さ
れたような結晶欠陥を発生することはない。しかし、半
導体基体の表面から約30n層以内の浅いil域に転位
のような結晶欠陥が発生し、それによって結晶中に歪が
生ずるため、均一な半導体領域が形成できないという欠
点はあった。
As described in the above publication, unlike the ion implantation method, according to the plasma doping method, the concentration of the introduced impurity is highest at the surface of the semiconductor substrate and shows a profile that decreases in the depth direction, and the depth is also 500 mm. ~150
Deep junctions, which are extremely shallow and therefore suitable for forming shallow junctions and shallow ohmic contact layers, also depend on appropriate heat treatment conditions. Furthermore, since this method requires low energy during doping, crystal defects such as crystal lattice destruction do not occur in the surface layer of the semiconductor substrate. However, crystal defects such as dislocations occur in the shallow il region within about 30n layers from the surface of the semiconductor substrate, and this causes distortion in the crystal, resulting in a drawback that a uniform semiconductor region cannot be formed.

本発明の課題は、上記の欠点を除いて半導体基体表面層
にそのような種類の結晶欠陥の発生を無くするか、ある
いは僅少の発生にとどめるプラズマドーピング方法を提
供することにある。
An object of the present invention is to provide a plasma doping method that eliminates the above-mentioned drawbacks and eliminates the occurrence of such types of crystal defects in the surface layer of a semiconductor substrate, or minimizes the occurrence thereof.

〔課題を解決するための手段〕[Means to solve the problem]

上記の課題の解決のために、本発明のプラズマドーピン
グ方法は、真空容器内に置かれる半導体基体の表面に予
め厚さ10nm以上の酸化膜を形成するものとする。
In order to solve the above problems, in the plasma doping method of the present invention, an oxide film with a thickness of 10 nm or more is formed in advance on the surface of a semiconductor substrate placed in a vacuum container.

〔作用〕[Effect]

10nm以上の厚さの酸化膜はドーピング時のエネルギ
のかなりの部分を吸収するので、その下の半導体基体中
での結晶欠陥の発生を抑える。
An oxide film with a thickness of 10 nm or more absorbs a significant portion of the energy during doping, thereby suppressing the generation of crystal defects in the underlying semiconductor substrate.

〔実施例〕〔Example〕

以下図を引用して本発明の一実施例について述べる。半
導体基体としてはn型で比抵抗約100Ω−の単結晶シ
リコン板を用い、その表面に1ooo℃でのドライ酸素
酸化法により膜厚30nsの酸化膜を形成した。このシ
リコン基板上に第2図に示した装置を用いて、はう素の
プラズマドーピングを行った。第2図において、真空容
器1内には下部電極21と上部1を極22が508の距
離をおいて対同配置されている。下部電極21上に上記
のように酸化膜を形成したシリコン基板3を置き、容器
l内を真空排気系4を用いて真空にし、真空度を真空計
5で測定した0次いで電源61に接続された、下部電極
21内のヒータ6によりシリコン基板反3を200℃に
保つと共に、ボンベ71からのBJiガスをボンベ72
からのキャリアガスとしてのHeガスによって調整回路
81.82を用いて11000ppに稀釈し、真空バル
ブ83により容器内の圧力を4 Torrに調整した。
An embodiment of the present invention will be described below with reference to the drawings. An n-type single-crystal silicon plate with a specific resistance of about 100 Ω was used as the semiconductor substrate, and an oxide film with a thickness of 30 ns was formed on its surface by dry oxygen oxidation at 100° C. Plasma doping of boron was performed on this silicon substrate using the apparatus shown in FIG. In FIG. 2, a lower electrode 21 and an upper electrode 22 are disposed in the vacuum chamber 1 at a distance of 508. The silicon substrate 3 on which the oxide film was formed as described above was placed on the lower electrode 21, the inside of the container 1 was evacuated using the evacuation system 4, and the degree of vacuum was measured with a vacuum gauge 5. In addition, the silicon substrate plate 3 is maintained at 200° C. by the heater 6 in the lower electrode 21, and the BJi gas from the cylinder 71 is transferred to the cylinder 72.
The mixture was diluted to 11,000 pp using He gas as a carrier gas from the reactor using a regulating circuit 81.82, and the pressure inside the container was adjusted to 4 Torr using a vacuum valve 83.

この状態で電源9により電極21.22間に900vの
直流電圧を印加し、2−A/−のパワーのグロー放電を
発生させ、60秒間継続した。その結果はう素がドーピ
ングされ、第1図に示すような濃度分布を示した。欠陥
の発生する領域は表面から30n−深さの5IOt層で
あり、それより下のSi層には転位などの結晶欠陥はほ
とんど発生しない、この結果、従来方法でプラズマドー
ピングした場合は20〜30μsecであった少数キャ
リアのライフタイムが100μsec以上になった。
In this state, a DC voltage of 900 V was applied between the electrodes 21 and 22 by the power source 9 to generate a glow discharge with a power of 2-A/-, which continued for 60 seconds. The results showed that boron was doped and the concentration distribution was as shown in FIG. The region where defects occur is the 5IOt layer at a depth of 30n from the surface, and crystal defects such as dislocations hardly occur in the Si layer below this.As a result, when plasma doping is performed using the conventional method, the The lifetime of minority carriers, which was previously

5ift層の厚さを30nmより薄くすると、Si層の
表面不純物は高くなるが結晶欠陥が多少Si層中に入る
。しかし5iaxrHの厚さがIon−以下、例えば自
然酸化膜のように2nmである場合にくらべてSi層中
の結晶欠陥は掻めて少なくなる。
When the thickness of the 5ift layer is made thinner than 30 nm, the surface impurities of the Si layer become high, but some crystal defects enter the Si layer. However, compared to the case where the thickness of 5iaxrH is less than Ion-, for example, 2 nm like a natural oxide film, the crystal defects in the Si layer are significantly reduced.

510□膜を形成しないで直接Siiにプラズマドーピ
ングを行い、表面から3On−程度エツチングで除去す
れば、5lli中に発生した結晶欠陥も除かれるが、S
irMをそのように正確な厚さだけ除去するようにエツ
チングを制御するのは困難である。これに対し、本発明
によって形成された5ift層を除去しようとするなら
ば、ふっ酸を用いて容易にできる。
If Si is directly plasma-doped without forming a 510□ film and removed by etching about 3On- from the surface, the crystal defects generated in 5lli will be removed, but S
It is difficult to control the etching to remove such a precise thickness of irM. On the other hand, if the 5ift layer formed according to the present invention is to be removed, it can be easily done using hydrofluoric acid.

上記の実施例では、キャリアガスとしてヘリウムを用い
たが、水素などのガスを用いた場合、またドーピング不
純物ガスとしてBtHbガス以外の他のガスを用いた場
合も同様の効果が得られる。
In the above embodiment, helium was used as the carrier gas, but similar effects can be obtained when using a gas such as hydrogen, or when using a gas other than BtHb gas as the doping impurity gas.

〔発明の効果〕〔Effect of the invention〕

本発明によれば、ドーピング時に表面結晶欠陥の発生の
少ないプラズマドーピングを半導体基体表面にIon−
以上の極く薄い酸化膜を予め形成してその酸化膜を通し
て行うだけで、さらに半導体表面層での結晶欠陥の発生
を低く抑えることができる。従って不純物ドーピングに
よって製造される各種半導体素子の特性を向上させるこ
とが容易である。
According to the present invention, plasma doping, which causes fewer surface crystal defects during doping, is applied to the surface of a semiconductor substrate using Ion-
By simply forming the extremely thin oxide film described above in advance and performing the process through the oxide film, it is possible to further suppress the occurrence of crystal defects in the semiconductor surface layer. Therefore, it is easy to improve the characteristics of various semiconductor devices manufactured by impurity doping.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は本発明の一実施例によりほう素をドーピングし
た直後のほう素の深さ方向濃度分布図、第2図は本発明
の実施のために用いるプラズマドーピング装置の概略構
成図である。 l:真空容器、21.22:電橋、3:シリコン基板、
6:ヒータ、71 : BzHhガスボンベ、72 :
 Heガ(4チ/am3) 第]図
FIG. 1 is a depthwise concentration distribution diagram of boron immediately after boron doping according to an embodiment of the present invention, and FIG. 2 is a schematic diagram of a plasma doping apparatus used for implementing the present invention. l: vacuum container, 21.22: electric bridge, 3: silicon substrate,
6: Heater, 71: BzHh gas cylinder, 72:
Hega (4chi/am3) Figure]

Claims (1)

【特許請求の範囲】[Claims] 1)ドーパントとして所定の不純物を含む雰囲気を有す
る真空容器内に400℃以下の温度に保持された半導体
基体を置き、前記容器内にグロー放電を発生させて半導
体基体内に不純物を導入する方法において、真空容器内
に置かれる半導体基体の表面に予め厚さ10mm以上の
酸化膜を形成することを特徴とするプラズマドーピング
方法。
1) A method in which a semiconductor substrate maintained at a temperature of 400°C or less is placed in a vacuum container having an atmosphere containing a predetermined impurity as a dopant, and a glow discharge is generated in the container to introduce the impurity into the semiconductor substrate. , a plasma doping method characterized in that an oxide film with a thickness of 10 mm or more is formed in advance on the surface of a semiconductor substrate placed in a vacuum container.
JP11416888A 1988-05-11 1988-05-11 Plasma doping method Pending JPH01283919A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP11416888A JPH01283919A (en) 1988-05-11 1988-05-11 Plasma doping method

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP11416888A JPH01283919A (en) 1988-05-11 1988-05-11 Plasma doping method

Publications (1)

Publication Number Publication Date
JPH01283919A true JPH01283919A (en) 1989-11-15

Family

ID=14630875

Family Applications (1)

Application Number Title Priority Date Filing Date
JP11416888A Pending JPH01283919A (en) 1988-05-11 1988-05-11 Plasma doping method

Country Status (1)

Country Link
JP (1) JPH01283919A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7858537B2 (en) 2003-09-08 2010-12-28 Panasonic Corporation Plasma processing method and apparatus
JP2016122769A (en) * 2014-12-25 2016-07-07 東京エレクトロン株式会社 Doping method and manufacturing method of semiconductor element

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6114762A (en) * 1984-06-29 1986-01-22 Toshiba Corp Manufacture of thin film field effect transistor

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6114762A (en) * 1984-06-29 1986-01-22 Toshiba Corp Manufacture of thin film field effect transistor

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7858537B2 (en) 2003-09-08 2010-12-28 Panasonic Corporation Plasma processing method and apparatus
US8288259B2 (en) 2003-09-08 2012-10-16 Panasonic Corporation Plasma processing method and apparatus
US8404573B2 (en) 2003-09-08 2013-03-26 Panasonic Corporation Plasma processing method and apparatus
JP2016122769A (en) * 2014-12-25 2016-07-07 東京エレクトロン株式会社 Doping method and manufacturing method of semiconductor element

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