JPS6037122A - Annealing method of semiconductor substrate - Google Patents
Annealing method of semiconductor substrateInfo
- Publication number
- JPS6037122A JPS6037122A JP14477783A JP14477783A JPS6037122A JP S6037122 A JPS6037122 A JP S6037122A JP 14477783 A JP14477783 A JP 14477783A JP 14477783 A JP14477783 A JP 14477783A JP S6037122 A JPS6037122 A JP S6037122A
- Authority
- JP
- Japan
- Prior art keywords
- substrate
- semiconductor substrate
- annealing
- section
- temperature
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000000758 substrate Substances 0.000 title claims abstract description 53
- 239000004065 semiconductor Substances 0.000 title claims abstract description 38
- 238000000137 annealing Methods 0.000 title claims description 22
- 238000000034 method Methods 0.000 title claims description 16
- 239000006096 absorbing agent Substances 0.000 claims abstract description 3
- 238000010438 heat treatment Methods 0.000 claims abstract description 3
- OKTJSMMVPCPJKN-UHFFFAOYSA-N Carbon Chemical compound [C] OKTJSMMVPCPJKN-UHFFFAOYSA-N 0.000 abstract description 9
- 229910052799 carbon Inorganic materials 0.000 abstract description 9
- 230000017525 heat dissipation Effects 0.000 abstract description 6
- 230000002093 peripheral effect Effects 0.000 abstract description 6
- JBRZTFJDHDCESZ-UHFFFAOYSA-N AsGa Chemical compound [As]#[Ga] JBRZTFJDHDCESZ-UHFFFAOYSA-N 0.000 description 3
- 229910001218 Gallium arsenide Inorganic materials 0.000 description 3
- 238000010521 absorption reaction Methods 0.000 description 3
- 238000007796 conventional method Methods 0.000 description 3
- 238000010586 diagram Methods 0.000 description 3
- 239000012535 impurity Substances 0.000 description 3
- 230000008646 thermal stress Effects 0.000 description 3
- 238000005468 ion implantation Methods 0.000 description 2
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 1
- 239000013078 crystal Substances 0.000 description 1
- 238000009792 diffusion process Methods 0.000 description 1
- 230000005669 field effect Effects 0.000 description 1
- 229910052736 halogen Inorganic materials 0.000 description 1
- 150000002367 halogens Chemical class 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 230000003287 optical effect Effects 0.000 description 1
- 230000002250 progressing effect Effects 0.000 description 1
- 230000000630 rising effect Effects 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/26—Bombardment with radiation
- H01L21/263—Bombardment with radiation with high-energy radiation
- H01L21/265—Bombardment with radiation with high-energy radiation producing ion implantation
Landscapes
- Physics & Mathematics (AREA)
- High Energy & Nuclear Physics (AREA)
- Engineering & Computer Science (AREA)
- Health & Medical Sciences (AREA)
- Toxicology (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Recrystallisation Techniques (AREA)
Abstract
Description
【発明の詳細な説明】
本発明は半導体基板のアニール方法、詳しくは赤外線照
射による高温短時間のアニール時にかかる熱応力に起因
するスリップ線(結晶の弁開方向に沿って走る転位線)
の発生を抑えることを可能にする半導体基板のアニール
方法に関するものである。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a method for annealing a semiconductor substrate, and more specifically, slip lines (dislocation lines running along the valve opening direction of a crystal) caused by thermal stress applied during high temperature and short time annealing using infrared irradiation.
The present invention relates to a semiconductor substrate annealing method that makes it possible to suppress the occurrence of .
近年、イオン注入技術を用いてシリコン基板やガリウム
砒素(以後、GaAsと記す)基板上に高集積で高性能
な集積回路の開発が進められている。In recent years, development of highly integrated and high-performance integrated circuits on silicon substrates and gallium arsenide (hereinafter referred to as GaAs) substrates has been progressing using ion implantation technology.
これらの集積回路は半導体基板上に形成されたn形ある
いはP形の導電層の上に電界効果トランジスタ、ダイオ
ード等の基本素子を集積化することにより作製されるが
、該集積回路のより一層の高性能化のためには、線審に
制御された不純物濃度分布の形成が不可欠である。These integrated circuits are manufactured by integrating basic elements such as field effect transistors and diodes on an n-type or p-type conductive layer formed on a semiconductor substrate. In order to improve performance, it is essential to form an impurity concentration distribution controlled by the linesman.
最近、イオン注入後のアニール法トシて、ハロゲン・ラ
ンプ等の赤外線照射を用のる高温短時間のアニール方法
が研究されている。該アニール法を用いれば、従来の電
気炉アニール法に比べ半導体中の不純物の熱拡散を少な
く抑えることが可能であり、急峻な不純物分布の形成が
可能となる。Recently, a high-temperature, short-time annealing method using infrared irradiation from a halogen lamp or the like has been studied as an annealing method after ion implantation. By using this annealing method, thermal diffusion of impurities in a semiconductor can be suppressed to a lower level than in the conventional electric furnace annealing method, and a steep impurity distribution can be formed.
しかしながら、この赤外線照射短時間アニールにおいて
は、急速な昇温工程中に半導体基板の中心部と周辺部に
熱勾配が生じ、これによる熱応力が原因となって、半導
体基板の周辺部にスリップ線が発生する現象が、しばし
ばみられている。However, in this short-time annealing with infrared irradiation, a thermal gradient occurs between the center and the periphery of the semiconductor substrate during the rapid temperature rising process, and the resulting thermal stress causes slip lines at the periphery of the semiconductor substrate. This phenomenon is often observed.
半導体基板間内の熱勾配は半導体基板の中光部と周辺部
で熱吸収し熱放散の様子が異なるために生じるものであ
る。Thermal gradient between semiconductor substrates occurs because heat is absorbed and heat is dissipated differently in the central and peripheral areas of the semiconductor substrate.
第1図は半導体基板面内での熱の吸収および放散の様子
を模式的に示したものである。1は入射熱、2は放散熱
、3は半導体基板を示す。入射熱は殆んどが試料面に垂
直に入射する平行赤外線より供給されるため、熱吸収は
主に半導体基板の主平面部で起こり、基板端面部からの
熱吸収は横方向からの熱入射が少ないだめ、非常に少な
い。FIG. 1 schematically shows how heat is absorbed and dissipated within the plane of a semiconductor substrate. 1 indicates incident heat, 2 indicates dissipated heat, and 3 indicates a semiconductor substrate. Most of the incident heat is supplied by parallel infrared rays that are incident perpendicularly to the sample surface, so heat absorption mainly occurs at the main plane of the semiconductor substrate, and heat absorption from the edge of the substrate is caused by heat incident from the lateral direction. There are very few, very few.
これに対し熱放散は半導体基板の主平面部、端面部を問
わず全表面的に一様に起こる。赤外線照射による短時間
アニールではアニールによる温度上昇が被アニール試料
において、はぼ選択的に生じアニール雰囲気の温度上昇
は非常に小さいため半導体基板のアニール雰囲気からの
熱吸収は殆んどない。したがって、半導体基板の主平面
部と端面部での熱吸収および熱放散状態の違いは、その
まま半導体基板面内での湛度不均−となって表われる。On the other hand, heat dissipation occurs uniformly over the entire surface of the semiconductor substrate, regardless of whether it is a main plane or an end surface. In short-time annealing using infrared irradiation, the temperature increase due to annealing occurs selectively in the annealed sample, and the temperature increase in the annealing atmosphere is very small, so that almost no heat is absorbed from the annealing atmosphere by the semiconductor substrate. Therefore, the difference in the state of heat absorption and heat dissipation between the main plane part and the end face part of the semiconductor substrate directly appears as non-uniformity of coverage within the plane of the semiconductor substrate.
その結果、第2図に示すように赤外線照射による短時間
アニールにより半導体基板をアニールすると、半導体基
板の中心部に比べ、周辺部の温度上昇が少なく、その温
度勾配による熱応力により基板周辺部にスリップ線が発
生する。As a result, as shown in Figure 2, when a semiconductor substrate is annealed by short-time annealing using infrared irradiation, the temperature rise at the periphery is smaller than that at the center of the semiconductor substrate, and thermal stress due to the temperature gradient causes a rise in temperature at the periphery of the substrate. A slip line occurs.
本発明の目的は、前記半導体基板の中心部と周辺部の温
度勾配に基づくスリップ線の発生を抑え半導体基板全面
に渡って均質なアニールを施すことを可能とする半導体
基板のアニール方法を提供することにある。An object of the present invention is to provide a method for annealing a semiconductor substrate, which makes it possible to suppress the occurrence of slip lines due to the temperature gradient between the center and periphery of the semiconductor substrate and to perform uniform annealing over the entire surface of the semiconductor substrate. There is a particular thing.
本発明の特徴は、赤外線照射により半導体基板に高温短
時間の熱処理を施す下程において、前記半導体基板の周
囲を赤外線吸収体で囲った状態で加熱する点にある。A feature of the present invention resides in that, in the process of performing high-temperature, short-time heat treatment on a semiconductor substrate by infrared irradiation, the semiconductor substrate is heated while being surrounded by an infrared absorber.
以下に、本発明の内容を実験事実とともに実施例を用い
て説明する。The content of the present invention will be explained below using experimental facts and examples.
第3図は従来方法を第4図は本発明になる方法を説明す
るための図である。第3図、第4図において、4は赤外
線ランプ、5は赤外線反射鏡、6は基板保持具、7はカ
ーボン薄板である。カーボン薄板で半導体試料を囲うこ
とにより、半導体基板の端面部からの横方向の熱放散は
接触しているカーボン薄板からの熱放散と相殺するため
、半導体基板面内の昇温特性は基板の中心部と周辺部で
同一にすることが可能となり、基板周辺部でれスリップ
線の発生を防止することができる。半導体基板を囲う材
料としてカーボンを用いる理由は、加工性が良いため、
基板の形に合わせて容易に円形あるいはD形に加工でき
ることにある。カーボン薄板の厚さとじては1〜1.5
朋程度が適当であり、表面は8iCコートしておくのが
望ましい。FIG. 3 is a diagram for explaining the conventional method, and FIG. 4 is a diagram for explaining the method according to the present invention. In FIGS. 3 and 4, 4 is an infrared lamp, 5 is an infrared reflector, 6 is a substrate holder, and 7 is a thin carbon plate. By surrounding the semiconductor sample with a carbon thin plate, the lateral heat dissipation from the edge of the semiconductor substrate is offset by the heat dissipation from the contacting carbon thin plate, so the temperature rise characteristic within the semiconductor substrate plane is reduced to the center of the substrate. This makes it possible to make the area and the peripheral area the same, and it is possible to prevent the occurrence of slip lines at the peripheral area of the substrate. The reason why carbon is used as a material surrounding the semiconductor substrate is because it has good processability.
The advantage is that it can be easily processed into a circular or D-shape to match the shape of the substrate. The thickness of the carbon thin plate is 1 to 1.5.
The surface is preferably coated with 8iC.
本発明になる方法を用いて21nchφのGaAs基板
に950℃、4秒間の短時間アニールを行った結果、従
来方法で1はアニール後の基板表面に最大5闘を越える
スリップ線の発生がみられたものが光学顕Wt、鏡によ
る観察においても全くスリップ線は検出されず、本方法
の有用性が実証された。As a result of short-time annealing at 950° C. for 4 seconds on a 21-nchφ GaAs substrate using the method of the present invention, slip lines of more than 5 lines were observed on the substrate surface after annealing using the conventional method. No slip lines were detected even when observed using an optical microscope (Wt) or a mirror, demonstrating the usefulness of this method.
本発明になるアニール法を用いることにより半導体基板
面内の特性の均一性が向上し、一枚の半導体基板面内で
の有効面積を広くとることが可能By using the annealing method of the present invention, it is possible to improve the uniformity of characteristics within the plane of the semiconductor substrate, and to increase the effective area within the plane of one semiconductor substrate.
第1図は、半導体基板面内での熱の吸収および放散の様
子を示す図、第2図は赤外線照射短時間アニール時に半
導体基板面内に生じる温LW勾配を示す図、第3図は従
来法における半導体基板の保持部を示す断面図、第4図
は本発明になるアニール方法における半導体基板の保持
部を示す断面図である。
図において、1は入射熱、2は放散熱、3は半導体基板
、4は赤外線ランプ、5は赤外線反射鏡6け基板保持具
、7はカーボン薄板をそれぞれ示す。
第3図
第牛図Figure 1 shows how heat is absorbed and dissipated in the plane of a semiconductor substrate, Figure 2 shows the temperature LW gradient that occurs in the plane of the semiconductor substrate during short-time annealing with infrared irradiation, and Figure 3 shows the conventional method. FIG. 4 is a sectional view showing a holding part for a semiconductor substrate in an annealing method according to the present invention. In the figure, 1 indicates incident heat, 2 indicates dissipated heat, 3 indicates a semiconductor substrate, 4 indicates an infrared lamp, 5 indicates a substrate holder with 6 infrared reflectors, and 7 indicates a thin carbon plate. Figure 3 Cow diagram
Claims (1)
す工程において、前記半導体基板の周囲を赤外線吸収体
で囲った状態で加熱することを特徴とする半導体基板の
アニール方法。1. A method of annealing a semiconductor substrate, characterized in that, in the step of subjecting a semiconductor substrate to high-temperature, short-time heat treatment by infrared irradiation, the semiconductor substrate is heated while being surrounded by an infrared absorber.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP14477783A JPS6037122A (en) | 1983-08-08 | 1983-08-08 | Annealing method of semiconductor substrate |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP14477783A JPS6037122A (en) | 1983-08-08 | 1983-08-08 | Annealing method of semiconductor substrate |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS6037122A true JPS6037122A (en) | 1985-02-26 |
Family
ID=15370186
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP14477783A Pending JPS6037122A (en) | 1983-08-08 | 1983-08-08 | Annealing method of semiconductor substrate |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS6037122A (en) |
Cited By (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS6099109A (en) * | 1983-10-13 | 1985-06-03 | Tokuyama Sekisui Kogyo Kk | Removal of scale attached to polymerizer |
US4752592A (en) * | 1985-11-29 | 1988-06-21 | Matsushita Electric Industrial Co., Ltd. | Annealing method for compound semiconductor substrate |
US4754117A (en) * | 1985-03-25 | 1988-06-28 | Sony Corporation | Annealing method by irradiation of light beams |
-
1983
- 1983-08-08 JP JP14477783A patent/JPS6037122A/en active Pending
Cited By (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS6099109A (en) * | 1983-10-13 | 1985-06-03 | Tokuyama Sekisui Kogyo Kk | Removal of scale attached to polymerizer |
JPS6246562B2 (en) * | 1983-10-13 | 1987-10-02 | Tokuyama Sekisui Kogyo Kk | |
US4754117A (en) * | 1985-03-25 | 1988-06-28 | Sony Corporation | Annealing method by irradiation of light beams |
US4752592A (en) * | 1985-11-29 | 1988-06-21 | Matsushita Electric Industrial Co., Ltd. | Annealing method for compound semiconductor substrate |
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