JPS61207016A - Formation of gallium arsenide conductive layer - Google Patents

Formation of gallium arsenide conductive layer

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Publication number
JPS61207016A
JPS61207016A JP4772985A JP4772985A JPS61207016A JP S61207016 A JPS61207016 A JP S61207016A JP 4772985 A JP4772985 A JP 4772985A JP 4772985 A JP4772985 A JP 4772985A JP S61207016 A JPS61207016 A JP S61207016A
Authority
JP
Japan
Prior art keywords
gaas
conductive layer
implantation
gallium arsenide
ion implantation
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP4772985A
Other languages
Japanese (ja)
Inventor
Kazuo Nakamura
和夫 中村
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Priority to JP4772985A priority Critical patent/JPS61207016A/en
Publication of JPS61207016A publication Critical patent/JPS61207016A/en
Pending legal-status Critical Current

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Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/26Bombardment with radiation
    • H01L21/263Bombardment with radiation with high-energy radiation
    • H01L21/265Bombardment with radiation with high-energy radiation producing ion implantation

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  • Physics & Mathematics (AREA)
  • High Energy & Nuclear Physics (AREA)
  • Engineering & Computer Science (AREA)
  • Health & Medical Sciences (AREA)
  • Toxicology (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Junction Field-Effect Transistors (AREA)

Abstract

PURPOSE:To contrive improvement in crystallizability by a method wherein Si or Sn and Ga are simultaneously ion-implanted on a compound semiconductor GaAs crystal and then a heat treatment is performed thereon. CONSTITUTION:When an N-type region is going to be formed by ion-implanting IV group element which is intrinsically amphoteric impurity for GaAs, the crystallizability of GaAs can be improved without impairing the rate of activation by performing a double-implantation of Ga, double-implantation of the suitable dosage of Ga against the specific dosage of Si and Sn, and a heat treatment. When the crystallizability of GaAs conductive layer is improved, advantages such as improvement in irregularity of characteristics, improvement in controllability and the like in the manufacture of a highly efficient device such as GaAs extra high speed LSI and the like can be obtained. As a result, the GaAs conductive layer of excellent crystallizability can be formed.

Description

【発明の詳細な説明】 (産業上の利用分野) 本発明は砒化ガリウム導電層の形成方法に関する。[Detailed description of the invention] (Industrial application field) The present invention relates to a method of forming a gallium arsenide conductive layer.

(従来技術とその問題点) 化合物半導体、とりわけ砒化ガリウム(GaAs)はポ
ストシリコン材料と称され、超高速LSIの開発が急速
に進められている。その中の一つのM’lな要素技術と
してイオン注入技術がある。GaAsを始めとする化合
物半導体へのイオン注入技術は。
(Prior art and its problems) Compound semiconductors, especially gallium arsenide (GaAs), are called post-silicon materials, and the development of ultrahigh-speed LSIs is progressing rapidly. Ion implantation technology is one of the M'l elemental technologies. Ion implantation technology for compound semiconductors including GaAs.

シリコン(81)へのイオン注入技術がほぼ確立された
技術であるのに対し%まだ十分に確立されているとは言
えず、特に化合物半導体に特有の化学量論的組成に関わ
る問題がある。
Although ion implantation technology into silicon (81) is almost an established technology, it cannot be said to be fully established yet, and there are problems particularly related to stoichiometric composition specific to compound semiconductors.

従来、この化学1に論的組成の問題を解決する試みとし
て、不純物となる元素のイオン注入時に。
Conventionally, as an attempt to solve this theoretical composition problem in chemistry 1, when ions of elements to be impurities were implanted.

化合物半導体の構成元素を同時に注入するいわゆる二重
注入が行なわれてきている。典型的な例Fi。
So-called double implantation, in which constituent elements of a compound semiconductor are implanted simultaneously, has been carried out. Typical example Fi.

補出らがラディエイシlン イフェクツ(Radiat
ionEffects) IE48巻、1980年、9
1頁に報告しているように、GaAsの 8eとGaの
二重注入であり、この二重注入により8eを単独で注入
する場合と比べ活性化率が向上し、ピークキャリア濃度
1.75X10  /d  が達成されている。これは
a 86はVI族元素で、  Asと置換わる事でドナ
ーとなり、この際に発生するGaの空孔がAs位置の8
Cと結びついてアクセプタを形成する傾向にあるが、G
aを同時に注入する事で、これを抑制できた為と考えら
れている。又、GaAs中で両性不純物となるGeのイ
オン注入に際しても。
Radiat Effects
ionEffects) IE Volume 48, 1980, 9
As reported on page 1, this is a double implantation of GaAs 8e and Ga, and this double implantation improves the activation rate compared to when 8e is implanted alone, and the peak carrier concentration is 1.75X10 / d has been achieved. This is because a86 is a group VI element and becomes a donor by replacing As, and the Ga vacancy generated at this time becomes a donor at the As position.
It tends to combine with C to form an acceptor, but G
It is thought that this was suppressed by simultaneously injecting a. Also, during ion implantation of Ge, which becomes an amphoteric impurity in GaAs.

1XIQ”/G7!以上の注入量で通常n型となるのに
対し、Ga1を同時に注入する事でn型は形成されずp
型となり、逆にAsを二重注入する事でn型の活性化が
増速さねる事をベドロッティらがジャーナル オプ ア
プライド フィジクス(Jour−nal of Ap
plied Physics) 51巻、1980年。
An implantation amount of 1XIQ"/G7! or higher normally results in n-type, but by simultaneously implanting Ga1, n-type is not formed and p-type is formed.
Vedrotti et al. reported in the Journal of Applied Physics that double injection of As does not accelerate n-type activation.
Plied Physics) Volume 51, 1980.

5781頁に報告している。このように、二重注入によ
って、イオン注入時の化学量論的組成の制御を図る事は
活性化率の向上に有効である事が示さねている。
It is reported on page 5781. Thus, it has not been shown that controlling the stoichiometric composition during ion implantation by double implantation is effective in improving the activation rate.

しかしながら、GaAsのデバイスのn型能@層をイオ
ン注入によって形成する場合には、必要とされるドーズ
量は高濃度層においても高々10じ伽1のオーダーのド
ーズ量であり、このドーズ量の範囲においてp型となる
Geは余り用いられない。
However, when forming an n-type active layer of a GaAs device by ion implantation, the required dose is on the order of at most 10 diodes even in a highly doped layer; Ge, which becomes p-type in this range, is rarely used.

父、デバイス特性の向上の為には、イオン注入時の損傷
をできるだけ軽減する必要からより軽い質量のイオン種
が望まね、又、イオン注入後の熱処理によって生じる注
入時のプロファイルのだ名を軽減する必要から拡散係数
の小さなイオン種が望1ねて〉す、こねらの要請から現
在では、一般に。
In order to improve device characteristics, it is necessary to reduce damage during ion implantation as much as possible, so it is desirable to use ion species with a lighter mass, and also to reduce the negative impact of the profile during implantation caused by heat treatment after ion implantation. Currently, ion species with small diffusion coefficients are desired due to the need to do so.

Siが用いらjているわけである。このSiのイオン圧
入にンいても、やはり化学量論的組成の問題がいくつか
指摘さねている。特に問題とさねてきたのは、Si庄人
後の損傷回復の為熱処理時において、保賎膜として用い
られるS iOz  中へ。
This means that Si is being used. Even with this ion implantation of Si, some problems with stoichiometric composition have not been pointed out. What has been particularly problematic is that SiOz is used as a protective film during heat treatment to recover from damage after Si treatment.

G a A sからGaが多量に外部拡散する事である
This means that a large amount of Ga diffuses outward from GaAs.

一般的にff、8iはGaAs中でGaとぢt換する事
でn型ドーパントとなり、Gaの空孔はStの活性化を
促進すると考えらねるが、上記の外部拡散量はs 8 
tがGa位置に置き換わるのに最適な量のGa空孔が生
じる量よりはるかに多く、この為に活性化率は低下し、
結晶性も悪くなる事が指摘さねている。又、GaAs基
板結晶自体についても。
In general, ff, 8i becomes an n-type dopant by exchanging with Ga in GaAs, and Ga vacancies are not considered to promote activation of St, but the above external diffusion amount is s 8
t is much larger than the optimal amount of Ga vacancies to replace the Ga positions, which reduces the activation rate.
It has been pointed out that crystallinity also deteriorates. Also, regarding the GaAs substrate crystal itself.

結晶成長時にAsの蒸発を抑える目的でAs王下におい
て成長を行なっており、この為に、でき上がった基板は
As過剰となっている事が指摘され。
In order to suppress the evaporation of As during crystal growth, growth is carried out under As conditions, and it has been pointed out that for this reason, the resulting substrate has an excess of As.

GaAsのlf:表的な深い不純物準位であるEL−2
もこの過剰Asの集合体であるとの指摘もされている。
GaAs lf: EL-2 which is a superficial deep impurity level
It has also been pointed out that this is an aggregate of excess As.

このように、化学量論的組成の不均衡が指摘されてきて
いるにもかかわらず、81イオン注入については、こね
まで二重注入の報告が余りなさねていなかった。
Despite the fact that the imbalance in stoichiometric composition has been pointed out, there have not been many reports of double implantation in 81 ion implantation until now.

(発明の目的) 本発明の目的は、砒化ガリウムにシリコン等のIV族元
素のイオン注入を行なうに際して適切な量のカリ9ムを
二重注入することによって活性化率を損うことなく結晶
性を向上させる砒化ガリウム導電層の形成方法を提供す
ることにある。
(Objective of the Invention) The object of the present invention is to improve the crystallinity of gallium arsenide without impairing the activation rate by doubly implanting an appropriate amount of potassium 9 when performing ion implantation of group IV elements such as silicon into gallium arsenide. An object of the present invention is to provide a method for forming a gallium arsenide conductive layer that improves the performance of the gallium arsenide conductive layer.

(発明の構成) 本発明の砒化ガリウム導電装の形成方法は、化合物半導
体砒化ガリウム結晶にシリコンまたは錫とガリウムとを
同時にイオン注入する工程と、前記イオン注入工程後に
熱処理を行う工程とを含んで構成される。
(Structure of the Invention) A method for forming a gallium arsenide conductive device according to the present invention includes a step of simultaneously implanting ions of silicon or tin and gallium into a compound semiconductor gallium arsenide crystal, and a step of performing heat treatment after the ion implantation step. configured.

(本発明の作用原理) 本発明は8i及びSnというGaAsに対して本来両性
不純物であるIV族元素のイオン注入を用いて、n型領
域を形成するにあたり、Gaを二重注入するという新規
な発想、及び一定の8i、81のドーズ量に対して、適
切なGaのドーズ量を二重注入して、熱処理する事によ
り活性化率を損う事な(GaAsの結晶性を向上せしめ
得る事を見い出した新規な実験事実に基づくものである
。即ち。
(Principle of operation of the present invention) The present invention uses ion implantation of group IV elements, which are essentially amphoteric impurities, into GaAs, such as 8i and Sn, to form an n-type region using a novel technique in which Ga is double-implanted. The idea is that by doubly implanting an appropriate Ga dose for a constant 8i, 81 dose and heat treatment, the activation rate will not be impaired (the crystallinity of GaAs can be improved). This is based on a new experimental fact that found that.

■族元素は、「従来技術とその問題点」の項で示したG
eの例かられかるように、Ga位置を占める事でドナー
となり、n型ドーパントとして高活性化率を得るという
観点からはGeの場合と同様にAsの二重注入が有効で
あり、Gaの二重注入はむしろ活性化率を抑制する事が
予想される訳であり、このように従来行なわれて来た二
重注入の発想からは本発明のIV族元素とGaの組み合
わせによる二重注入は容易には類推できない。
Group ■ elements are G
As can be seen from the example of e, double implantation of As is effective in the same way as in the case of Ge, from the viewpoint of obtaining a high activation rate by occupying the Ga position and becoming a donor as an n-type dopant. It is expected that double implantation will rather suppress the activation rate, and in this way, the idea of double implantation that has been carried out in the past has led to the double implantation using the combination of group IV elements and Ga of the present invention. cannot be easily inferred.

本発明の新規な発想は、単に81又は8nのGa A 
sへのイオン注入という一つのブクセスのみに注目して
いては生まれてこないものであり、「従来技術とその問
題点」で述べたように、GaAs結晶基板及びイオン注
入後のアニールエ穆を含めた全体としての結晶性の問題
点、即ち、過剰Asによる欠陥、あるいは、Gaの空孔
といった問題点をも考慮して初めて生まわてくるもので
あり1本発明では主たる目的をこの結晶性の向上に置い
ている。高活性化には必ずしも結びつかなくとも。
The novel idea of the present invention is that simply 81 or 8n Ga A
This cannot be achieved by focusing only on one process, i.e., ion implantation into s. This problem arises only by taking into consideration the problems of overall crystallinity, that is, defects caused by excess As, or Ga vacancies.The main purpose of the present invention is to improve this crystallinity. It is placed in Even if it does not necessarily lead to high activation.

結晶性の向上を図る事は特にGaAs超高速LSIなど
の高性能デバイスを作製する上では、特性のばらつきの
改善、制御性の向上等1種々の利点が生ずる事は明らか
である。後の実施例で詳述するよつにs S i又は8
nの活性化率を損う事なく結晶性を向上させ得るGaの
ドーズ量には最適値が存在するが、この最適値にかいて
、81又FiS nの活性化率を損わない範囲でGa空
孔及び過剰Mによる欠陥の回復がGaの注入とそれに引
続く熱処理で最も良く行なわれている。
It is clear that improving crystallinity brings about various advantages, such as improving property variations and improving controllability, especially when manufacturing high-performance devices such as GaAs ultrahigh-speed LSIs. s S i or 8 as detailed in later examples
There is an optimal value for the dose of Ga that can improve the crystallinity without impairing the activation rate of n, but within this optimal value, 81 or within a range that does not impair the activation rate of FiS n. Recovery of defects due to Ga vacancies and excess M is best accomplished by Ga implantation followed by heat treatment.

(実施例) 以下1本発明の実施例について1図面を参照して詳細に
説明する。
(Example) Hereinafter, an example of the present invention will be described in detail with reference to one drawing.

G a A s半絶縁性基板にGaイオンを加速エネル
ギー100keV、  ドーズ量I X 10”l 3
 X 10”。
Ga ions are accelerated on a semi-insulating substrate at an energy of 100 keV and a dose of I x 10”l 3
X 10”.

I X 10”、 3 X 101311 X 10”
/mの5種類注入し、引続き81イオンを47.5ke
Vの加速エネルギー、5 x 1012/cIdのドー
ズ量で二重に注入した試料と、Gaイオンは注入せずに
同じ条件で8iイオンだけを注入した試料の合計6種類
について% S i O2を保護膜として850C,2
0分間水素雰囲気中でブ二−ルを施した後に、ラマン散
乱を測定した。
I x 10”, 3 x 101311 x 10”
/m, followed by 81 ions at 47.5ke.
% Si O2 was protected for a total of 6 types: a sample double-implanted with an acceleration energy of V and a dose of 5 x 1012/cId, and a sample in which only 8i ions were implanted under the same conditions without implanting Ga ions. 850C,2 as a membrane
Raman scattering was measured after applying vinyl in a hydrogen atmosphere for 0 minutes.

第1図は上記6種の試料についてのラマン散乱強度を測
定した結果を示す特性図である。
FIG. 1 is a characteristic diagram showing the results of measuring the Raman scattering intensities of the six types of samples mentioned above.

292α 付近のピークはGaAsのLOフォノン振動
モードに対応したラマン散乱スペクトルであり、このピ
ークのピーク強度が大きい程、又半値幅が狭い種結晶性
が良いと考λらねる。第1図かられかるように、ピーク
強度は3X10”/c++fのドーズ量までGaイオン
の注入ドーズ量の増加と共に増加しh  I X 10
14y、メのドーズ量では減少しはじめている。即ち、
3 X 10”/Cff1のドーズ量でピーク強度II
′i最大となっており、結晶性が渚も良好になっている
と理解できる。又、同時に注入しているSiイオンのド
ーズ量に対するラマン強度の依存性は5X10”シボ 
までの範囲ではほとんど変化がない事がわかった。
The peak near 292α is a Raman scattering spectrum corresponding to the LO phonon vibration mode of GaAs, and it is considered that the larger the peak intensity of this peak, the better the seed crystallinity with a narrower half-width. As can be seen from FIG. 1, the peak intensity increases as the implantation dose of Ga ions increases up to a dose of 3X10"/c++f.
At 14y, the dose started to decrease. That is,
Peak intensity II at a dose of 3 x 10”/Cff1
'i is maximum, and it can be understood that the crystallinity is also good. Also, the dependence of Raman intensity on the dose of Si ions implanted at the same time is as follows:
It was found that there was almost no change in the range.

第2図は同じ試料についてポール測定を行ない。Figure 2 shows Pole measurement performed on the same sample.

シートキャリア濃度のGaイオン注入ドーズ量に対する
依存性を示した特性図である。
FIG. 3 is a characteristic diagram showing the dependence of sheet carrier concentration on Ga ion implantation dose.

8iイオン注入ドーズ量が5X10”、%−の場合には
3xIQ”、@!のGaイオン注入ドーズ量までシート
キャリア濃度は変化がなく、81イオン圧入ドーズ量が
5X10”シボの場合には1XIQ”9ゴのGaイオン
圧入ドーズ量まで変化がない事がわかる。こねは、これ
らのドーズ量までGaの存在はSiの活性化には影響し
ない事を示している。従って、第1図の結果と合わせて
考えるとh Siイオン圧入ドーズ量が5×10”7c
mの場合には同時にGaイオンをlX10”Al1のド
ーズ量注入し、81イオン注入ドーズ量が5 X I 
Q ” ”/Clの場合には同時に3X10/CI+!
  のGaイオンを注入し、その後に熱処理することで
81の活性化率には影響を与えずに結晶性の改善が可能
となることがわかる。
8i ion implantation dose is 5X10", 3xIQ" when %-, @! It can be seen that the sheet carrier concentration does not change up to a Ga ion implantation dose of 1XIQ''9 when the 81 ion implantation dose is 5X10'' grain. Kone has shown that the presence of Ga does not affect the activation of Si up to these doses. Therefore, when considered together with the results in Figure 1, the h Si ion implantation dose is 5 x 10"7c.
In the case of m, Ga ions are simultaneously implanted at a dose of 1×10”Al1, and the 81 ion implantation dose is 5×I
In the case of Q ” ”/Cl, 3X10/CI+ at the same time!
It can be seen that the crystallinity can be improved without affecting the activation rate of 81 by implanting Ga ions and then performing heat treatment.

本実施例はSNイオンに関してのみ行なったが、8nイ
オンについても同様の結果を得ており、Gaイオンを同
時に注入する事でh 8 nの活性化率には影響を与え
ずに結晶性の改善が実現できている。
Although this example was conducted only for SN ions, similar results were obtained for 8n ions, and simultaneous implantation of Ga ions improved crystallinity without affecting the activation rate of h8n. has been realized.

このようにして得られたn型領域はGaA3超高速LS
I を始め種々のデバイスに応用する事によって、特性
の良好な製品を得る事が期待できる。
The n-type region thus obtained is a GaA3 ultrafast LS
By applying it to various devices including I, we can expect to obtain products with good characteristics.

(発明の効果) 以上詳細に説明したように1本発明によりば。(Effect of the invention) According to one aspect of the present invention, as described in detail above.

従来の方法と比べて結晶性が良い砒化ガリウム導電層を
形成することができる。そして、この砒化ガリウム導電
層を電子デバイスの製造に適用することにより、製造工
程の制御性の向上及び製品の特性向上を図ることが可能
となる。
A gallium arsenide conductive layer with better crystallinity than conventional methods can be formed. By applying this gallium arsenide conductive layer to the manufacture of electronic devices, it is possible to improve the controllability of the manufacturing process and improve the characteristics of the product.

【図面の簡単な説明】[Brief explanation of drawings]

g1図は本発明及び従来の方法で製造したGaAs基板
の277強度のGaイオン注入ドーズ量依存性金示す特
性図、第2図は本発明及び従来の方法で製造したGaA
s基板のGaイオン注入ドース0量とシートキャリア濃
度との関係を示す特性図である。 牛[a 21y0290  3t)0 @〕皮数ンフ)(c勿−9
Figure g1 is a characteristic diagram showing the dependence of the 277 intensity on Ga ion implantation dose of GaAs substrates manufactured by the present invention and the conventional method, and Figure 2 is a characteristic diagram of GaAs substrates manufactured by the present invention and the conventional method.
FIG. 2 is a characteristic diagram showing the relationship between the zero dose of Ga ion implantation in the s-substrate and the sheet carrier concentration. Cow [a 21y0290 3t) 0 @] skin count) (c mu-9

Claims (1)

【特許請求の範囲】[Claims] 化合物半導体砒化ガリウム結晶にシリコンまたは錫とガ
リウムとを同時にイオン圧入する工程と、前記イオン注
入工程後に熱処理を行う工程とを含むことを特徴とする
砒化ガリウム導電層の形成方法。
A method for forming a gallium arsenide conductive layer, the method comprising the steps of: simultaneously ion-injecting silicon or tin and gallium into a compound semiconductor gallium arsenide crystal; and performing heat treatment after the ion implantation step.
JP4772985A 1985-03-11 1985-03-11 Formation of gallium arsenide conductive layer Pending JPS61207016A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP4772985A JPS61207016A (en) 1985-03-11 1985-03-11 Formation of gallium arsenide conductive layer

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP4772985A JPS61207016A (en) 1985-03-11 1985-03-11 Formation of gallium arsenide conductive layer

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JPS61207016A true JPS61207016A (en) 1986-09-13

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JP4772985A Pending JPS61207016A (en) 1985-03-11 1985-03-11 Formation of gallium arsenide conductive layer

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