JPH01145855A - Semiconductor integrated circuit device and manufacture thereof - Google Patents

Abstract

PURPOSE:To prevent the formation of an Si deposit on a wiring and to prevent decrease in resistance value and wire breakdown, by introducing high concentration impurities in a polycrystalline silicon film, breaking the polycrystalline property, forming an amorphous silicon film, performing heat treatment for the amorphous silicon film, and forming a single crystal silicon film. CONSTITUTION:A polycrystalline silicon film 34B is formed on the entire surface of the upper part of an interlayer insulating film 30 so that the film is brought into contact with another semiconductor region 31 through a contact hole 33. High concentration n-type impurities are introduced into the polycrystalline silicon film 34B. As the n-type impurities, e.g., high concentration P (or As) is used. When the crystals are broken, the polycrystalline silicon film 34B is transformed into an amorphous silicon film 34C. Then, the amorphous silicon film 34C is patterned into a specified shape. The patterning is performed by, e.g., anisotropic etching such as RIE. Grains are formed in the amorphous silicon film 34C from a part of a memory selecting MISFET QS, which is single crystal silicon, in contact with the other semiconductor region by heat treatment. The grains grow and the size is increased. Thus the intermediate conductor film 34, in which single crystals are formed, is provided.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a semiconductor integrated circuit device, and particularly to a technique that is effective when applied to a semiconductor integrated circuit device in which wiring is connected to a semiconductor region.

[Conventional technology]

D RAM (D dynamic anddom 8cc
The memory cell of es (Memory) is composed of a memory cell selection MISFET and an information storage capacitive element connected in series to one of the semiconductor regions.

A data line is connected to the other semiconductor region of the memory cell selection M I S FET. The data line is formed of an aluminum film or an aluminum alloy film to which Cu or Si is added.

The two memory cells arranged in the direction in which the data line extends integrally constitute (share) the other semiconductor region of each memory cell selection MISFET. In other words, the area corresponding to the field insulating film that insulates and isolates the other semiconductor region is eliminated, thereby achieving higher integration of the DRAM.

A DRAM having a large capacity which is currently being developed by the present inventor is configured as shown in FIG. 7 (a sectional view of a main part of a memory cell). In other words, the memory cell selection MISFET Qi is connected to a p° type semiconductor substrate (or well region) made of single crystal silicon.
1 main surface.

MISFETQ for memory cell selection is gate insulating film 2
．． It is composed of a gate electrode 3 and a pair of n-type semiconductor regions 5, which are a source region and a drain region. The other semiconductor region 5 of the memory cell selection MISFETQ is connected to the data line 12 with an intermediate conductive film 8 interposed therebetween. The intermediate conductive film 8 is formed of a polycrystalline silicon film deposited by CVD, and is doped with an n-type impurity to reduce the resistance value. The intermediate conductive film 8 is connected to the other semiconductor region 5 in a self-aligned manner with respect to the gate electrode 3 through a connection hole 7 defined in a sidewall spacer 6 formed on the side wall of the gate electrode 3 . MISFETQ for memory cell selection
The n-type impurity introduced into the intermediate conductive film 8 is diffused into the connection portion between the other semiconductor region 5 and the intermediate conductive film 8.
An n-type semiconductor region 9 is configured. Gate electrode 3 and intermediate conductive film 8 are electrically separated by interlayer insulating film 4 .

The data line 12 is connected to a connection hole 1 formed in the interlayer insulating film 10.
1 to the intermediate conductive film 8. data line 1
An interlayer insulating film 13 is provided above 2.

A DRAM configured in this way has M for memory cell selection.
Mask misalignment in the manufacturing process between the semiconductor region 5 (actually 9) of ISFETQ and the data line 12 can be alleviated by the intermediate conductor [8].

In other words, the intermediate conductive film 8 is the MISFE for memory cell selection.
Since the area of the other semiconductor region 5 of T can be reduced by an amount corresponding to the amount of mask misalignment, there is a feature that the degree of integration of the DRAM can be improved.

The technology for connecting the polycrystalline silicon film to the semiconductor region in a self-aligned manner is described in Japan Journal.
l of Applied Physics, Vo18
．． It is described on pages 35 to 42.

[Problem that the invention seeks to solve]

Prior to the development of the above-mentioned DRAM, the present inventor discovered that the following problem occurred.

The intermediate conductive film 8 shown in FIG. 7 has solid phase diffusion of Il type impurities of 10" [atoms/millimeter] so that the pn junction depth of the semiconductor region 9 becomes deep and the short channel effect of the memory cell selection MISFET Qs does not occur. In the case of ion implantation, the introduction of n-type impurities was set to less than an'1.
Although the concentration was as high as 0'' [atoa+s/an2], it was introduced only into the surface layer of the intermediate conductive film 8.The intermediate conductive film 8 configured in this manner has the following results:
In particular, it was confirmed that an inflection point 14 where the orientation of the grain boundary changes was formed in the stepped portion. This inflection point 14 becomes an entrance/exit for replacing the silicon atoms of the intermediate conductive film 8 with the aluminum atoms of the data line 12, and in the vicinity of the contact portion between the intermediate conductive film 8 and the data line 12, silicon atoms are formed inside the data l1i112. Precipitate 15 was generated. Therefore, data line 1
A problem occurred in that not only the resistance value of the data line 12 increased, but also the data line 12 was disconnected due to the heat generated by the increased resistance value. Disconnection of the data line 12 reduces the electrical reliability of the DRAM.

An object of the present invention is to provide a technique that can prevent silicon precipitates from forming inside the wiring in a semiconductor integrated circuit device in which wiring is connected to a semiconductor region with a silicon film interposed therebetween. be.

Another object of the present invention is to provide a manufacturing method for achieving the above object.

Another object of the present invention is to provide a technique capable of achieving the above object and improving the electrical reliability of a semiconductor integrated circuit device.

The above and other objects and novel features of the present invention will become apparent from the description of this specification and the accompanying drawings.

[Means for solving problems]

A brief overview of typical inventions disclosed in this application is as follows.

A semiconductor integrated circuit device in which interconnections are connected to a semiconductor region with a silicon film interposed therebetween, in which an inflection point where the orientation of crystal grain boundaries of the silicon film changes is eliminated.

In addition, a polycrystalline silicon film is formed, a high concentration of impurity is introduced into this polycrystalline silicon film, the polycrystallinity is destroyed, an amorphous silicon film is formed, and this amorphous silicon film is heat-treated. The silicon film is formed by forming an amorphous silicon film on a single crystal silicon film.

[For production]

According to the above-mentioned means, since the substitution reaction caused by the inflection point can be eliminated, the formation of silicon precipitates inside the wiring can be prevented, and the resistance value of the wiring can be reduced or the disconnection of the wiring can be prevented. This can be prevented. As a result, the electrical reliability of the semiconductor integrated circuit device can be improved.

Further, by forming the polycrystalline silicon film as a Ql crystalline silicon film, a silicon film without an inflection point can be formed.

Hereinafter, a configuration of the present invention will be described together with an embodiment in which the present invention is applied to a DRAM in which a memory cell is formed of a planar structure information storage capacitor element.

In addition, in all the times for explaining the example.

Components having the same function are given the same reference numerals, and repeated explanations thereof will be omitted.

[Embodiments of the invention]

The structure of a DRAM which is an embodiment of the present invention is shown in FIG. 1 (a sectional view of the main part).

In a memory cell array (memory cell mat) of a DRAM employing a folded pit line method (folded bit line method), a plurality of memory cells M shown in FIG. 1 are arranged in a matrix. The DRAM is composed of an n-type semiconductor substrate 20 made of single crystal silicon. The memory cell M is provided on the main surface of a p° type well region 21 formed on the main surface of the semiconductor substrate 20. Although not shown, the P channel of CMO8
An n-type well region is provided on the main surface of the half-forming plate 20 in the formation region.

The memory cell M is formed on the main surface of the well region 21 within a region defined (surrounded) by the field insulating film 22 and the p-type channel 1-flange region 23A.

The field insulating film 22 is formed of a silicon oxide film having a thickness of one size, in which the main surface of the well region 21 is selectively oxidized. The channel stopper region 23A is formed on the main surface of the well region 21 of the field insulating film 22F in the memory cell array formation region.

Field insulating film 22 and channel stopper region 23A
is configured to electrically isolate the memory cells M from each other.

A p-type potential barrier layer 23B is formed on the main surface of the well region 21 below the memory cell M. The potential barrier layer 23B is provided under the entire surface of the memory cell M, that is, over the entire surface of the memory cell array. Note that, basically, the potential barrier layer 23B only needs to be provided at least under the information storage capacitive element C of the memory cell M. The potential barrier layer 23B mainly forms a potential barrier against minority carriers generated by the incidence of α rays inside the semiconductor substrate 20 and the well region 21, respectively. In other words, potential barrier layer 2
3B is configured to prevent minority carriers from entering the information storage capacitive element C and reduce the incidence of soft errors in the memory cell mode. Further, the potential barrier layer 23B is configured to increase the amount of charge stored in the information storage capacitive element C.

This potential barrier layer 23B is formed in the same manufacturing process as the channel stopper region 23A.

A p-type channel stopper region defining a region of a MISFET constituting a peripheral circuit, for example, a decoder circuit, is formed in substantially the same manufacturing process as the field insulating film 22, and is formed in a separate manufacturing process from the channel stopper region 23A. 6. In other words, the potential barrier layer 23B and the channel stopper region 23A are formed by introducing p-type impurities by ion implantation and stretching and diffusing the p-type impurities before or after forming the field insulating film 22. Can be done.

The memory cell M is a memory cell selection MIS1”ET.
Q, and an information storage capacitive element C in series.

The information storage capacitive element C has an n-type semiconductor region 24. which is one electrode (lower electrode). dielectric film 25, the other fttt
It is constructed by sequentially stacking plate electrodes 26, which are 4 (upper electrodes).

A power supply voltage 1/2vce is applied to the plate electrode 26. The power supply voltage 1/2 cc is the power supply voltage VeC
(for example, circuit operating potential 5 [V]) and reference voltage VSS (
The intermediate potential (approximately 2.5 [V]) between the circuit ground potential (0 [V])
V]), the power supply voltage 1/2 cc is the semiconductor region 2
Since the electric field strength between the electrodes 4 and the plate electrode 26 can be reduced, the dielectric film 24 can be made thinner and the amount of charge stored in the information storage capacitive element C can be increased. The plate electrode 26 is, for example, an n
It is composed of a polycrystalline silicon film into which a type impurity (As or P) is introduced.

The semiconductor region 24 is a MISFE T for memory cell selection.
It is configured such that a potential (Vgs Vth or Vcc Vth) serving as information from the data line (DL) is applied through Q m . The semiconductor region 24 has a plate electrode 26 connected to a power supply voltage of 1/2V. The structure is such that even when a voltage is applied to the current, electric charges serving as information can be reliably accumulated. The semiconductor region 24 is l x 10''~I
It is constructed by introducing AS (or P) with an impurity concentration of approximately X 10'' [atoms/an2] by ion implantation.

The dielectric film 25 is composed of a silicon oxide film formed by oxidizing the surface of the semiconductor region 24. Further, the dielectric film 25 may be composed of a composite film in which a silicon oxide film and a silicon nitride film are stacked.

The information storage capacitive element C is basically composed of the semiconductor region 24, the dielectric film 25, and the plate electrode 26 as described above, but the pn junction capacitance between the semiconductor region 24 and the potential barrier layer 2313 is This contributes to an increase in the amount accumulated.

An interlayer insulating film 27 is provided on the surface of the plate electrode 26 of the information storage capacitive element C to electrically isolate it from the upper conductive film.

The memory cell selection MISFET Q3 of the memory cell M is
Well region 21 (actually potential barrier layer 23B
). MIS for memory cell selection
FETQ is configured within a region defined by field insulating film 22 and channel stopper region 23A.

The memory cell selection MISFETQ mainly includes a well region 21, a gate insulating film 28. It is composed of a gate electrode 29 and a pair of n-type semiconductor regions 31 which are a source region and a drain region.

The tube area 21 is a MISFETQ for memory cell selection.
It is used as a channel forming region for S.

The gate insulating film 28 is composed of a silicon oxide film formed by oxidizing the main surface of the well region 21.

The gate electrode 29 is provided on a predetermined upper part of the gate insulating film 28 and is composed of a composite film in which a high melting point metal film or a high melting point metal silicide film is superimposed on a polycrystalline silicon film into which impurities are introduced to reduce the resistance value. has been done. The interlayer insulating film 2
A word line (WL, ) 29 formed in the same manufacturing process as the gate electrode 29 is configured to extend above the information storage capacitive element C with 7 interposed therebetween or above the field insulating film 22. There is. Further, the gate electrode 29 and the word line 29 may be formed of a single layer polycrystalline silicon film, a high melting point metal film, or a high melting point metal silicide film.

Of the pair of semiconductor regions 31, one semiconductor region 31 connected (integrated) with the semiconductor region 24, which is the lower electrode of the information storage capacitor C, is formed by ion implantation with a low impurity concentration. . That is, one semiconductor region 3
1 is 1×10” to 1×10” [atoms/■2
] is formed by ion implantation with a low impurity concentration. This one semiconductor region 31 is.

Although it has a resistance value of 1 to 2 [KΩ], since the ON resistance of the memory cell selection MISFETQ is about several [KΩ], there is no problem in information writing and reading operations.

Of the pair of semiconductor regions 31, the other semiconductor region 31 (the side connected to the data line 38) is basically implanted with low impurity concentration ions in the same manner as the one semiconductor region 31 (in the same manufacturing process). It is formed. Other semiconductor region 3
1 is an n-type semiconductor region 35 in which at least the portion connected to the data line (actually, the intermediate conductive layer 34) has a high impurity concentration, as shown in FIGS. 1 and 2 (enlarged sectional views of main parts).
It consists of The semiconductor region 35 is formed by introducing an n-type impurity by thermal diffusion from the intermediate conductive film 34 connected thereto in a self-aligned manner. For example, the semiconductor region 34 has a surface concentration of 10"-10" [atom
It is formed with a high impurity concentration of about s/cn31 or more.

The intermediate conductive film 34 is connected to the semiconductor region 35 through a connection hole 33 defined by a sidewall spacer 32 formed on the sidewall of the gate electrode 29 . Intermediate conductive film 3
4 is a highly concentrated n-type impurity P(
The single crystal silicon film is formed from a polycrystalline silicon film into which A s ) is introduced. The intermediate conductive film 34 has a region indicated by the symbol 34A in FIG. 2 and surrounded by a dotted line, that is,
In particular, there is no inflection point where the orientation of grain boundaries changes in the stepped portion. Intermediate conductive film 34 and gate electrode 29 are electrically isolated by interlayer insulating film 30.

A data line (DL) 38 is connected to the intermediate conductive film 34 through a connection hole 37 formed in an interlayer insulating film 36 . Although the data line 38 is misaligned with the semiconductor region 35 during the manufacturing process, since the central portion of the intermediate conductive film 34 is connected to the semiconductor region 35 in a self-aligned manner, the intermediate conductive film 34 is interposed. This substantially connects the data line 38 and the semiconductor region 35 to the gate i'
Connection can be made in a self-aligned manner in a narrow region between the l poles 29. The data line 38 is made of aluminum, for example.
Aluminum alloy film 311 added with Si or Cu
It is composed mainly of 1B. In this embodiment, the data line 38 is composed of a composite film in which an aluminum alloy film 38B is laminated on a high melting point metal silicide film 38A. The high melting point metal silicide film 38A is, for example, MoSi,
is formed. The high melting point metal silicide film 38A is configured to prevent the ohmic characteristics from deteriorating due to the epitaxial layer being stacked on the connection portion between silicon (for example, the source region and drain region of MISFET in the peripheral circuit) and the aluminum alloy film 38B. has been done. The high melting point metal silicide film 38A has a film thickness of about 150 [people], for example.
o5it, and the aluminum alloy film 38B is made of AI-〇, 5% Cu-1,
It is made of 5% Si.

A shunt word line (W L ) 40 is provided above the data line 38 with an interlayer insulating film 39 interposed therebetween. Although not shown, a shunt word line 40 is provided.

It is connected to the word line 29 in a predetermined region and is configured to reduce its resistance value. The shunt word line 40 is mainly composed of an aluminum film or an aluminum alloy film, for example, like the data line 38.

Next, a method for manufacturing the intermediate conductive film 34 will be briefly described using FIGS. 3 to 6 (cross-sectional views of main parts for each manufacturing process).

First, a memory cell selection MISFETQ is formed on the main surface of the well region 21 (actually, the potential barrier layer 23B). After this, MISFETQs for memory cell selection
A contact hole 33 defined by a sidewall spacer 32 is formed on the other semiconductor region 31 .

Next, as shown in FIG. 3, a polycrystalline silicon film 34B is formed over the entire surface of the substrate including the upper part of the interlayer insulating film 30 so as to contact (connect) the other semiconductor region 31 through the connection hole 33. The polycrystalline silicon film 34B has a thickness of 630 to 650 ['C
] Deposited by CVD at a low temperature of about 2,000 yen
It will be formed by about 3,000 [people]. Polycrystalline silicon film 34B
The above-mentioned intermediate conductive film 34 is formed.

Next, as shown in FIG. 4, a high concentration of n-type impurity is introduced into the polycrystalline silicon film 34B. For example, the n-type impurity is 10
" P (or As) with a high concentration of [atoms/cya21 or more] is used and introduced by ion implantation with an energy of about 70 to 90 [KeV]. The introduction of this n-type impurity can reduce the resistance value. Furthermore, the n-type impurity is
Since it can diffuse into the crystal grain boundaries of the polycrystalline silicon film 34B and cause strain between crystals, the crystals of the polycrystalline silicon film 34B can be destroyed.

This crystal destruction is performed entirely in the thickness direction of the polycrystalline silicon film 34B. When the crystal is destroyed by introducing a high concentration of n-type impurity in this way, the polycrystalline silicon film 34B becomes amorphous. A silicon film (so-called amorphous silicon film) 34C is formed.

The amorphous silicon film 34C need only be formed at least at the connection portion between the other semiconductor region 31 of the memory cell selection MISFETQ and the polycrystalline silicon film 34B.

Further, the amorphous silicon film 34C may be formed by introducing n-type impurities by solid phase diffusion. When introducing n-type impurities by in-phase diffusion, heat treatment is performed at 850 to 900 ['C] and at a high concentration of 102' [atoms/an 3] or more.

Next, the amorphous silicon film 34G is patterned into a predetermined shape (the shape of the intermediate conductive film 34). This patterning is performed by anisotropic etching such as RIE.

Next, as shown in FIG. 5, the amorphous silicon film 34C is subjected to heat treatment. The heat treatment is performed at a high temperature of about 900 to 1000 [°C]. Through this heat treatment, the memory cell selection MISFETQ, which is made of single crystal silicon, is formed.

Grains are formed in the amorphous silicon film 34C from the part that contacts the other semiconductor region 31, and the grains grow and increase in size, and the intermediate conductive film 3 is made into a single crystal.
4 can be formed. The polycrystalline silicon film 34B formed by the low-temperature CVD has a small grain size and easily forms an inflection point where the orientation of crystal grain boundaries changes, but the single-crystal intermediate conductive film 34 does not have such an inflection point.

As a result of the heat treatment process for forming the intermediate conductive film 34, as shown in FIG. Thermal diffusion is performed to form a highly concentrated n-type semiconductor region 35.

Next, an interlayer insulating film 36 is formed, a connection hole 37 is formed,
As shown in FIG. 6, a data line 38 (see FIG. 2 for detailed structure) is formed.

Next, as shown in FIGS. 1 and 2, an interlayer insulating film 39 and a shunt word line 40 are sequentially formed to complete the DRAM of this embodiment.

In this way, a polycrystalline silicon film 34B is formed, and a high concentration of n-type impurity is introduced into this polycrystalline silicon film 34B to destroy its polycrystallinity to form an amorphous silicon film 34G. By performing heat treatment on the crystalline silicon film 34C and forming the amorphous silicon film 34C into a single crystal silicon film (34) to form the intermediate conductive film 34, an inflection point where the orientation of crystal grain boundaries changes. It is possible to form an intermediate conductive IPJ 34 without any.

That is, in a DRAM in which a data line (wiring) 38 is connected to a semiconductor region 31 (actually a semiconductor region 35) with an intermediate conductive film 34 interposed therebetween, an inflection point where the orientation of the crystal grain boundaries of the intermediate conductive film 34 changes. Due to the inflection point. Since the substitution reaction between the silicon atoms of the intermediate conductive film 34 and the aluminum atoms of the data line 38 can be eliminated, the formation of silicon precipitates inside the data line 38 is prevented, and the resistance value of the data line 38 is reduced. Or data line 38
It is possible to prevent wire breakage. This effect is similar not only in the memory cell array but also in peripheral circuits in which wiring is connected to the semiconductor region with an intermediate conductive film interposed therebetween.

As a result, the electrical reliability of the DRAM can be improved.

Although the invention made by the present inventor has been explained in detail based on the above embodiments, the present invention is not limited to the above embodiments, and can be modified in various ways without departing from the gist thereof. Of course.

For example, the present invention is not limited to DRAMs, but can be applied to a MoS integrated circuit device in which wiring is connected to each of the source region and train region of a MISFET with an intermediate conductive film interposed therebetween.

Further, the present invention can be applied to a bipolar transistor integrated circuit device in which an aluminum wiring is connected with a silicon film interposed in an emitter region or the like.

〔Effect of the invention〕

Among the inventions disclosed in this application, the effects obtained by typical inventions will be briefly explained.

It is as follows.

In a semiconductor integrated circuit device, the existence of an inflection point in a silicon film interposed between a semiconductor region and a wiring can be eliminated.

Furthermore, the electrical reliability of the semiconductor integrated circuit device can be improved.

[Brief explanation of the drawing]

FIG. 1 is a sectional view of a main part showing the structure of a DRAM which is an embodiment of the present invention, and FIG. 2 is an enlarged sectional view of a main part of the DRAM. 3 to 6 are enlarged cross-sectional views of the main parts of each manufacturing process for explaining the method of manufacturing the main parts of the DRAM. FIG. 7 is a sectional view of a main part of a DRAM memory cell, which is the background of the present invention.

Claims (1)

[Scope of Claims] 1. A semiconductor integrated circuit device in which a wiring mainly made of an aluminum film or an alloy film thereof is connected to a semiconductor region formed on the main surface of a single-crystal silicon substrate with a silicon film interposed therebetween, A semiconductor integrated circuit device characterized in that an inflection point at which the orientation of crystal grain boundaries of the silicon film changes is eliminated. 2. The semiconductor integrated circuit device according to claim 1, wherein at least a portion of the silicon film in contact with the wiring is made of a single crystal silicon film. 3. The silicon film is connected to the semiconductor region, which is the source region or drain region of the MISFET, in a self-aligned manner with respect to the gate electrode of the MISFET and defined by a sidewall spacer formed on a sidewall of the gate electrode. A semiconductor integrated circuit device according to claim 1 or 2, characterized in that: 4. A method for manufacturing a semiconductor integrated circuit device, in which a wiring mainly made of an aluminum film or an alloy film thereof is connected to a semiconductor region formed on the main surface of a single-crystal silicon substrate, with a silicon film interposed therebetween. a step of forming a polycrystalline silicon film in contact with the polycrystalline silicon film; a step of introducing high concentration impurities into the polycrystalline silicon film to destroy its polycrystallinity to form an amorphous silicon film; 1. A method of manufacturing a semiconductor integrated circuit device, comprising the step of subjecting the film to heat treatment to form an amorphous silicon film into a single crystal silicon film from a portion that contacts the semiconductor region. 5. The method of manufacturing a semiconductor integrated circuit device according to claim 4, wherein the polycrystalline silicon film is formed by low-temperature CVD. 6. The impurity is 10^1^6 [atoms/cm^
2] or higher concentration of ion implantation or 10^1^9[a
5. The method for manufacturing a semiconductor integrated circuit device according to claim 4 or 5, wherein the semiconductor integrated circuit device is introduced by solid-phase diffusion at a high concentration of at least 13cm^3]. 7. The method of manufacturing a semiconductor integrated circuit device according to each of claims 4 to 6, wherein the heat treatment is performed at a temperature of about 900 to 1000 [°C].