JPS52149988A - Semiconductor device - Google Patents

Semiconductor device

Info

Publication number
JPS52149988A
JPS52149988A JP6653176A JP6653176A JPS52149988A JP S52149988 A JPS52149988 A JP S52149988A JP 6653176 A JP6653176 A JP 6653176A JP 6653176 A JP6653176 A JP 6653176A JP S52149988 A JPS52149988 A JP S52149988A
Authority
JP
Japan
Prior art keywords
impurity layer
conductivity type
gate
semiconductor device
under
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP6653176A
Other languages
Japanese (ja)
Other versions
JPS6053470B2 (en
Inventor
Masaaki Nakai
Seiji Kubo
Ryoichi Hori
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Original Assignee
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd filed Critical Hitachi Ltd
Priority to JP51066531A priority Critical patent/JPS6053470B2/en
Publication of JPS52149988A publication Critical patent/JPS52149988A/en
Publication of JPS6053470B2 publication Critical patent/JPS6053470B2/en
Expired legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/30—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells

Abstract

PURPOSE:To improve memory information storage time of a MOS type memory cell by 1 to 2 digits by forming an impurity layer of a conductivity type differing from that of a substrate near the semiconductor substrate surface under a first gate and an impurity layer of the same conductivity type under a second gate respectively by a self-aligning method.
JP51066531A 1976-06-09 1976-06-09 Manufacturing method of semiconductor memory Expired JPS6053470B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP51066531A JPS6053470B2 (en) 1976-06-09 1976-06-09 Manufacturing method of semiconductor memory

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP51066531A JPS6053470B2 (en) 1976-06-09 1976-06-09 Manufacturing method of semiconductor memory

Related Child Applications (1)

Application Number Title Priority Date Filing Date
JP60070903A Division JPS611047A (en) 1985-04-05 1985-04-05 Semiconductor memory

Publications (2)

Publication Number Publication Date
JPS52149988A true JPS52149988A (en) 1977-12-13
JPS6053470B2 JPS6053470B2 (en) 1985-11-26

Family

ID=13318550

Family Applications (1)

Application Number Title Priority Date Filing Date
JP51066531A Expired JPS6053470B2 (en) 1976-06-09 1976-06-09 Manufacturing method of semiconductor memory

Country Status (1)

Country Link
JP (1) JPS6053470B2 (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0046886A2 (en) * 1980-08-29 1982-03-10 Siemens Aktiengesellschaft Method of making dynamic integrated RAM one-transistor memory cells
EP0053672A2 (en) * 1980-12-08 1982-06-16 Siemens Aktiengesellschaft Method of producing a one-transistor memory cell employing the double silicon layer technique
JPS6150361A (en) * 1976-09-13 1986-03-12 テキサス　インスツルメンツ　インコ−ポレイテツド Memory cell

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6150361A (en) * 1976-09-13 1986-03-12 テキサス　インスツルメンツ　インコ−ポレイテツド Memory cell
EP0046886A2 (en) * 1980-08-29 1982-03-10 Siemens Aktiengesellschaft Method of making dynamic integrated RAM one-transistor memory cells
EP0046886A3 (en) * 1980-08-29 1982-06-09 Siemens Aktiengesellschaft Method of making dynamic integrated ram one-transistor memory cells
EP0053672A2 (en) * 1980-12-08 1982-06-16 Siemens Aktiengesellschaft Method of producing a one-transistor memory cell employing the double silicon layer technique
EP0053672A3 (en) * 1980-12-08 1983-10-05 Siemens Aktiengesellschaft Method of producing a one-transistor memory cell employing the double silicon layer technique

Also Published As

Publication number Publication date
JPS6053470B2 (en) 1985-11-26

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