JPH04145660A - Semiconductor memory - Google Patents

Abstract

PURPOSE:To facilitate connections between metal interconnection and lower layer interconnection, a diffused layer, etc., and to improve workability by superposing adjacent capacity storage electrodes of a stacked memory cell to increase the flat area of the capacity. CONSTITUTION:A first capacity storage electrode 107 provided on a P-type silicon substrate 101 having a field oxide film 102 is so provided as to be disposed on word lines 105a, 105b, 105c through silicon oxide films 106a, 106b, 106c. For example, they are formed of polycrystalline silicon. A plate electrode 109 is provided on the electrode 107 through a first capacity insulating film 108. A second capacity storage electrode 117 is provided on an electrode 109 through a second capacity insulating film 118. Thus, the electrodes 107, 117 are superposed to increase the flat area of the capacity to facilitate connections between metal interconnection provided on a cell array and a lower layer interconnection, a diffused layer, etc., and to reduce the height of the electrode, and hence workability can be easily improved.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a semiconductor memory, and particularly to a DRAM comprising stacked memory cells.

[Conventional technology]

As the cell size of DRAM memory cells decreases,
It has progressed from the planar type to the trench type and then to the stacked type. It is difficult to reduce the storage capacitance value due to soft errors, for example, and therefore, in order to secure the storage capacitance in the stacked type, a method is used to extend the storage capacitance in the vertical direction.

The cell structure of a DRAM composed of conventional stacked memory cells can be roughly divided into the following two types of structures.

FIG. 3 is a longitudinal sectional view of a first conventional memory cell.

The structure of the first conventional example is a structure in which the capacitance storage electrode is formed below the bit line.

Field oxide film 30 provided on the surface by selective oxidation
Gate oxide films 304a, 304b or field oxide films 302 are formed on a P-type silicon substrate 301 having
via word lines 305a, 305b, 305
c, 305d are formed, word lines 305a,
305b, 305c, 305d are silicon oxide films 306a, 306b, 306c, 306
covered by d. A capacitor storage electrode 327 made of, for example, polycrystalline silicon is connected to the N-type diffusion layer 303b formed on the surface of the substrate 301 between the word line 305b and the field oxide film 302, and a capacitor insulating film is formed on the capacitor storage electrode 327. A plate electrode 309 is formed via 328. The bit line 311 passes over the plate electrode 309 via the interlayer insulating film 310, and the N-type diffusion layer 303a formed between the word line 305a and the word line 305b.
It is connected to the.

FIG. 4 is a cross-sectional view of a second conventional memory cell.

The structure of the second conventional example is such that the capacitance storage electrode is formed in a layer above the bit line.

Field oxide film 40 provided on the surface by selective oxidation
2, word lines 405a, 405b, 405c are formed on a P-type silicon substrate 401 with gate oxide films 404a, 404b or field oxide films 402.
, 405d are formed, word lines 405a, 405
b, 405c, 405d are silicon oxide films 406a, 4
06b, 406c, and 406d. The bit line 411 is connected to the interlayer insulating film 410 and the silicon oxide film 4.
Word lines 405a, 405b, 405c via 06a, 406b, 406c, 406d
, 405d (in FIG. 4, part of the word lines 405a, 405b and the word line 405c,
Although the bit line 411 is not shown on 405d, it passes over it in an unillustrated portion. ) is connected to an N-type diffusion layer 403a formed on the surface of the P-type silicon substrate 401 between the word line 405a and the word line 405b. Capacitance storage electrodes 427a, 427b, and 427c are formed on the bit line 411 via a glabella insulating film 420, and the capacitance storage electrode 427b is an N-type diffusion layer 403b formed between the word line 405b and the word line 405C. connected to 0.

[Problem to be solved by the invention]

In the conventional semiconductor memory mentioned above, as integration progresses, for example, in the case of a 16 Mbit DRAM, the cell size is 4 μm2.
It is necessary to do the following. At this time, the above-mentioned 1. When a storage capacitor is provided for each individual memory cell as in the second conventional example, even if it is designed using the 0.5 μm rule, the planar area of the storage capacitor must be approximately 1.5 μm2 or less, approximately 2 μm2 or less. be. Therefore, the height of the storage capacitor is increased to ensure the opposing area between the capacitor storage electrode and the plate electrode.

In such a case, first of all, it is not easy to connect the metal wiring provided above the cell array and the lower layer wiring, diffusion layer, etc. This is because it becomes difficult to process the opening due to steps, unevenness, etc. caused by a tall storage capacitor, and it also becomes difficult to embed a conductor in the opening.

Secondly, increasing the height of the storage capacitor also increases the length of the capacitor storage electrode, making it difficult to process it.

[Means to solve the problem]

A semiconductor memory of the present invention has a stacked memory cell including one transistor and one stacked storage capacitor, and includes at least one conductive film layer;
and a portion of the capacitance storage electrode of the first stacked memory cell and a portion of the capacitance storage electrode of the stacked memory cell adjacent to the first stacked memory cell with at least two layers of insulating films in between. , have an overlapping structure.

〔Example〕

Next, the present invention will be explained with reference to the drawings.

FIG. 1 is a longitudinal sectional view for explaining a first embodiment of the present invention. In this example, the first
The storage capacitance of the stacked memory cell and the storage capacitance of the second stacked memory cell adjacent to the first stacked memory cell are stacked back to back.

Field oxidation M10 provided on the surface by selective oxidation
2, word lines 105a, 105d, 105b are formed on a P-type silicon substrate 101 with gate oxide films 104a, 104b or field oxide films 102
, 105c are formed, and word lines 105a, 1
05b, 105c, 105d are silicon oxide 1
1! Covered by 106a, 106b, 106c, and 106d. The N-type diffusion layers 103b and 103c serve as connection terminals for the first and second capacitance storage electrodes 107 and 117, respectively.

The first capacitance storage electrode 107 includes a silicon oxide film 106a,
Words via 106b, 106c! 105a, 105
b, 105c, and is formed of polycrystalline silicon, for example. First capacitive storage M electrode 107
A plate electrode [
1109 is provided. On the plate electrode 109, a second capacitive storage electrode [11
7 is provided. N-type diffusion layers 103a and 103d, which serve as connection terminals for the capacitance storage electrodes, are both connected to the bit line 111. Further, the bit line 111 is connected to the interlayer insulating film 11
0 on the storage capacitor.

In this embodiment, by overlapping the storage capacitances of two memory cells, the planar area of these storage capacitances is 1.7 mm compared to the conventional one.
Can be expanded to about twice the size. 'FIG. 2 is a longitudinal sectional view for explaining a second embodiment of the present invention. In this embodiment, half of the second stacked memory cell adjacent to the first stacked memory cell and the first stacked memory cell are placed on the storage capacitor of the first stacked memory cell with the plate electrode in between. A third stacked memory cell half adjacent to the memory cell is formed.

Field oxidation M2O provided on the surface by selective oxidation
Gate oxide films 204a, 204b, 204c, 204d are formed on a P-type silicon substrate 201 having
Alternatively, the word line 20 can be connected via the field oxide film 202.
5a, 205b, 205e, 205f, or 205c, 205d are formed, and the word line 205
a, 205b, 205c, 205d,
205e and 205f are silicon oxide films 206a,
206b, 206c, 206d, 206
e, covered by 206f.

The N-type diffusion layers 203b and 203e serve as connection terminals for the bit line 211, and the field oxide films 202. Silicon oxide films 206a, 206b, 206c, 20
Glabellar insulating film 21 on 6d, 206e, 206f
A bit line 211 is also provided via the bit line 0.

N-type diffusion layers 203c, 203f, and 203a,
203d are first capacitance storage electrodes 207a and 207b
, and the connection terminals of the second capacitance storage electrodes 217a and 217b. On the first capacitor electrode 207a, a first capacitor insulating film 208a, a plate electrode 209. Each half of the second capacitive storage electrode 217a and the second capacitive storage electrode 217b are formed via the second capacitive insulating film 218a, and the first capacitive insulating film 208b is formed on the first capacitive electrode 1207b.
, plate electrode 209. A half of the second capacitor storage electrode 217b and the like are formed through the second capacitor insulating film 218b, thereby forming a storage capacitor. Further, these storage capacitors are connected to the bit line 211 via the interlayer insulating film 220.
formed on top.

In this example, one capacitance storage electrode stores two adjacent capacitances! Since it overlaps with the pole, the planar area of the storage capacity can be expanded to about twice that of the conventional one.

〔Effect of the invention〕

As described above, in the present invention, the height of the capacitor storage electrode can be reduced by overlapping adjacent capacitor storage electrodes of a stacked memory cell to increase the planar area of the storage capacitor.

As a result, first of all, connections between the metal wiring provided on the upper part of the cell array and the lower layer wiring, diffusion layer, etc. are facilitated. This is because the height of the storage capacitor is shorter than that of conventional semiconductor memory, which reduces the steps and unevenness that occur, making it easier to process the opening, and to embed conductive material in the opening. This is because. Second, since the height of the capacitance storage electrode is reduced, its workability becomes easier.

[Brief explanation of the drawing]

FIG. 1 is a longitudinal cross-sectional view for explaining the first embodiment of the present invention, FIG. 2 is a longitudinal cross-sectional view for explaining the second embodiment of the present invention, and FIGS. 3 and 4 are FIG. 2 is a vertical cross-sectional view of a conventional semiconductor memory. 101.201.301.401...P-type silicon substrate, 102.202,302,402...Field oxide film, 103a, 103b, 103c, 103d, 2
03a, 203b, 203c, 203d. 203e, 203f, 303a, 303b, 403a,
403b---N type diffusion layer, 104a, 104b, 2
04a, 204b, 204c, 204d, 304a, 3
04b. 404a, 404b---gate oxide film, 105a,
105b, 105c, 105d, 205a, 205b,
205c, 205d. 205e, 205f, 305a, 305b, 305c,
305d, 405a, 405b. 405c, 405d... word line, 106a, 106b, 106c, 106d, 206a,
206b, 206c, 206d206e, 206f, 3
06a, 306b, 306c, 306d, 406a, 4
06b. 406c, 406d...Silicon oxide film, 107.2
07a, 207b ---first capacitance storage electrode, 108
．． 208a, 208b - first capacitive insulating film, 109
, 209, 309, 409... plate electrode,
110.210,220,310,410,420...
・Interlayer insulating film, 111.211.311,411...
Bit line, 117.217a, 217b --- Second capacitor storage electrode, 11g, 218a, 218b --- Second capacitor insulating film, 327, 427a, 427b
, 427c -- Capacitance storage electrode, 328.428a,
428b, 428cm--capacitive insulating film.

Claims (1)

[Claims] 1. A semiconductor memory having a stacked memory cell consisting of one transistor and one stacked storage capacitor, with at least one conductive film and at least two insulating films interposed therebetween. , a semiconductor having a structure in which a part of a capacitance storage electrode of a first stacked memory cell and a part of a capacitance storage electrode of a stacked memory cell adjacent to the first stacked memory cell overlap. memory. 2, a capacitive storage electrode of the first stacked memory cell, and a second capacitor storage electrode adjacent to the first stacked memory cell;
2. The semiconductor memory according to claim 1, wherein the capacitance storage electrodes of the stacked memory cells overlap each other. 3. a capacitor storage electrode of the first stacked memory cell, and a second capacitor storage electrode adjacent to the first stacked memory cell;
A part of the capacitance storage electrode of the stacked memory cell and a part of the capacitance storage electrode of the third stacked memory cell adjacent to the first stacked memory cell overlap each other. The semiconductor memory according to item 1.