JPH02116160A - Semiconductor device and manufacture thereof - Google Patents

Abstract

PURPOSE:To make the device of a high density by laminating through an insulating film the lower electrode of a capacitor on an element isolation area and a gate electrode, said lower electrode being connected at the bottom or side surface of a groove formed in an N-type diffusion area of a substrate surrounded by the element isolation area and the gate electrode. CONSTITUTION:A P-well area 15 and an element isolation area 2 are selectively formed on a P type Si substrate 1. Then, an access transistor 10a is formed of a gate insulating film 9, a gate electrode 10, and source and drain diffusion layers 11, 111. After formation of an interlayer insulating film 16, the film 16, the layer 11, and the substrate 1 are etched to form a groove 17. A polycrystalline Si film 19 is formed on the internal wall of the groove 17 into which P is doped, and simultaneously and N type diffusion layer 18 is formed on the surface of the substrate 1 and connected to the layer 111. After a pattern of the polycrystalline Si film is formed on the lower electrode of a MOS capacitor, an insulating film 5 and an N type polycrystalline Si film 20 are deposited to form a cell plate pattern. After an interlayer insulating film 21 is deposited on the cell plate 20, an electrode lead window 13 is formed, and thereafter a bit line 14 is formed to construct a memory cell.

Description

DETAILED DESCRIPTION OF THE INVENTION (Industrial Application Field) The present invention relates to semiconductor devices, such as MOS devices suitable for high density
The present invention relates to the structure of a dynamic RAM (hereinafter referred to as DRAM) and its manufacturing method.

(Prior art) In recent years, the degree of integration of DRAMs has improved, and large capacity devices of 4 Mbits to 16 Mbits have been reported, but in order to put them into practical use, it is necessary to further reduce the chip size by reducing the memory cells. Miniaturization is necessary. For example, the memory cell area per 1 bit is 8 to 8 in a 4 Mbit DRAM.
For a 1 OpH2, 16 Mbit DRAM, it must be less than 2 to 3 μm2. However, considering soft errors and noise margins, it is difficult to reduce the capacitance of the capacitor. In order to keep the memory cell capacity constant while reducing the memory cell area, it is possible to reduce the effective film thickness of insulation III (hereinafter referred to as capacitor insulation film), which is a component of the memory cell capacitor, or to reduce the effective area. For example, in the former method, in a 4M bit DRAM, the capacitor capacity is 4
To achieve 0fF, the capacitor insulating film should be 2.2nm thick.
It is necessary to make it extremely thin. This is difficult to implement due to pinholes in the insulating film and reliability. However, to eliminate these problems, it is possible to dig a trench several microns deep in the semiconductor substrate and form a capacitor on the inner wall of the trench. Alternatively, a manufacturing method is known in which a capacitor is formed between polycrystalline silicon and the effective area of the capacitor is increased by a stacked structure (see, for example, Japanese Patent Laid-Open No. 103372/1983, Semiconductor Memory Device).

Hereinafter, a description will be given with reference to FIG. 3, which shows a cross-sectional view of the structure of a DRAM memory cell manufactured by the former method.

Incidentally, FIG. 3 shows a portion where 2-bit memory cells are placed with the isolation region sandwiched therebetween so that the state of the element isolation region can be easily understood.

First, an element isolation region 2 is formed on a P-type silicon substrate 1 by selective oxidation, and then an anisotropic etching technique such as reactive ion etching is applied to a region of the silicon substrate 1 that is in contact with and sandwiches the element isolation region 2. A trench 3 with a depth of approximately 4 microns is formed by the above method, and an impurity of the electric shock type opposite to that of the substrate 1 is diffused into the side wall of this trench 3 to form an N9 layer 4.Next, a capacitor insulator is formed on the inner wall of this trench 3. A film 5 is provided, and this insulating film 5
After depositing an N-type polycrystalline silicon film 6 thereon, the gap remaining in the trench 3 is filled with an insulator or a second polycrystalline silicon film 7, and the surface of the trench 3 is made flat. The silicon film 6 is selectively removed.

Form a capacitor electrode pattern. Next, after depositing the interlayer insulating film 12, the gate insulating film 9 of the access MOS transistor. Gate electrode 10 made of low resistance metal.
A word line 101 made of a polycrystalline silicon film connected thereto is formed, and an N-type diffusion region 11 which becomes a source/drain region of an access MOS transistor is formed.
and lll are formed. Next, after depositing one interlayer insulating film 12, an N-type diffusion region 11 and an electrode extraction window 13 formed in this diffusion region 11 are provided. A memory cell is formed by forming a bit line 14 made of aluminum wiring. In this manufacturing method, a groove 3 is formed in a silicon substrate 1.
By digging, a MOS capacitor can be formed three-dimensionally, a capacitance of 40 fF can be obtained, and the cell area can be reduced.

(Problems to be Solved by the Invention) In conventional semiconductor manufacturing methods, a hole is dug in a silicon substrate and a capacitor is formed on the inner wall of the hole to reduce the cell area. However, when trench capacitors are formed in contact with both sides of an element isolation region formed by selective oxidation, punch-through occurs between adjacent capacitors, making it difficult to reduce the isolation width. ) Using a P-type silicon substrate with a crystalline surface and a specific resistance of 4Ω·1, two adjacent concave capacitors with a distance between holes of M2.5μ are formed, and the bunch-through voltage is measured at a substrate bias of 13V. Although it is 20V,
When forming a concave capacitor with a distance between holes of 2.0 μm, the punch-through voltage rapidly decreases to about 2V. Although it is possible to improve the bunch-through voltage by increasing the substrate concentration, it cannot be significantly increased due to problems with transistor characteristics of peripheral circuits. In order to increase the bunch-through voltage of the trench capacitor,
There is a method of creating a P-well on a P-type substrate and placing a concave capacitor cell in it (for example, see Nikkei Microdevice May 1987 issue, p. 133).
- Even if the surface concentration of the well is as high as lXl017/-, the depth of the 4μ garden is 5X101s/ci, 5μm.
At a depth of
This is a major challenge in manufacturing large-capacity memory. The trench cell has a problem in that it is difficult to deepen the trench and expand the capacitor area because leakage tends to occur at the bottom of the trench capacitor.

Furthermore, etching deep grooves in the silicon substrate1
As is well known, there are considerable difficulties in processing technology, and there are many problems in putting it to practical use.In particular, as mentioned above, it is extremely difficult to form deep grooves of 4 microns or more.

The present invention is directed to solving one or more of the following problems:
It is an object of the present invention to provide a semiconductor device that is highly integrated by reducing the distance between capacitors and a method for manufacturing the same.

(Means for Solving the Problems) A semiconductor device of the present invention provides at least a portion of the bottom or side surface of a trench formed in an N-type diffusion region of a semiconductor substrate surrounded by an element isolation region and a gate electrode of a MOS transistor. The lower electrode of the MOS capacitor connected to the N-type diffusion region is laminated so as to cover the element isolation region and the gate electrode of the MOS transistor via an interlayer insulating film, and the interlayer insulating film and the upper electrode It is configured to include an MO3 type capacitor having a structure that covers the lower electrode.

(Function) According to the semiconductor device and the manufacturing method thereof of the present invention, punch-through at the bottom of the trench, which is a drawback of trench-type capacitors, can be prevented, and memory cells can be densely packed. Furthermore, compared to conventional stacked capacitors, it is possible to reduce the memory cell area by increasing the effective surface area.

(Example) An example of a DRAM to which the present invention is applied will be described with reference to a partial process flowchart consisting of process cross-sectional views shown in FIGS. 1(a) to 1h). FIG. 2 is a schematic plan view of an embodiment of the DRAM, and FIG. 1 is a diagram showing x-x shown in FIG.
' is a sectional view of '.

First, a P-well region 15 and an element isolation region 2 are selectively formed on the main surface of a P-type silicon substrate 1 (FIG. 1 shows only the memory cell portion, so only the P-well is shown). . The element isolation region 2 is an outer portion surrounded by the region 31 in FIG. 2, and is arranged as shown in FIG. 1(a).

Next, an access transistor loa which becomes a word line (see FIG. 2, 32.32A) is formed. The access transistor 10a has a gate insulating film 9. Gate electrode 10.
Figure 1(b) shows an N-type diffusion region (hereinafter referred to as a source/drain diffusion layer) 11.111 which becomes a source/drain region.
It is configured as shown in . After forming the interlayer insulating film 16 as shown in FIG. 1(Q), the element isolation region 31 (see FIG. 2) is formed.
and access transistors.

An inter-station insulating film 16. is formed by photolithography in the area surrounded by the word line (see FIG. 2A). The source/drain diffusion layer 111 and the silicon substrate 1 are continuously etched to form a trench 17 as shown in FIG. 1(d). As shown in FIG. A film 19 is deposited and phosphorus is diffused into the polycrystalline silicon film 19 to give it conductivity, and at the same time an N-type diffusion layer 18 is formed on the surface of the substrate 1 in the groove 17.

Connected to source/drain diffusion M111. The polycrystalline silicon film 19 is used as the lower electrode of the MOS capacitor (FIG. 2, 34).
After forming a pattern on the capacitor insulating film 5. A second N-type polycrystalline silicon film (cell plate) 20 is deposited, and the cell plate pattern shown in FIG. 2 is formed as shown in FIG. 1(f).

Next, as shown in FIG. 1(g), after depositing a second interlayer insulating film 21 on the cell plate 20, a bit line (second
(see FIG. 36).
After forming as shown in Figure (h), aluminum wiring 14 which is a bit line is formed. A memory cell is formed by connecting a bit line 14 made of aluminum wiring through the electrode extraction window 13.

Note that the protective film is omitted in the figure.

When a part of the MO3 type capacitor is buried in the P-well by the method according to this embodiment, unlike a conventional trench type capacitor cell, not only the inner wall of the trench 17 formed in the silicon substrate 1 but also the gate electrode 10 is buried. °101, element isolation region 2
and the gate electrodes 5, 51 . The upper area of the element isolation region 2 is also utilized, and the diameter of the opening is 1.0 μm and the insulating film is 10 nm thick, as in the conventional trench type capacitor cell.

The depth of the groove is about 1 to 2 μm, and 40 fF can be secured. In the conventional trench capacitor formation method, the surface concentration is 1×101
In the case of 7/ad, it is 5X10"/cd at a depth of 4μ-, and the gap between groove capacitors is 1.4JJIl, the punch-through voltage is about 2μ, and there is a limit in the depth direction of the groove.This book In the method according to the embodiment, the depth is 2μ or less,
In addition, since the N-type polycrystalline silicon film 19 serves as the lower electrode of the MOS capacitor, the punch-through voltage is less affected by the depth of the grooves and the distance between the grooves, and is improved to more than the IOV.

(Effects of the Invention) According to the method of manufacturing a semiconductor device of the present invention, not only the inner wall of the groove formed in the silicon substrate but also the step portion formed by the gate electrode and the element isolation region, and the upper part of the gate electrode and the element isolation region are The area is also utilized, and the diameter of the opening is 1.0 μm and the insulating film is 10 μm, just like the conventional trench type capacitor cell.
Assuming that the groove depth is approximately 1 to 2 μm, 40 fF can be secured. moreover.

Due to the effect of changes in the boron concentration distribution in the depth direction of the groove, the punch-through voltage decreases little, making it possible to reduce the distance between capacitors.

[Brief explanation of the drawing]

1(a) to h) are flowcharts showing partial process cross-sectional views of a DRAM manufacturing method to which the semiconductor device manufacturing method of the present invention is applied, FIG. 2 is a schematic plan view thereof, and FIG. 3 is a conventional A structural cross-sectional view of a DRAM to which the manufacturing method is applied is shown. 5... Capacitor insulating film, 17... Groove, 18
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Claims (2)

[Claims] (1) A MOS capacitor connected to the N-type diffusion region at least part of the bottom or side surface of a trench formed in the N-type diffusion region of the semiconductor substrate surrounded by the element isolation region and the gate electrode of the MOS transistor. A MOS type capacitor having a structure in which a lower electrode is stacked so as to cover the element isolation region and a gate electrode of a MOS transistor via an interlayer insulating film, and the interlayer insulating film and the electrode cover the lower electrode. Semiconductor devices including. (2) An element isolation region and M on the main surface of a semiconductor substrate of one conductivity type.
a step of forming an OS transistor; a step of forming a trench in an N-type diffusion region of a semiconductor substrate surrounded by the gate electrode of the MOS transistor and an element isolation region; N-type polycrystalline silicon is formed so as to cover the gate electrode of the transistor via an interlayer insulating film, and the N-type polycrystalline silicon is connected to the N-type diffusion region at least part of the bottom or side surface of the trench. 1. A method for manufacturing a semiconductor device, comprising: forming a MOS capacitor by depositing and covering the lower electrode made of N-type polycrystalline silicon with a capacitor insulating film and an upper electrode.