JPH02116160A - Semiconductor device and manufacture thereof - Google Patents
Semiconductor device and manufacture thereofInfo
- Publication number
- JPH02116160A JPH02116160A JP63268090A JP26809088A JPH02116160A JP H02116160 A JPH02116160 A JP H02116160A JP 63268090 A JP63268090 A JP 63268090A JP 26809088 A JP26809088 A JP 26809088A JP H02116160 A JPH02116160 A JP H02116160A
- Authority
- JP
- Japan
- Prior art keywords
- insulating film
- capacitor
- type
- element isolation
- film
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims description 16
- 238000004519 manufacturing process Methods 0.000 title claims description 13
- 239000003990 capacitor Substances 0.000 claims abstract description 42
- 239000000758 substrate Substances 0.000 claims abstract description 23
- 238000002955 isolation Methods 0.000 claims abstract description 22
- 238000009792 diffusion process Methods 0.000 claims abstract description 18
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims abstract description 16
- 239000011229 interlayer Substances 0.000 claims abstract description 11
- 238000000034 method Methods 0.000 claims description 13
- 238000000151 deposition Methods 0.000 claims description 5
- 239000010410 layer Substances 0.000 abstract description 10
- 230000015572 biosynthetic process Effects 0.000 abstract description 2
- 238000010030 laminating Methods 0.000 abstract 1
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 11
- 229910052710 silicon Inorganic materials 0.000 description 11
- 239000010703 silicon Substances 0.000 description 11
- 229910052782 aluminium Inorganic materials 0.000 description 3
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 3
- 230000007423 decrease Effects 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 238000005530 etching Methods 0.000 description 2
- 238000000605 extraction Methods 0.000 description 2
- 238000009413 insulation Methods 0.000 description 2
- 239000012212 insulator Substances 0.000 description 2
- 230000003647 oxidation Effects 0.000 description 2
- 238000007254 oxidation reaction Methods 0.000 description 2
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 description 1
- 241000238558 Eucarida Species 0.000 description 1
- 240000008881 Oenanthe javanica Species 0.000 description 1
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 1
- 229910052796 boron Inorganic materials 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 238000009826 distribution Methods 0.000 description 1
- 210000004709 eyebrow Anatomy 0.000 description 1
- 230000006870 function Effects 0.000 description 1
- 210000004209 hair Anatomy 0.000 description 1
- 239000012535 impurity Substances 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 229910052751 metal Inorganic materials 0.000 description 1
- 239000002184 metal Substances 0.000 description 1
- 235000012149 noodles Nutrition 0.000 description 1
- 230000002093 peripheral effect Effects 0.000 description 1
- 229910052698 phosphorus Inorganic materials 0.000 description 1
- 239000011574 phosphorus Substances 0.000 description 1
- 238000000206 photolithography Methods 0.000 description 1
- 238000001020 plasma etching Methods 0.000 description 1
- 230000001681 protective effect Effects 0.000 description 1
- 239000004576 sand Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B12/00—Dynamic random access memory [DRAM] devices
- H10B12/30—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
- H10B12/37—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells the capacitor being at least partially in a trench in the substrate
- H10B12/377—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells the capacitor being at least partially in a trench in the substrate having a storage electrode extension located over the transistor
Landscapes
- Semiconductor Integrated Circuits (AREA)
- Semiconductor Memories (AREA)
Abstract
Description
【発明の詳細な説明】
(産業上の利用分野)
本発明は、半導体装置、例えば高密度化に好適なMOS
ダイナミックRAM(以下、DRAMと記載する)の構
造およびその製造方法に関するものである。DETAILED DESCRIPTION OF THE INVENTION (Industrial Application Field) The present invention relates to semiconductor devices, such as MOS devices suitable for high density
The present invention relates to the structure of a dynamic RAM (hereinafter referred to as DRAM) and its manufacturing method.
(従来の技術)
近年、DRAMの集積度の向上が進み、4Mビットない
し16Mビットの大容量のものが報告されるに至ってい
るが、実用化するには、さらにメモリセルの縮小による
チップサイズの小型化が必要である。例えば、1ビツト
当たりのメモリセル面積は、4MビットDRAMで8〜
1OpH2,16MビットDRAMで2〜3μm2以下
にしなければならない。しかし、ソフトエラーやノイズ
マージンなどを考慮すると、キャパシタ容量を小さくす
ることは困難である。メモリセル面積を小さくしながら
メモリセル容量を一定に保つには、メモリセルキャパシ
タの構成要素である絶縁III(以下、キャパシタ絶縁
膜と記載する)の実効膜厚を薄くする方法、あるいは実
効面積を大きくする方法などがある0例えば、前者の方
法では、4MビットDRAMにおいてキャパシタ容量4
0fFを実現するには、キャパシタ絶縁膜を2.2nm
と極めて薄くする必要がある。これは、絶縁膜のピンホ
ールや信頼性から考えて実現性に乏しい、一方、このよ
うな不都合を除くため、半導体基板に数ミクロンの深さ
の溝を掘り、この内壁にキャパシタを形成すること、あ
るいは多結晶シリコン間でキャパシタを作り、積み上げ
構造によりキャパシタの実効面積を大きくする製造方法
が知られている(例えば、特開昭59−103372号
、半導体記憶装置参照)。(Prior art) In recent years, the degree of integration of DRAMs has improved, and large capacity devices of 4 Mbits to 16 Mbits have been reported, but in order to put them into practical use, it is necessary to further reduce the chip size by reducing the memory cells. Miniaturization is necessary. For example, the memory cell area per 1 bit is 8 to 8 in a 4 Mbit DRAM.
For a 1 OpH2, 16 Mbit DRAM, it must be less than 2 to 3 μm2. However, considering soft errors and noise margins, it is difficult to reduce the capacitance of the capacitor. In order to keep the memory cell capacity constant while reducing the memory cell area, it is possible to reduce the effective film thickness of insulation III (hereinafter referred to as capacitor insulation film), which is a component of the memory cell capacitor, or to reduce the effective area. For example, in the former method, in a 4M bit DRAM, the capacitor capacity is 4
To achieve 0fF, the capacitor insulating film should be 2.2nm thick.
It is necessary to make it extremely thin. This is difficult to implement due to pinholes in the insulating film and reliability. However, to eliminate these problems, it is possible to dig a trench several microns deep in the semiconductor substrate and form a capacitor on the inner wall of the trench. Alternatively, a manufacturing method is known in which a capacitor is formed between polycrystalline silicon and the effective area of the capacitor is increased by a stacked structure (see, for example, Japanese Patent Laid-Open No. 103372/1983, Semiconductor Memory Device).
以下、前者の方法により製作されたDRAMメモリセル
の構造断面図を示した第3図を参照しながら説明する。Hereinafter, a description will be given with reference to FIG. 3, which shows a cross-sectional view of the structure of a DRAM memory cell manufactured by the former method.
なお、第3図は、素子分離領域の様子がわかりやすいよ
うに、分離領域を挟んだ2ビツトのメモリセルが配置さ
れた部分を示している。Incidentally, FIG. 3 shows a portion where 2-bit memory cells are placed with the isolation region sandwiched therebetween so that the state of the element isolation region can be easily understood.
先ず、P型シリコン基板1に選択酸化法により素子分離
領域2を形成した後、素子分離領域2に接し、かつこれ
を挟むシリコン基板1の領域に、反応性イオンエツチン
グなどの異方性エツチング技術により深さ約4ミクロン
の溝3を形成し、この溝3の側壁に基板1と反対の感電
型の不純物を拡散し、N9層4を形成する6次に、この
溝3の内壁にキャパシタ絶縁膜5を設け、この絶縁膜5
上にN型多結晶シリコン膜6を堆積した後、絶縁物また
は第2の多結晶シリコン膜7により溝3に残存する隙間
を埋め、溝3の表面を平坦にした後、前記N型多結晶シ
リコン膜6を選択的に除去し。First, an element isolation region 2 is formed on a P-type silicon substrate 1 by selective oxidation, and then an anisotropic etching technique such as reactive ion etching is applied to a region of the silicon substrate 1 that is in contact with and sandwiches the element isolation region 2. A trench 3 with a depth of approximately 4 microns is formed by the above method, and an impurity of the electric shock type opposite to that of the substrate 1 is diffused into the side wall of this trench 3 to form an N9 layer 4.Next, a capacitor insulator is formed on the inner wall of this trench 3. A film 5 is provided, and this insulating film 5
After depositing an N-type polycrystalline silicon film 6 thereon, the gap remaining in the trench 3 is filled with an insulator or a second polycrystalline silicon film 7, and the surface of the trench 3 is made flat. The silicon film 6 is selectively removed.
キャパシタ電極パターンを形成する。次に、層間絶縁膜
12を堆積した後、アクセス用MOSトランジスタのゲ
ート絶縁膜9.低抵抗の金属からなるゲート電極10.
およびこれにつながる多結晶シリコン膜からなるワード
ライン101を形成し、さらに、アクセス用MOSトラ
ンジスタのソースドレイン領域となるN型拡散領域11
とlllとを形成する。次に1層間絶縁膜12を堆積し
た後、N型拡散領域11とこの拡散領域11に形成され
た電極取り出し窓13とを設ける。アルミ配線からなる
ビットライン14を形成することにより、メモリセルが
形成される。この製造方法では、シリコン基板1に溝3
を掘ることにより、3次元的にMOSキャパシタを形成
し、40fFの容量を得、しかもセル面積の縮小を図る
ことができる。Form a capacitor electrode pattern. Next, after depositing the interlayer insulating film 12, the gate insulating film 9 of the access MOS transistor. Gate electrode 10 made of low resistance metal.
A word line 101 made of a polycrystalline silicon film connected thereto is formed, and an N-type diffusion region 11 which becomes a source/drain region of an access MOS transistor is formed.
and lll are formed. Next, after depositing one interlayer insulating film 12, an N-type diffusion region 11 and an electrode extraction window 13 formed in this diffusion region 11 are provided. A memory cell is formed by forming a bit line 14 made of aluminum wiring. In this manufacturing method, a groove 3 is formed in a silicon substrate 1.
By digging, a MOS capacitor can be formed three-dimensionally, a capacitance of 40 fF can be obtained, and the cell area can be reduced.
(発明が解決しようとする課題)
従来の半導体製造方法では、シリコン基板にホールを掘
り、この内壁にキャパシタを形成することにより、セル
面積の縮小を図っている。しかし、溝型キャパシタを選
択酸化法により形成された素子分離領域の両側に接して
形成した場合、隣接するキャパシタ間でパンチスルーが
起こり、分離幅を小さくすることが困難となる0例えば
、(100)結晶面をもつ比抵抗4Ω・1のP型シリコ
ン基板を用い、ホール間距M2.5μ論の隣り合う二つ
の凹型キャパシタを形成し、基板バイアスが一3vの条
件でバンチスルー電圧を測定すると約20Vであるが、
ホール間距離を2.0μ墓とする凹型キャパシタを形成
した場合には、パンチスルー電圧が約2Vまで急激に低
下する。バンチスルー電圧は、基板濃度を高くすること
により改善するのは可能であるが、周辺回路のトランジ
スタ特性の問題もあり、著しく高くすることはできない
。溝型キャパシタのバンチスルー電圧を高くするため、
P型基板にP−ウェルを造り、この中に凹型キャパシタ
セルを入れる方法がある(例えば、日経マイクロデバイ
ス1987年5月号、P、133参照)、この場合、P
−ウェルの表面濃度をlXl017/−という高濃度に
しても、4μ園の深さでは5X101s/ci、5μm
の深さではlXl0”/csfとなり、P−ウェルの中
に入れるだけでは溝型キャパシタ間のリークを抑えるこ
とはできない。この溝型キャパシタ間の耐圧の向上は、
大容量メモリの製造における大きな課題である。溝型セ
ルは、溝型キャパシタの底部でリークが起こり易いため
、溝を深くし、キャパシタ面積を拡大することは困難で
あるという問題があった。(Problems to be Solved by the Invention) In conventional semiconductor manufacturing methods, a hole is dug in a silicon substrate and a capacitor is formed on the inner wall of the hole to reduce the cell area. However, when trench capacitors are formed in contact with both sides of an element isolation region formed by selective oxidation, punch-through occurs between adjacent capacitors, making it difficult to reduce the isolation width. ) Using a P-type silicon substrate with a crystalline surface and a specific resistance of 4Ω·1, two adjacent concave capacitors with a distance between holes of M2.5μ are formed, and the bunch-through voltage is measured at a substrate bias of 13V. Although it is 20V,
When forming a concave capacitor with a distance between holes of 2.0 μm, the punch-through voltage rapidly decreases to about 2V. Although it is possible to improve the bunch-through voltage by increasing the substrate concentration, it cannot be significantly increased due to problems with transistor characteristics of peripheral circuits. In order to increase the bunch-through voltage of the trench capacitor,
There is a method of creating a P-well on a P-type substrate and placing a concave capacitor cell in it (for example, see Nikkei Microdevice May 1987 issue, p. 133).
- Even if the surface concentration of the well is as high as lXl017/-, the depth of the 4μ garden is 5X101s/ci, 5μm.
At a depth of
This is a major challenge in manufacturing large-capacity memory. The trench cell has a problem in that it is difficult to deepen the trench and expand the capacitor area because leakage tends to occur at the bottom of the trench capacitor.
さらに、シリコン基板に深い溝をエツチングすること1
周知の如く加工技術ではかなりの難しさがあり、実用化
には問題が多く、特に、前記の如く4ミクロン以上の深
い溝は著しく困難であるという問題があった。Furthermore, etching deep grooves in the silicon substrate1
As is well known, there are considerable difficulties in processing technology, and there are many problems in putting it to practical use.In particular, as mentioned above, it is extremely difficult to form deep grooves of 4 microns or more.
本発明は1以上のような問題を解決するためのもので、
キャパシタ間の距離を縮小して高密度に集積した半導体
装置およびその製造方法を提供することを目的とする。The present invention is directed to solving one or more of the following problems:
It is an object of the present invention to provide a semiconductor device that is highly integrated by reducing the distance between capacitors and a method for manufacturing the same.
(課題を解決するための手段)
本発明の半導体装置は、素子分離領域とMOSトランジ
スタのゲート電極とにより囲まれた半導体基板のN型拡
散領域に形成された溝の底面または側面の少なくとも一
部で前記N型拡散領域に接続されたMOS型キャパシタ
の下部電極が、前記素子分離領域とMOSトランジスタ
のゲート電極とに層間絶縁膜を介して覆い被さるように
積層され、層間絶縁膜および上部電極が前記下部電極を
覆い被さるような構造を有するMO3型キャパシタを含
むよう構成する。(Means for Solving the Problems) A semiconductor device of the present invention provides at least a portion of the bottom or side surface of a trench formed in an N-type diffusion region of a semiconductor substrate surrounded by an element isolation region and a gate electrode of a MOS transistor. The lower electrode of the MOS capacitor connected to the N-type diffusion region is laminated so as to cover the element isolation region and the gate electrode of the MOS transistor via an interlayer insulating film, and the interlayer insulating film and the upper electrode It is configured to include an MO3 type capacitor having a structure that covers the lower electrode.
(作 用)
本発明の半導体装置およびその製造方法によれば、溝型
キャパシタの欠点である溝の底でのパンチスルーを防止
し、メモリセルの高密度化が可能になる。また、従来の
積み上げ型キャパシタよりも、実効表面積の拡大により
メモリセル面積の縮小が可能となる。(Function) According to the semiconductor device and the manufacturing method thereof of the present invention, punch-through at the bottom of the trench, which is a drawback of trench-type capacitors, can be prevented, and memory cells can be densely packed. Furthermore, compared to conventional stacked capacitors, it is possible to reduce the memory cell area by increasing the effective surface area.
(実施例)
本発明を適用したDRAMの実施例を第1図(a)ない
しくh)の工程断面図からなる一部工程フローチャート
を参照しながら説明する。第2図はそのDRAMの実施
例の平面図の概略であり、第1図は第2図に示すx−x
’の断面図である。(Example) An example of a DRAM to which the present invention is applied will be described with reference to a partial process flowchart consisting of process cross-sectional views shown in FIGS. 1(a) to 1h). FIG. 2 is a schematic plan view of an embodiment of the DRAM, and FIG. 1 is a diagram showing x-x shown in FIG.
' is a sectional view of '.
先ず、P型シリコン基板1の主面に選択的にP−ウェル
領域15と素子分離領域2を形成する(第1図ではメモ
リセル部分のみ示したので、P−ウェルのみが表示され
ている)。素子分離領域2は第2図の領域31に囲まれ
た外側の部分で、第1図(a)に示す如く配置する。First, a P-well region 15 and an element isolation region 2 are selectively formed on the main surface of a P-type silicon substrate 1 (FIG. 1 shows only the memory cell portion, so only the P-well is shown). . The element isolation region 2 is an outer portion surrounded by the region 31 in FIG. 2, and is arranged as shown in FIG. 1(a).
次に、ワードライン(第2図32.32A参照)となる
アクセストランジスタloaを形成する。アクセストラ
ンジスタ10aは、ゲート絶縁膜9.ゲート電極10.
ソースドレインの領域となるN型拡散領域(以下、ソー
スドレイン拡散層という)11.111を第1図(b)
に示す如く構成する。層間絶縁膜16を第1図(Q)に
示す如く形成した後、素子分離領域31(第2図参照)
およびアクセストランジスタ。Next, an access transistor loa which becomes a word line (see FIG. 2, 32.32A) is formed. The access transistor 10a has a gate insulating film 9. Gate electrode 10.
Figure 1(b) shows an N-type diffusion region (hereinafter referred to as a source/drain diffusion layer) 11.111 which becomes a source/drain region.
It is configured as shown in . After forming the interlayer insulating film 16 as shown in FIG. 1(Q), the element isolation region 31 (see FIG. 2) is formed.
and access transistors.
ワードライン(第2図32A参照)によって囲まれた領
域に、写真食刻法により局間絶縁膜16.ソースドレイ
ン拡散層111およびシリコン基板1を連続してエツチ
ングし、溝17を第1図(d)に示す如く穿つ、第1図
(e)に示す如く、溝17の内壁に接して多結晶シリコ
ン膜19を堆積し、この多結晶シリコン膜19にリンを
拡散°し、導電性を与え、同時に溝17の基板1の表面
にN型拡散層18が形成され。An inter-station insulating film 16. is formed by photolithography in the area surrounded by the word line (see FIG. 2A). The source/drain diffusion layer 111 and the silicon substrate 1 are continuously etched to form a trench 17 as shown in FIG. 1(d). As shown in FIG. A film 19 is deposited and phosphorus is diffused into the polycrystalline silicon film 19 to give it conductivity, and at the same time an N-type diffusion layer 18 is formed on the surface of the substrate 1 in the groove 17.
ソースドレイン拡散M111と接続される。多結晶シリ
コン膜19をMOSキャパシタの下部電極(第2図34
参照)にパターン形成した後、キャパシタ絶縁膜5.第
2のN型多結晶シリコン膜(セルプレート)20を堆積
し、第2図35に示すセルプレートのパターンを第1図
(f)に示す如く形成する。Connected to source/drain diffusion M111. The polycrystalline silicon film 19 is used as the lower electrode of the MOS capacitor (FIG. 2, 34).
After forming a pattern on the capacitor insulating film 5. A second N-type polycrystalline silicon film (cell plate) 20 is deposited, and the cell plate pattern shown in FIG. 2 is formed as shown in FIG. 1(f).
次に、第1図(g)に示す如くセルプレート20上に第
2の層間絶縁膜21を堆積した後、ビットライン(第2
図36参照)の取り出し用の電極取り出し窓13を第1
図(h)に示す如く形成した後、ビットラインであるア
ルミ配線14を形成する。電極取り出し窓13を通じて
アルミ配線からなるビットライン14を接続することに
より、メモリセルが形成される。Next, as shown in FIG. 1(g), after depositing a second interlayer insulating film 21 on the cell plate 20, a bit line (second
(see FIG. 36).
After forming as shown in Figure (h), aluminum wiring 14 which is a bit line is formed. A memory cell is formed by connecting a bit line 14 made of aluminum wiring through the electrode extraction window 13.
なお、図中保護膜は省略した。Note that the protective film is omitted in the figure.
本実施例による方法で、P−ウェル内にMO3型キャパ
シタの一部を埋め込んだ場合、従来の溝型キャパシタセ
ルと異なり、シリコン基板1に形成された溝17の内壁
だけでなく、ゲート電極10゜101、素子分離領域2
による段差部分、およびゲート電極5,51.素子分離
領域2の上部の面積をも利用しており、従来の溝型キャ
パシタセルと同じく、開口の直径を1.0μ隠、絶縁膜
10n■とすると。When a part of the MO3 type capacitor is buried in the P-well by the method according to this embodiment, unlike a conventional trench type capacitor cell, not only the inner wall of the trench 17 formed in the silicon substrate 1 but also the gate electrode 10 is buried. °101, element isolation region 2
and the gate electrodes 5, 51 . The upper area of the element isolation region 2 is also utilized, and the diameter of the opening is 1.0 μm and the insulating film is 10 nm thick, as in the conventional trench type capacitor cell.
溝の深さは約1〜2μmで40fFを確保できる。従来
の溝型キャパシタ形成方法では、表面濃度がlX101
7/adの場合、4μ−の深さで5X10”/cdとな
り、溝型キャパシタ間の間隔が1.4JJIlでパンチ
スルー電圧が約2■であり、溝の深さ方向に限界がある
。本実施例による方法では、深さが2μ−以下となり、
かつN型多結晶シリコン膜19がMOSキャパシタの下
部電極となるため、パンチスルー電圧が溝の深さや溝間
距離による影響を受けにくく、IOV以上に改善された
。The depth of the groove is about 1 to 2 μm, and 40 fF can be secured. In the conventional trench capacitor formation method, the surface concentration is 1×101
In the case of 7/ad, it is 5X10"/cd at a depth of 4μ-, and the gap between groove capacitors is 1.4JJIl, the punch-through voltage is about 2μ, and there is a limit in the depth direction of the groove.This book In the method according to the embodiment, the depth is 2μ or less,
In addition, since the N-type polycrystalline silicon film 19 serves as the lower electrode of the MOS capacitor, the punch-through voltage is less affected by the depth of the grooves and the distance between the grooves, and is improved to more than the IOV.
(発明の効果)
本発明の半導体装置の製造方法によれば、シリコン基板
に形成された溝の内壁だけでなく、ゲート電極、素子分
離領域による段差部分、およびゲート電極、素子分離領
域の上部の面積をも利用しており、従来の溝型キャパシ
タセルと同じく、開口の直径を1.0μ鳳、絶縁膜10
nmとすると、溝の深さは約1〜2μ陽で40fFを確
保できる。さらに。(Effects of the Invention) According to the method of manufacturing a semiconductor device of the present invention, not only the inner wall of the groove formed in the silicon substrate but also the step portion formed by the gate electrode and the element isolation region, and the upper part of the gate electrode and the element isolation region are The area is also utilized, and the diameter of the opening is 1.0 μm and the insulating film is 10 μm, just like the conventional trench type capacitor cell.
Assuming that the groove depth is approximately 1 to 2 μm, 40 fF can be secured. moreover.
溝部の深さ方向によるボロン濃度分布の変化による影響
を受けに<<、パンチスルー電圧の低下が少なく、キャ
パシタ間の距離の縮小を可能にした。Due to the effect of changes in the boron concentration distribution in the depth direction of the groove, the punch-through voltage decreases little, making it possible to reduce the distance between capacitors.
第1図(a)ないしくh)は本発明の半導体装置の製造
方法を適用したDRAMの製造方法の一部工程断面図に
よるフローチャート、第2図はその概略平面図、第3図
は従来の製造方法を適用したDRAMの構造断面図を示
す。
5・・・キャパシタ絶縁膜、 17・・・溝、 18
・・・N型拡散層、 19・・・N型多結晶シリコン膜
、20・・・第2のN型多結晶シリコン層。
特許出願人 松下電子工業株式会社
第1 因
第1 因
1−1)型ン)っ>J4*
15・・−p−ウ1ル横域
(e)
17・・−噴。
(c)
9・・−イZ目eすI逢
10.101−・汀;)’I#
11.111.・・N’!i’陥Ik璧橢戒18・−N
型憾(→
19・−NJ!l!吟台括′轟シリつンーシ+6−−−
、愉!Ifl髪11懺
5・−・2slぐシタ 會亡J−引欄麺20・・弓酬二
のN’j’f’@&シリっ、暖(h)
13−・セ俗嗟砂眉セリ出し5
14−一−べ1しミ(ヒ線
第
31−・11卆薙惜属
32 32A−一−ワーμライン
33−・へ11−rコンタクμ1(a) to h) are flowcharts showing partial process cross-sectional views of a DRAM manufacturing method to which the semiconductor device manufacturing method of the present invention is applied, FIG. 2 is a schematic plan view thereof, and FIG. 3 is a conventional A structural cross-sectional view of a DRAM to which the manufacturing method is applied is shown. 5... Capacitor insulating film, 17... Groove, 18
...N type diffusion layer, 19...N type polycrystalline silicon film, 20...2nd N type polycrystalline silicon layer. Patent applicant: Matsushita Electronics Co., Ltd. No. 1 No. 1 No. 1-1) Model n) J4 * 15...-p-Ul horizontal area (e) 17...-Jump. (c) 9...-I Z eyes I meet 10.101-・怀;)'I# 11.111. ...N'! i' fall Ik peku precept 18・-N
Type hatred (→ 19・-NJ!l! Gindai bracket 'Todoroki Shiritsunushi +6---
, Enjoy! Ifl hair 11 5 - 2 sl gushita death J - side noodles 20... Yumi Shuuji's N'j'f' @ & Siri, warmth (h) 13 - se vulgar sand eyebrows seri 5 14-1-be 1 Shimi (hi line 31-・11 volume 32 32A-1-wa μ line 33-・11-r contact μ
Claims (2)
とにより囲まれた半導体基板のN型拡散領域に形成され
た溝の底面または側面の少なくとも一部で前記N型拡散
領域に接続されたMOS型キャパシタの下部電極が、前
記素子分離領域とMOSトランジスタのゲート電極とに
層間絶縁膜を介して覆い被さるように積層され、層間絶
縁膜および上記電極が前記下部電極を覆い被さる構造を
有するMOS型キャパシタを含む半導体装置。(1) A MOS capacitor connected to the N-type diffusion region at least part of the bottom or side surface of a trench formed in the N-type diffusion region of the semiconductor substrate surrounded by the element isolation region and the gate electrode of the MOS transistor. A MOS type capacitor having a structure in which a lower electrode is stacked so as to cover the element isolation region and a gate electrode of a MOS transistor via an interlayer insulating film, and the interlayer insulating film and the electrode cover the lower electrode. Semiconductor devices including.
OSトランジスタを形成する工程と、前記MOSトラン
ジスタのゲート電極と素子分離領域とにより囲まれた半
導体基板のN型拡散領域に溝を形成する工程と、溝の底
面、側面および前記素子分離領域とMOSトランジスタ
のゲート電極とに層間絶縁膜を介して覆い被さるように
N型多結晶シリコンを形成し、前記N型多結晶シリコン
が前記N型拡散領域に溝の底面または側面の少なくとも
一部で接続される工程と、前記N型多結晶シリコンから
なる下部電極をキャパシタ用絶縁膜および上部電極を堆
積し被覆することによりMOS型キャパシタを形成する
工程とを含むことを特徴とする半導体装置の製造方法。(2) An element isolation region and M on the main surface of a semiconductor substrate of one conductivity type.
a step of forming an OS transistor; a step of forming a trench in an N-type diffusion region of a semiconductor substrate surrounded by the gate electrode of the MOS transistor and an element isolation region; N-type polycrystalline silicon is formed so as to cover the gate electrode of the transistor via an interlayer insulating film, and the N-type polycrystalline silicon is connected to the N-type diffusion region at least part of the bottom or side surface of the trench. 1. A method for manufacturing a semiconductor device, comprising: forming a MOS capacitor by depositing and covering the lower electrode made of N-type polycrystalline silicon with a capacitor insulating film and an upper electrode.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP63268090A JPH02116160A (en) | 1988-10-26 | 1988-10-26 | Semiconductor device and manufacture thereof |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP63268090A JPH02116160A (en) | 1988-10-26 | 1988-10-26 | Semiconductor device and manufacture thereof |
Publications (1)
Publication Number | Publication Date |
---|---|
JPH02116160A true JPH02116160A (en) | 1990-04-27 |
Family
ID=17453751
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP63268090A Pending JPH02116160A (en) | 1988-10-26 | 1988-10-26 | Semiconductor device and manufacture thereof |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPH02116160A (en) |
Cited By (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
FR2667984A1 (en) * | 1990-10-11 | 1992-04-17 | Samsung Electronics Co Ltd | DYNAMIC MEMORY CELL WITH DIRECT ACCESS AND METHOD FOR MANUFACTURING SUCH CELL. |
US5196363A (en) * | 1990-10-11 | 1993-03-23 | Samsung Electronics Co., Ltd. | Method of forming mist type dynamic random access memory cell |
US5202279A (en) * | 1990-12-05 | 1993-04-13 | Texas Instruments Incorporated | Poly sidewall process to reduce gated diode leakage |
US5217918A (en) * | 1990-08-14 | 1993-06-08 | Samsung Electronics Co., Ltd. | Method of manufacturing a highly integrated semiconductor memory device with trench capacitors and stacked capacitors |
US5411911A (en) * | 1992-10-27 | 1995-05-02 | Sanyo Electric Co., Ltd. | Process for producing DRAM semiconductor devices |
Citations (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS61177771A (en) * | 1985-02-04 | 1986-08-09 | Mitsubishi Electric Corp | Manufacture of semiconductor device |
JPS6384149A (en) * | 1986-09-29 | 1988-04-14 | Hitachi Ltd | Manufacture of semiconductor memory |
JPH01119053A (en) * | 1987-10-31 | 1989-05-11 | Sony Corp | Semiconductor memory device |
-
1988
- 1988-10-26 JP JP63268090A patent/JPH02116160A/en active Pending
Patent Citations (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS61177771A (en) * | 1985-02-04 | 1986-08-09 | Mitsubishi Electric Corp | Manufacture of semiconductor device |
JPS6384149A (en) * | 1986-09-29 | 1988-04-14 | Hitachi Ltd | Manufacture of semiconductor memory |
JPH01119053A (en) * | 1987-10-31 | 1989-05-11 | Sony Corp | Semiconductor memory device |
Cited By (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5217918A (en) * | 1990-08-14 | 1993-06-08 | Samsung Electronics Co., Ltd. | Method of manufacturing a highly integrated semiconductor memory device with trench capacitors and stacked capacitors |
FR2667984A1 (en) * | 1990-10-11 | 1992-04-17 | Samsung Electronics Co Ltd | DYNAMIC MEMORY CELL WITH DIRECT ACCESS AND METHOD FOR MANUFACTURING SUCH CELL. |
US5196363A (en) * | 1990-10-11 | 1993-03-23 | Samsung Electronics Co., Ltd. | Method of forming mist type dynamic random access memory cell |
US5202279A (en) * | 1990-12-05 | 1993-04-13 | Texas Instruments Incorporated | Poly sidewall process to reduce gated diode leakage |
US5411911A (en) * | 1992-10-27 | 1995-05-02 | Sanyo Electric Co., Ltd. | Process for producing DRAM semiconductor devices |
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