JPS6221266A - Semiconductor memory cell - Google Patents

Abstract

PURPOSE:To reduce the area of a memory cell, by forming the memory cell, which is formed by two MOSFETs and an electrostatic capacitor, which is connected between the MOSFETs, by utilizing a groove shaped electrostatic capacitor. CONSTITUTION:On a P<+> type of N<+> type semiconductor substrate 1 having high impurity concentration, a P-type epitaxial layer 2 is laminated and formed by an epitaxial growing method. A groove 4 is formed in the surface of the layer 2 at an element forming part so as to reach the Si substrate 1 by anisotropic etching. MOSFETs 8 and 9 are formed on both sides of the groove 4. The MOSFET 8 is constituted by an N<+> region 10, which is extended to the side surface of the groove 4, another N<+> region 11, which is separately provided on the surface of the layer 2, and a gate layer 14. The gate layer 14 comprises a poly Si layer 13, which is provided on a channel region 12 between both N<+> regions 10 and 11 through a gate oxide film 5. Both N<+> regions 10 and 15, which are extended to both side surfaces of the groove 4, form an electrostatic capacitor between capacitor electrodes 7. This structure is equivalent to the series circuits of the two electrostatic capacitors, which are formed between the MOSFETs.

Description

DETAILED DESCRIPTION OF THE INVENTION (A) Field of Industrial Application The present invention relates to semiconductor memory cells, and particularly to dynamic memory cells using MOS transistors.

(b) Prior Art In recent years, the memory capacity of D-RAMs has been increasing from 256 bits to more than IM bits as the density of integration has progressed with the development of microfabrication technology. Like this-R
In AM, a one-transistor type memory cell is generally used to reduce the chip area. A one-transistor type memory cell consists of a MOS transistor that is switched by a word line and a capacitor that holds data in the form of stored charge.

The conventional D-RAM was published in "Nikkei Electronics" published on July 18, 1981, from page 169 to page 1.
As described on page 93, a sense amplifier whose basic components are seven lip-flops is used to sense the data stored in the memory cells, and a pair of bit lines and a number of word lines derived from the sense amplifier are used to sense the data stored in the memory cells. A memory cell is arranged between the two bit lines, and one dummy cell is provided on each of the pair of bit lines. The capacitance of the dummy cell is formed to be approximately 1/2 of the capacitance of the memory cell, and zero charge is stored in order to bring one of the bit lines to a reference potential for comparison. When reading data, the electric charge accumulated in the capacitance of the memory cell selected by the word line, the electric charge precharged in the bit line to which the memory cell is connected, and the combined potential of K are applied to one side. A potential is generated on the bit line, and a potential synthesized by the precharged charge and the dummy cell charge is generated on the other bit line, and a sense amplifier detects the potential difference between the pair of bit lines.

(c) Problems to be Solved by the Invention However, as the degree of integration increases from 256 bits to IM bits and above, the capacitance of memory cells and dummy cells becomes smaller, and a potential difference occurs between a pair of bit lines. Furthermore, manufacturing variations have a greater effect on the capacitance of memory cells and dummy cells individually, and variations in the potential difference between a pair of bit lines also increase, making it possible to improve the sensitivity of the sense amplifier. There must be. This causes the disadvantage that the sense amplifier occupies a large proportion of the chip, and the detection speed also decreases. Furthermore, wiring is required to connect one end of the conventional memory cell's capacitance to a common potential and wiring to connect one end of the dummy cell's capacitance to a predetermined potential, resulting in an increase in cell area. There is.

B) Means for Solving the Problems The present invention has been made in view of the above-mentioned points, and includes a gate with one end connected to the other bit line between a pair of bit lines derived from a sense amplifier. a first MOSFET whose one end is connected to one word line, and a first MOSFET whose gate is connected to the other bit line.
A second MOSFET connected to the same word line connected to T, and an xth MOSFET, ! = [MO of 2
The capacitance of the memory cell connected to each bit line is buried in the groove (4) provided on the surface of the epitaxial layer (2), and the capacitance is connected between the SFETs. A capacitor electrode (7) in contact with the substrate (1)
) and N regions 1o)a of the first and second MOSFETs
It is formed between s.

(E) Effect According to the present invention, WJl and the second MOSFET (
Since the memory cell formed by 81+9+ and the capacitance connected therebetween is formed by a groove-shaped capacitance, the area of the memory cell can be reduced.

(f) Example FIG. 1 shows an embodiment of the present invention.

In FIG. 1, a P-type epitaxial layer (2) is laminated and formed by an epitaxial growth method on a P-type or N+-type semiconductor substrate (1) with a high impurity concentration, and a LOCO8 thicker field oxide (3
) is formed.

A groove (4) is formed on the surface of the epitaxial layer (2) in the element forming portion by anisotropic etching until it reaches the silicon substrate (1). A gate oxide film (5) is deposited in the trench (4), and after removing the gate oxide film (5) at the bottom of the trench (4) by anisotropic etching, a first polysilicon layer is deposited in the trench (4). (6> bt is buried to form a capacitor electrode (7).

A first MOSFET (8) and a second MOSFET 19) are formed on both sides of the groove (4).
S FET (8) is an N
A second polyurethane layer is formed on the channel region 02 between the region α0 and the other +N region aυ provided at a distance on the surface of the epitaxial layer (2), and both N regions α0)Qlj via a gate oxide film (5). It is composed of a gate electrode (t4) made of silicon layer α3, and the second MOS FET (9) is I'JI (4).
A gate oxide film (5) is formed on the N region α9 extending on the opposite side surface, the other N region σe provided at a distance on the surface of the epitaxial layer (2), and the channel region αη between both N regions 090e. A gate electrode (18) made of a second polysilicon layer α3 is interposed therebetween.

Both N areas (IOIQ) extending on both sides of the groove (4)
S is the capacitor electrode (7) via the gate oxide film (5)
This is equivalent to connecting two capacitances in series with each MO8FET. In particular, since the capacitor electrode (force is fixed by biasing the substrate potential), the capacitance can be reliably doubled. Note that both N regions α0) 09 are extended to reach the semiconductor substrate (1), Obtaining as large a capacitance as possible.

The capacitor electrode (the surface of which is covered with an oxide film Ql, and a second polysilicon layer (a) is extended on this oxide film (q!J) and connects the gate electrodes tt4Jas of both MO8FETs. Furthermore, a second polysilicon layer 0■ is covered with a PSG layer (A), and An
A wiring layer 011 is provided, a second polysilicon layer αJ, and! The wiring layer 01) is connected to the wiring layer 01). while the first and second
The other N region (11) αe of MOS FET (8) and (9) serves as bit lines BL and BL, and the above-mentioned memory cells are connected in series between the bit lines.

Next, FIG. 2 shows a circuit diagram of a memory using the memory cell of the present invention described above. The sense amplifier C31) includes a MOS FE Te131:(3) whose gates and drains are connected across each other to form a flip-flop, and a pair of bit lines BL and MOS transistors derived from the drains of each MO8FETC33 (to). MOS F E TG4 for precharging electric charge to BL! MO8FE to start the sensing operation of sense amplifier 01).
MOS connected between each source of TC33 (to) and ground
It is composed of FET (g). A number of word lines W are provided on the pair of bit lines BL and Ding Ding.

~W nb′- orthogonal to each other, and the memory cell c3 is located at the intersection.
7) are provided respectively. The memory cell c3η is a first MOSFET (
) and a second M whose one end is connected to the bit line BL.
O8FETGI, the capacitance (
4G, the first MOSFET (to) and the 20th MOSFET
The gates of M0SFETGI are connected to the same word line W.
, ~3 connected to Wn, thus the word line W, ~
When one of W111 is selected, K is the first MOSFET connected to that word line and the second MOSFET connected to that word line.
The OSFET (3!11) is turned on and both ends of the capacitor (4G) are connected to the pair of bit lines BL and BL.

Capacitance! (Data is stored in 41 by charging +Vc port or -Vc volts. In other words, +q charge is placed on the electrode side of @10M08FET (to) and -q charge is placed on the electrode side of the second MOSFET device. If the data is ``1n'' when charged, the data is ``O'' in the opposite case.Due to the charge accumulated in this capacitance (4(+)),
When the capacitance (4) is connected to the pair of bit lines BL and BL'', a potential difference occurs between the pair of bit lines BL and BL''.

FIG. 3 is a waveform diagram illustrating the read operation of the embodiment shown in FIG. 2. First, when the clock φp becomes ``H'', the MO8FETC341 (g) is turned on, and the bit lines BL and τ are precharged to a potential of 1/2 of the power supply Vcc.The clock φp becomes ``L'', and the MO8FET04 turns on. ) When the 3rd line turns off, the bit line BL
The potentials of and BL are held at the potential of Lvcc, and then,
One of the word lines W, ~Wn Wi (i=1, 2・
=n) becomes @HII, the first MOSFET (38) and the second MOSFET (38) connected to the word line Wi
FETC3! J is turned on and capacitance (40 is connected to bit line BL and 100τ. At this time, capacitance (+q
, when the electrode on the second MO3FETC3'1 side is charged with -q, the potential of the bit line BL rises from the potential of TVCC by the amount of charge +q, while the potential of the bit line τ is Since the potential of fTVcc is lowered by the amount of charge -q, a potential difference is generated between the bit line BL and the bit line τ. Then, when the clock φS becomes H' and MOSFET 2 is turned on, MO8FETC32
The source potential of 1 (to) is gradually lowered to the ground potential, and due to the feedback action of the flip-flop, the bit line B
Since the charge on L is discharged through the MOSFETs (to) and (to), its potential becomes close to the ground level, and the potential difference between the bit lines BL and τ is amplified.

FIG. 4 is a pattern diagram laid out based on the configuration shown in FIG. 1. In FIG. 4, (41) is an N region forming a pair of bit lines BL and BL, and between the N regions (41), four trench-shaped static capacitors are formed. N+ region 41) and trench capacitance (4
The second polysilicon layer (c) is an 8g2 polysilicon layer that forms the gate electrode between the bit lines BL and the Afi wiring layer (44) that forms the word line orthogonal to the BL, and the contact area (49). Figure 5 is a pattern diagram laid out based on a configuration different from that in Figure 4, with the first MOSF on both sides of the trench-shaped static capacitor.
ET country and second MO8FETC3! An island-shaped N 2 region (47) is provided, which is one of the regions of L. (4) A polysilicon layer forming a word line, and a groove-shaped capacitor (4) extending between the 4υ and N regions (47) to form a gate electrode. The bit lines BL and Ding are formed by the AJ wiring layer (4), and the Afi wiring layer (4ω) and the N region (47) in the direction of each bit line are connected by a contact region 6G.

In any of the patterns shown in FIGS. 4 and 5, as in the circuit diagram shown in FIG. 2, the first MO8FET GS and the z-th
The MO8FETr31 and the capacitance are connected in series. .

(G) Effects of the Invention As described above, according to the present invention, the capacitance of the memory cell is realized by the capacitor electrode (8) embedded in the groove (5), so the chip area of the memory cell can be reduced. There are advantages that can be achieved.

Further, in the present invention, the capacitor 'I! Since the capacitor electrode (7) is in contact with the semiconductor substrate fil, the potential of the capacitor electrode (7) can be fixed to the substrate potential, which has the advantage of allowing stable use of capacitance. It has the advantage of being completely unnecessary.

Furthermore, in the present invention, the wiring pattern b' on the D-RAM chip is simple, since the dummy cell b' is unnecessary and the wiring connecting one end of the capacitance of the memory cell to a predetermined common potential is not required. This has the advantage of reducing the chip area.

Furthermore, instead of sensing the potential difference on a pair of bit lines caused by two different capacitances, such as the capacitance of a memory cell and the capacitance of a dummy cell, the difference in potential on a pair of bit lines caused by one capacitance is sensed. Because it senses the potential difference on the bit line, there is no offset voltage caused by manufacturing variations in capacitance, making it possible to make the sense amplifier more sensitive than necessary, or to increase the capacitance of the memory cell more than necessary. Therefore, the area occupied by the sense amplifier can be reduced without sacrificing sensing speed, and a memory with the same capacity can be realized.

[Brief explanation of drawings]

FIG. 1 is a sectional view illustrating a semiconductor memory cell according to the present invention, and FIG. 2 is a D-rLAM using the memory cell according to the present invention.
A circuit diagram explaining the circuit, Fig. 3 is a waveform diagram showing the operation of the D-RAM circuit of Fig. 2, Fig. 4 is a pattern diagram laid out based on the memory cell of Fig. 1, and Fig. 5 is another diagram FIG. 2 is a pattern diagram showing the layout of FIG. Explanation of the main drawing numbers (1) is the semiconductor substrate, (2) is the epitaxial layer, (3)
) is the field oxide film, (4) is the trench, (5) is the gate oxide film, (cover capacitor electrode, (8) is the first MOS
FET. (9) C2+7) MOS FET, (10) (15
) C area, n4) as is gate electrode, ■ is PSG
Layer C+) is the A1 wiring layer. Applicant: Sanyo Electric Co., Ltd. and 1 other representative: Shizuo Sano, patent attorney Figure 1 Figure 2 Figure 3 Figure 4 Figure 5

Claims (1)

[Claims] (1) A high impurity concentration semiconductor substrate of one conductivity type or the opposite conductivity type, an epitaxial layer of one conductivity type laminated on the substrate, a groove provided on the surface of the epitaxial layer and reaching the substrate, and a groove buried in the groove. and a capacitor electrode in contact with the substrate, two MIS transistors provided on the surface of the epitaxial layer adjacent to the groove, and diffusion regions of opposite conductivity types of the MIS transistors extending to the sides of the groove to a capacitor formed between capacitor electrodes, the gate electrode of the MIS transistor is connected to a word line, the other diffusion region of the opposite conductivity type of the MIS transistor is connected to a bit line, and the capacitor electrode is connected to the substrate. A semiconductor memory cell characterized by being held at a fixed potential through a memory cell.