JPH0642533B2 - Semiconductor memory device - Google Patents

Description

The present invention relates to a semiconductor memory device.

[Conventional technology]

FIG. 3 is a cross-sectional view showing a memory cell structure of a conventional one-transistor one-capacity semiconductor memory device, where 1 is a p-type semiconductor substrate, 2 is a thick silicon oxide film serving as an isolation region, 3 is a source and a capacitor. N ⁺ diffusion layer to be one electrode,
Reference numeral 4 is an n ⁺ diffusion layer that will be a drain and a bit line, 5 is a thin silicon oxide film for forming a charge storage region, 6 is a first polysilicon layer that will be the other electrode of the capacitor,
Reference numeral 7 is a silicon oxide film which will be a gate oxide film of a MOS transistor, 8 is a second polysilicon layer which will be a gate electrode of a MOS transistor, and 9 is the second polysilicon layer 8 described above.
The silicon oxide film 10 covering the p-type semiconductor substrate 1 except a part above is an aluminum wiring which becomes a word line.

Next, the manufacturing process will be described.

First, a thick silicon oxide film 2 serving as an isolation region is formed in a p-type semiconductor substrate 1. Then to form the n ⁺ diffusion layer 4 of the n ⁺ diffusion layer 3 and the drain and the bit line to be one electrode of the source and the capacitor. Then, a thin silicon oxide film 5 is formed to form a charge storage region. Next, in order to form the other electrode of the capacitor, the first polysilicon layer 6 is inserted so as to sandwich the thin silicon oxide film 5.
To form. Then, a silicon oxide film 9 is grown on the first polysilicon layer 6 and a silicon oxide film 7 is formed to form a MOS structure. Then, a second polysilicon layer 8 to be a gate electrode is formed. Then, a silicon oxide film 9 is formed also on the second polysilicon layer 8, and then a contact hole is formed in the second polysilicon layer 8. Finally, a semiconductor memory device is formed by providing aluminum wiring 10 connected to polysilicon layer 8 on silicon oxide film 9.

[Problems to be solved by the invention]

In the conventional semiconductor memory device as described above, when increasing the storage capacity, the area of the capacitor region cannot be reduced due to the limit of the capacity of the capacitor forming the memory cell. However, there is a problem in that it cannot be miniaturized.

The present invention has been made in order to solve such a problem, and an object thereof is to obtain a semiconductor memory device which can be miniaturized without reducing the capacitance of a capacitor forming a memory cell.

[Means for solving problems]

A semiconductor memory device according to the present invention includes an isolation region formed on a substrate of a first conductivity type to separate a capacitor region and a transistor region, and a second conductivity type high impurity formed in a capacitor region. The first semiconductor layer having a high concentration, the second and third semiconductor layers having a second conductivity type and a high impurity concentration formed in the transistor region, and the first semiconductor layer and the first semiconductor layer are formed in parallel with each other with an insulating film interposed therebetween. A second conductor layer, a part of which is connected to the first semiconductor layer, and the second conductor layer and the first conductor layer.
Formed between two semiconductor layers with an insulating film between them
A first conductor layer connected to the first semiconductor layer and a third conductor layer formed above the second and third semiconductor layers via an insulating film.
Of the conductor layer, the insulating film covering the substrate except the partial region of the third semiconductor layer, and the metal wiring connected to the partial region of the third semiconductor layer.

[Action]

In the present invention, the charge storage region is formed between the first conductor layer and the first semiconductor layer and between the first conductor layer and the second conductor layer, and the capacitance of the capacitor region increases.

[Embodiment] FIGS. 1 (a) and 1 (b) are a sectional view and a plan view showing an embodiment of a memory cell structure of a semiconductor memory device of the present invention, in which 11 is a p-type semiconductor substrate and 12 is an isolation region. A silicon oxide film, 13 is an n ⁺ diffusion layer which is a first semiconductor layer, 14 is an n ⁺ diffusion layer which is a second semiconductor layer, 15 is an n ⁺ diffusion layer which is a third semiconductor layer, 16, Reference numeral 17 is a thin silicon oxide film for forming a charge storage region, 18 is a first polysilicon layer which is a first conductor layer, 19 is a second polysilicon layer which is a second conductive layer, and 20 is a second polysilicon layer. A third polysilicon layer which is a conductive layer of 3 and serves as a word line, 21 is a silicon oxide film which is an insulating film covering the p-type semiconductor substrate 11 except a part of the n ⁺ diffusion layer 15, 22 Is an aluminum wiring to be a bit line.

Next, the manufacturing process will be described.

First, a silicon oxide film 12 serving as an isolation region for isolating a capacitor region and a transistor region is formed in a p-type semiconductor substrate 11. Next, an n ⁺ diffusion layer 13 which is a first semiconductor layer is formed on the entire surface of the capacitor region. The n ⁺ diffusion layer 13 is connected to V _SS , V _CC or another constant voltage source. At the same time, n ⁺ diffusion layers 14 and 15 which are the second and third semiconductor layers serving as the source and drain of the MOS transistor are formed in the transistor region. Then, a thin silicon oxide film 16 is formed to form a charge storage region.
To form. Then, a first polysilicon layer 18 which is a first conductor layer is selectively formed for each bit unit, and one end thereof is connected to the n ⁺ diffusion layer 14 through a contact hole. The bit line unit isolation is the first polysilicon layer 1
A thin silicon oxide film 17 for forming a charge storage region is formed on the upper surface of the first polysilicon layer 18 determined by the patterning accuracy of 8. Then, a second polysilicon layer 19 which is a second conductor layer is formed. At this time, the second polysilicon layer 19 contacts the n ⁺ diffusion layer 13 without contacting the first polysilicon layer 18. It is formed so as to be connected through a hole. At the same time, the third polysilicon layer 2 which is the third conductor layer serving as the word line is formed.
Form 0. Next, after covering the p-type semiconductor substrate 11 with the silicon oxide film 21, a contact hole for connecting the n ⁺ diffusion layer 15 and the aluminum wiring 22 is formed in the silicon oxide film 21, and then the aluminum wiring 22 is formed. Form.

In this semiconductor memory device, charge storage regions are formed between the n ⁺ diffusion layer 13 and the first polysilicon layer 18 and between the first polysilicon layer 18 and the second polysilicon layer 19, so that The capacity is increased, and the area of the capacitor region can be reduced. In addition, n ⁺ diffusion layer 1
The contact of the aluminum wiring 22 to 5 is one every two bits, which is a structure useful for improving the degree of integration. Furthermore, since the capacitor region is the entire active region, the memory cell isolation can be determined only by the patterning accuracy of the first polysilicon layer 18.

2 (a) and 2 (b) are a sectional view and a plan view showing another embodiment of the memory cell structure of the semiconductor memory device of the present invention.
The same reference numerals as those in the figure indicate the same parts, and 23 is a groove formed in the p-type semiconductor substrate 11.

Next, the manufacturing process will be described.

First, the silicon oxide film 12 to be an isolation region is formed on the p-type semiconductor substrate 11. Next, a groove 23 which will be a capacitor region is formed. Next, the n ⁺ diffusion layer 13 is formed in the groove 23. At the same time, n ⁺ diffusion layers 14 and 15 serving as the source and drain of the MOS transistor are formed. Then, a thin silicon layer 16 for forming a charge storage region is formed on the surface of the n ⁺ diffusion layer 13. Then the first
Is formed from the groove 23 to the transistor region, and one end of the polysilicon layer 18 is connected to the n ⁺ diffusion layer 14 through a contact hole. Then, a thin silicon oxide film 17 for forming a charge storage region is formed so as to cover the surface of the first polysilicon layer 18. Then, the second polysilicon layer 19 is formed. The second polysilicon layer 19 is connected to the n ⁺ diffusion layer 13 via a deep contact hole. At this time, at the same time, the third polysilicon layer 20 to be the word line is also formed. Next, after covering the p-type semiconductor substrate 11 with the silicon oxide film 21, a contact hole for connecting the n ⁺ diffusion layer 15 and the aluminum wiring 22 is formed in the silicon oxide film 21, and then the aluminum wiring 22 is formed. Form.

In this semiconductor memory device, between the n ⁺ diffusion layer 13 and the first polysilicon layer 18 and between the first polysilicon layer 18 and the second polysilicon layer 19 in the groove 23 formed in the p-type semiconductor substrate 11. Since the charge storage region is formed in the capacitor region, the capacitance of the capacitor region increases and the area of the capacitor region can be further reduced.

Although the silicon oxide film 21 is used as the insulating film in the above embodiment, the present invention is not limited to this, and a silicon nitride film or a laminated film of a silicon oxide film and a silicon nitride film may be used.

EFFECTS OF THE INVENTION As described above, according to the present invention, an isolation region formed on a substrate of a first conductivity type for separating a capacitor region and a transistor region, and a second conductivity formed in the capacitor region. Through a first semiconductor layer of high conductivity type having a high impurity concentration, second and third semiconductor layers of a second conductivity type having a high impurity concentration formed in the transistor region, and the first semiconductor layer and an insulating film. A second conductor layer, which is formed substantially in parallel and a part of which is connected to the first semiconductor layer, is formed with an insulating film between the second conductor layer and the first semiconductor layer, and one end of which is the second layer. A first conductor layer connected to the semiconductor layer, a third conductor layer formed above the second and third semiconductor layers via an insulating film, and a partial region of the third semiconductor layer. Except for the insulating film that covers the substrate and connects to a partial region of the third semiconductor layer Since the semiconductor memory device is composed of the formed metal wiring, it is possible to apply a potential to the first conductive layer independently of the substrate. Further, a charge storage region is formed between the first conductor layer and the second semiconductor layer and between the first conductor layer and the second conductor layer without external connection wiring, and the capacitance of the capacitor region is increased. Since the area of the region can be reduced, the semiconductor memory device can be downsized.

[Brief description of drawings]

1 (a) and 1 (b) are a sectional view and a plan view showing an embodiment of a memory cell structure of a semiconductor memory device of the present invention, and FIG.
(a) and (b) are a sectional view and a plan view showing another embodiment of the memory cell structure of the semiconductor memory device of the present invention, and FIG. 3 is a sectional view showing the memory cell structure of the conventional semiconductor memory device. . In the figure, 11 is a p-type semiconductor substrate, 12 is a silicon oxide film, 13, 14 and 15 are n ⁺ diffusion layers, 16 and 17 are thin silicon oxide films, 18 is a first polysilicon layer, 1
Reference numeral 9 is a second polysilicon layer, 20 is a third polysilicon layer, 21 is a silicon oxide film, and 22 is an aluminum wiring. The same reference numerals in each drawing indicate the same or corresponding parts.

Claims (1)

[Claims] 1. An isolation region formed on a substrate of a first conductivity type for separating a capacitor region and a transistor region, and a second conductivity type formed in the capacitor region and given a predetermined potential. A high impurity concentration first semiconductor layer, second conductivity type high impurity concentration second and third semiconductor layers formed in the transistor region, and the first semiconductor layer
A second conductor layer which is formed substantially parallel to the semiconductor layer via an insulating film and a part of which is connected to the first semiconductor layer,
A first conductor layer formed between the second conductor layer and the first semiconductor layer via an insulating film, one end of which is connected to the second semiconductor layer; and the second and third semiconductor layers. A third conductor layer formed above the substrate via an insulating film, an insulating film covering the substrate except a partial region of the third semiconductor layer, and a partial region of the third semiconductor layer A semiconductor memory device comprising a metal wire connected to the.