JPS62156856A - Dynamic memory cell and manufacture thereof - Google Patents

Abstract

PURPOSE:To ensure reliable element isolation and enhanced integration by a method wherein an element-isolating insulating film is formed by thermal oxidation on the bottom of a groove provided in a semiconductor substrate and a capacitor cell is built on the side walls of the groove. CONSTITUTION:A groove is provided in a silicon substrate 15, a first oxide film 22 is formed on the side wall of the groove, and a field oxide film 20 is formed on the bottom of the groove. A first polycrystalline silicon layer 23 and N<+> diffusion layer 21 are formed with the first gate oxide film 22 sandwiched between them, for the construction of a capacitor. A transistor is built of a second gate oxide film 24, second polycrystalline layer 25, N<+> source.drain regions 26, 27, which reads out electric charges. On them all, a CVD oxide silicon layer 28 is formed, whereon an aluminum.silicon layer 29 is formed. The layer 29 is allowed to contact the N<+> source.drain layer region 27 with the intermediary of a contact hole, by which electric charges are read out. With a memory cell being of a trench-type structure, an ample capacitor area may be provided in a small region.

Description

DETAILED DESCRIPTION OF THE INVENTION [Technical Field of the Invention] The present invention relates to a dynamic memory cell and a method of manufacturing the same.

[Technical background of the invention]

A dynamic memory cell is generally represented by a circuit such as the one shown in FIG. Charge is stored in capacitor 33, and this stored charge is read out to pin 1-line 30 via switching transistor 32 controlled by word line 31'C''.

The structure of a conventional general dynamic memory hill is shown in FIG. 2(d). Field oxide film 5 on silicon substrate 1
And a first gate oxide film 7 is formed. This first
A capacitor is formed by the n+ diffusion layer 6 formed with the gate oxide film 7 sandwiched therebetween and the first silicon layer 8, and charges are accumulated therein.

On the other hand, the first gate oxide film 9, the second polysilicon layer 10,
A transistor is formed by the n+ source/drain regions 11 and '12, and charges are read out. A CVDI silicon layer 13 is formed on these, and an aluminum silicon layer is further formed on it. The aluminum silicon layer 14 is connected to the n+ source/drain region 12 via a contact hole, and charges are read out.

Such dynamic memory cells are manufactured in a conventional manner. First, as shown in FIG. 2(a), a thin oxide film 2 is formed on a silicon substrate 1 by heat treatment,
A silicon nitride layer 3 is deposited on top of this. Next, a resist layer 4 is formed on this, and then patterned by photolithography, and the silicon nitride layer 3 is etched using the patterned resist layer 4 as a mask. FIG. 2(a) shows this state.

Next, after removing the resist layer 4, a heat treatment is performed using the silicon nitride layer 3 as a mask to selectively oxidize and form a field oxide film 5. FIG. 2(b) shows this state.

Subsequently, the silicon nitride layer 3 is removed by dry etching or the like, and the oxide film 2 is further removed with NH4F, leaving only the field oxide film 5. FIG. 2(C) shows this state.

Subsequently, a first gate oxide film 7 is formed by heat treatment,
Arsenic or the like is implanted to form an n+ diffusion layer 6, and then a first polysilicon layer 8 is formed. Next, CVDM is performed using the CVD method.
Chemical silicon Fr? After depositing J13 and opening only the switching transistor region, a thin second gate oxide film 9 and a second polysilicon layer 10 are formed by heat treatment. By implanting arsenic into the bond, the n+ source/drain region [11,1
2 to form a switching transistor.

Finally, after depositing the CVD silicon oxide 2 layer 13 again and opening a contact hole, the aluminum silicon layer 1
4 forms a bit line. Through such a procedure, a dynamic memory cell as shown in FIG. 2(d) is constructed.

[Problems with background technology]

In recent years, there has been a desire for higher integration of memory elements, but it is considered impossible to construct a dynamic RAM of 4 Mbits or more using the above-mentioned planar type memory cells. For example, the capacitance C of a cell capacitor is expressed as ε C=−S where d is the thickness of the insulating film, ε is the dielectric constant, and S is the cell area. Here, if the value of d is made small, a constant capacitance C can be secured even if the cell area S is made small, but if the oxide film thickness is reduced to less than 1008, a problem will arise in terms of reliability.

There is a proposal to increase the proportion of the cell area by reducing the area of the field oxide film, but the patterning accuracy by light exposure of the silicon nitride used to form the field oxide film is 1.0.
There is a limit of about μ7n, and the bird's beak produced by selective oxidation is unavoidably about 1.0 μm, which is a big problem.

In recent years, following the idea of three-dimensionally securing capacitor cells, trench-type memory cells have been proposed in which trenches are dug in a semiconductor substrate. This is a method in which a silicon substrate is vertically etched to form a trench, silicon oxide is buried in the trench by CVD, and an element isolation region made of CVD silicon oxide is formed at the bottom of the trench. however,
This method has the disadvantage that it is difficult to form CVDIm silicon in the semiconductor layer, and that the CVD silicon oxide film is inferior to a thermal oxide film as an element isolation insulating film.

(Objective of the Invention) Therefore, an object of the present invention is to provide a dynamic memory cell which can achieve higher density and which uses a reliable insulating film for element isolation, and a method for manufacturing the same.

[Summary of the invention]

The feature of the present invention is that the dynamic memory cell includes:
A semiconductor substrate having a groove, a cell capacitor formed on the side surface of the groove, an insulating film for element isolation formed on the bottom of the groove by thermal oxidation, and a means for reading out charges from the cell capacitor are provided to ensure reliable operation. It is possible to separate elements and achieve high density.

Another feature of the present invention is that in order to manufacture the dynamic memory cell, a first mask layer is formed on the semiconductor substrate, a groove is dug in the semiconductor substrate through the first mask layer, and a trench is formed in the semiconductor substrate. The side surfaces of the groove are further dug to retreat the side surfaces, a second mask layer is formed on at least the side and bottom surfaces of the groove, and the second mask layer on the side surface of the groove is etched by anisotropic etching using the first mask layer as a mask. The second mask layer at the bottom is removed leaving the mask layer, and the bottom of the trench is thermally oxidized using the second mask layer remaining at the side as a mask to form an element isolation insulating film, and the first and second The main feature is that the mask layer is removed, and a cell pattern passita is formed on the side surface of the groove.

[Embodiments of the invention]

The present invention will be described below based on illustrated embodiments. 1st
Figure (f) shows the structure of an embodiment of a dynamic memory cell according to the present invention. A groove is placed on the silicon substrate 15,
A first gate oxide film 22 is formed on the side surfaces of this trench, and a field oxide film 20 is formed on the bottom surface. First gate oxide film 2
A first polysilicon FVJ 23 and an n-type diffusion layer 21 are formed on both sides of the capacitor 2, forming a capacitor. on the other hand,
Second gate oxide film 24, second polysilicon layer 25, n4
A transistor is formed by the source/drain regions [26, 27, and charges are read out.

CVDW on top of these! A silicon i-oxide layer 28 is formed, and an aluminum silicon layer 29 is further formed thereon. The aluminum silicon layer 29 is connected to the n+ source/drain region 27 via a contact hole, and charges are read out.

By forming the memory cell in a trench type structure in this manner, a sufficient cell capacitor area can be secured within a small region. Moreover, since the field oxide film 20 for element isolation is formed at the bottom of the trench, the area can be saved accordingly, and since the field oxide film 20 is formed by thermal oxidation, the CV
It is superior in terms of leakage, etc. compared to D silicon oxide crotches, and enables reliable element isolation.

Next, an embodiment of the method for manufacturing this memory cell will be described with reference to FIG. First, an oxide film 1 is placed on a silicon substrate 15.
6 is formed to a thickness of 900 nm, and a silicon nitride layer 17 is formed thereon to a thickness of 2000 nm. Furthermore, CV on top of this
A CVD silicon oxide film 18 is deposited to a thickness of 8000 mm using the D method. Subsequently, resist (
After removing a part of the CVDMlff1 silicon film 18 by etching using a mask (not shown) and peeling off the resist, the silicon nitride layer 17, oxide film 16, and silicon substrate 15 are etched vertically using the CVDM silicon crotch 18 as a mask. A groove with a depth of about 4 μm is formed by etching. Subsequently, the inside of the groove is etched using an etching method that is selective to the CVDtI silicon film 18, and the side surfaces of the groove are retreated. FIG. 1(a) shows this state. The shape is such that a rim is formed in the groove portion by the CVOS silicon film 18. This area has a thickness of about 0.7μ.

Next, by heat treatment, an oxide film 16 is formed on the inner surface of the groove to a thickness of 900 mm.
A silicon nitride layer 19 is further formed on the silicon nitride layer 19.
Deposit about 0008. FIG. 1(b) shows this state.

After that, the entire surface is etched by RIE.

Since RIE has anisotropy, it is possible to perform etching that removes the silicon nitride layer 19 on the surface and bottom of the trench, leaving the silicon nitride layer 19 on the side surfaces of the trench. Subsequently, after removing the CVDM silicon film 18 with N84F, thermal oxidation is performed to form the field oxide film 20 to a
Form to a thickness of 0 people. FIG. 1(C) shows this state.

Subsequently, by removing the silicon nitride layers 17 and 19 and the oxide film 16, field oxidation 11! is formed on the bottom of the trench, as shown in FIG. 1(d). Only J20 can remain.

Next, after forming an n+ diffusion layer 21 by a method such as a drive-in method, a first gate oxide film 22 is formed with a thickness of about 1,508 mm by heat treatment. Furthermore, a first polysilicon layer 23 is formed on this layer to a thickness of about 4000 mm, patterned using microfabrication technology, and separated at the bottom of )1/I. Figure 1(e)
shows this state.

Next, a CVDI silicon layer 28 is deposited by the CVD method, a hole is opened only in the switching transistor region, and a second gate oxide film 24 with a thickness of about 250 layers is formed by heat treatment. silicon layer 25 to 4000
It is formed to a thickness of about 0.00 cm, buttered using photo-etching technique,
Create a word line. Thereafter, by implanting arsenic to form n+ source/drain regions 26 and 27, a switching transistor can be constructed. Then, by CVD method, C
After depositing the VD silicon oxide 2 layer 28 again, contact holes are opened and bit lines are formed using the aluminum silicon layer 29.

In the above embodiment, a trench type memory cell has been described, but if the trench is made shallow so that only the field oxide film 20 is buried in the semiconductor substrate 15, a Brenna type memory cell can be obtained. The present invention can also be applied to.

〔Effect of the invention〕

As described above, according to the present invention, in a dynamic memory cell, a groove is provided in a semiconductor substrate, an insulating film for element isolation obtained by thermal oxidation is formed on the bottom surface of the groove, and a capacitor cell is formed on the side surface of the groove. As a result, reliable element isolation can be achieved, and high density can be achieved.

[Brief explanation of drawings]

FIG. 1 is a process diagram showing a method for manufacturing a dynamic memory cell according to the present invention, FIG. 2 is a process diagram showing a conventional method for manufacturing a dynamic memory cell, and FIG. 3 is an equivalent circuit of a general dynamic memory cell. It is. DESCRIPTION OF SYMBOLS 1...Silicon substrate, 2...Oxide film, 3...Silicon nitride layer, 4...Resist layer, 5...Field oxide film, 6...N+ diffusion layer, 7... First gate oxide film, 8... First polysilicon layer, 9... Second gate oxide film, 10... Second polysilicon layer, 11.12
...n+ source/drain region, 13...CVDI
II silicon layer, 14... aluminum silicon layer, 15... silicon substrate, 16... oxide film, 17
... silicon nitride layer, 18 ... CVDM silicon film, 19 ... silicon nitride layer, 20 ... field oxide film, 21 ... n+ diffusion layer, 22 ... first gate oxide film, 23... First polysilicon layer, 24... Second gate oxide film, 25... Second polysilicon layer, 26
．． 27...n+ source/drain region, 28...C
VDIa silicon layer, 29... aluminum silicon layer, 30... bit line, 31... word line, 3
2... Switching transistor, 33... Capacitor. Figure 1

Claims (1)

[Claims] 1. A semiconductor substrate having a groove, a cell capacitor formed on the side surface of the groove, an insulating film for element isolation formed on the bottom of the groove by thermal oxidation, and a semiconductor substrate formed from the cell capacitor. A dynamic memory cell comprising: means for reading charges. 2. The dynamic memory cell according to claim 1, wherein the semiconductor substrate is a silicon substrate. 3. The cell capacitor according to claim 1 or 2, characterized in that the cell capacitor is composed of an oxide film, a polysilicon layer formed across the oxide film, and a conductive pattern in the semiconductor substrate. Dynamic memory cell. 4. Form a first mask layer on the semiconductor substrate, and
digging a groove in the semiconductor substrate through the mask layer, further digging the side surfaces of the groove in the semiconductor substrate to retract the side surfaces, forming a second mask layer on at least the side and bottom surfaces of the groove; By anisotropic etching using the mask layer as a mask, the second mask layer on the side surfaces of the groove is left and the second mask layer on the bottom surface is removed, and the second mask layer remaining on the side surfaces is removed.
The bottom surface of the trench is thermally oxidized using the mask layer as a mask to form an element isolation insulating film, the first and second mask layers are removed, and a cell capacitor is formed on the side surface of the trench. A method for manufacturing a dynamic memory cell. 5. The method of manufacturing a dynamic memory cell according to claim 4, wherein the semiconductor substrate is a silicon substrate. 6. Claim 4, wherein the first mask layer is a silicon oxide film deposited by a CVD method.
6. A method for manufacturing a dynamic memory cell according to item 5. 7. The dynamic device according to any one of claims 4 to 6, characterized in that an etching method selective to the first mask layer is used to retreat the side surfaces of the groove. A method for manufacturing memory cells. 8. The method for manufacturing a dynamic memory cell according to any one of claims 4 to 7, wherein the second mask layer is a silicon nitride layer.