JPS6358863A - Manufacture of semiconductor storage device - Google Patents

Abstract

PURPOSE:To enhance integration and improve reliability by a method wherein a capacitor electrode is embedded in an element isolating groove in a substrate and isotropic etching is accomplished against the groove ridges for the formation of recesses wherein gate electrodes are embedded. CONSTITUTION:A lattice-geometry element isolating groove 3 is formed in a substrate 1 by using a mask 2. In the groove 3, a capacitor electrode 5 is embedded through the intermediary of an element isolating/insulating film 4. An oxide film 7 is formed on the surface of the capacitor electrode 5, and the ridges of the substrate 1 facing the groove 3 containing the capacitor electrode 5 are allowed to expose themselves, and the ridges are scraped off in an isotropic etching process with the oxide film 7 and mask 2 serving as a mask for the formation of recesses 6. In the recesses 6, by self-alignment, gate electrodes 8 to be word lines are embeded. The gate electrodes 8 serve as a mask in a process of implanting the substrate 1 with an impurity for the formation of an N-type layer 9 to be a drain region. The entire surface is covered by an CVD insulating film, and then a wiring 10 built is to be a bit line. This design enables a large capacitor to realize to occupy but a small area, which in turn realizes a high-reliability enhanced integration of MOS transistors.

Description

Detailed Description of the Invention [Objective of the Invention] (Industrial Application Field) The present invention relates to a MOS type semiconductor memory device <dRA~1 in which a memory cell is configured by - capacitors and one HIOS transistor. ) regarding.

(Conventional technology) In recent years, advances in semiconductor technology, particularly in microfabrication technology (i), have led to rapid increases in the integration of dRAMs. Therefore, the amount of charge stored in the ~108 capacitor decreases.As a result, the memory contents may be read out incorrectly, or the memory contents may be destroyed by radiation such as alpha rays.
Problems such as these are occurring. To solve this problem, various methods have been proposed to substantially increase the capacitor area without increasing the occupied area of the substrate by digging a groove in the semiconductor substrate and using the sidewalls of the groove as the capacitor area. There is.

FIG. 10 shows the structure of such a conventional dRAM (Japanese Unexamined Patent Publication No. 72161/1982). 31 is a p-type 3i substrate, on which a lattice-shaped groove 32 is formed;
A capacitor electrode 34 is embedded in the side wall of the capacitor through a capacitor insulating film 33, and a capacitor is formed around the island region surrounded by the groove. A p+ type layer 35 for element isolation is formed at the bottom of the groove 32. The MOS transistor is constructed by forming a gate electrode 37 on a flat surface of the substrate in a region surrounded by a groove 32 with a gate insulating film 36 interposed therebetween. 38 is the drain region n11.39 is 5iO
21[1F is present, and 40 is a wiring that becomes a bit line.

In this dRA~1 configuration, by effectively utilizing the sidewalls of the element isolation trenches, a large capacitance capacitor can be easily installed in a small occupied area. However, in this configuration, the MOS transistor still uses the flat surface of the substrate,
Not miniaturized. Further, in this configuration, the gate electrode 3
7 is patterned so as to overlap with the capacitor electrode 34, thereby omitting the source region.

In this case, if there is a misalignment in mask alignment during gate electrode formation, if the gate length of a certain MOS transistor section becomes longer, the gate length of the adjacent MOS transistor will become shorter. As a result, the variation in gate length within the memory cell region becomes extremely large.Furthermore, the capacitor is formed from the sidewall of the trench formed in the substrate to the top surface.In this configuration, the top corner of the trench Therefore, if the capacitor insulating film is made thinner to obtain a large capacity capacitor, the reliability of the capacitor decreases because the oxide film tends to become thinner and the electric field tends to concentrate.

(Problems to be solved by the invention) As described above, in the conventionally proposed dRAM, the M
No attempt has been made to reduce the area of the oS transistor region, and there are large variations in gate length, so higher integration and higher reliability of the -layer are desired.

An object of the present invention is to provide a method for manufacturing d RA N=+ that satisfies such requirements.

[Structure of the Invention] (Means for Solving Problems) The main steps of the dRAM manufacturing method according to the present invention will be explained with reference to FIGS. 1(a) to 1(d).

First, lattice-shaped element isolation grooves 3 are formed in a semiconductor substrate 1 using a mask 2 (a). Next, along the groove 3 in one direction, the element isolation isolation It! The capacitor electrode 5 is embedded through the capacitor electrode 14 (b). After that, an oxide film 7 is formed on the surface of the capacitor mold 5, and the ridgeline portion of the substrate that is in contact with the element isolation groove in which the capacitor electrode 5 is buried is exposed, and this ridgeline portion is oxidized! Using the mask 17 and the mask 2 as a mask, etching is performed by an isotropic etching method to form a concave portion 6 having a curved surface (C). Then, a gate electrode 8 that will become a word line is embedded in this recess in a self-aligned manner, and then impurities are introduced into the substrate using the gate electrode 8 as a mask to form an n-type layer 9 that will become a drain region. A wiring 10 that is covered with an insulating film and becomes a bit line in contact with the train region is formed (d).

(Function) According to the present invention, not only can a large capacitor capacity be obtained with a small occupied area by effectively utilizing the side walls of the element isolation groove, but also the ridgeline of the substrate in contact with the region where the capacitor electrode is embedded can be By cutting off a portion and embedding a gate electrode there, the MOS transistor region can also be formed in a sufficiently small area. Moreover, since the gate electrode can be formed in a self-aligned manner in a rounded concave portion by cutting off the edge of the substrate using a technique that leaves the sidewalls intact, there is no variation in gate length, and MOS transistors with small gate lengths can be formed. can be integrated reliably. Capacitors do not use the upper part of the groove, where the oxide film tends to become thinner and the electric field tends to concentrate.
In this respect as well, reliability is high.

(Actual travel example) The present invention will be explained in detail below.

FIG. 2 to FIG. 9 are diagrams for explaining the manufacturing process of dRA-1 of one embodiment. In each of these figures, (a> is a plan view, (b), (c), and (d) are respectively (a)
FIG. First, a p-type Si substrate 11 is prepared, and on its surface, an insulating film, that is, an oxide film 12 of several hundreds of layers by thermal oxidation, an Si3N41113 of several thousand amps, and a silicon oxide MM 14 of silicon oxide by CVD are formed on the surface of the substrate. form. A photoresist 151 is patterned into a plurality of islands on these laminated insulating films (FIG. 1). Using this photoresist 151 as a mask, the substrate 11 above and below the laminated insulating film is etched by reactive ion etching (RIE).

Element isolation grooves 16 are formed in a Y grid pattern. In this element isolation groove 16, a p1 type layer 17 for preventing inversion is formed by ion implantation, and then oxidized mis is formed by CVD as an element isolation insulating film to fill it so that the surface is flat (Fig. 3). .

Next, the element isolation region and the element region except for the groove region running in the Y direction for forming the capacitor are masked with a photoresist 152 patterned in a stripe shape, and the oxide film 18 is etched to remove the oxide film 18 in the Y direction. At the bottom of the trench 16, only the thickness necessary for element isolation is left, and the trench sidewall of the capacitor formation region is formed.

Expose (Figure 4). After this, PSG I! Alternatively, As5GIIA (not shown) is formed on the entire surface and solid phase diffusion is performed to form one n-type layer on the side wall of the groove 16.
After removing PSGI or As S G nQ and forming a capacitor insulating film 20 by, for example, thermal oxidation on the side wall of the trench 16, a capacitor electrode 21 made of a phosphorus-doped first layer multi-crystalline silicon film is buried in this 71116. Figure 5). The capacitor electrode 21 is formed continuously along the Y direction within the X and Y grooves 16.

After this, photoresist 1 used in the previous oxide film etching
A photoresist 15 with approximately the same stripe pattern as 52 and slightly narrower in width is formed, and an oxide film 18 is formed as an element isolation insulating film in contact with the side surface of the capacitor electrode 21.
A step portion 22 is formed by etching the culm by 0.5 μm (FIG. 6).

This is to ensure that the gate electrode, which will be formed later by the sidewall leaving technique, is disposed continuously in the Y direction.

After this, oxide 1124 is formed on the capacitor electrode 21 by low-temperature oxidation, and then T chemical etching is performed to selectively expose the Si substrate region adjacent to the upper end of the capacitor electrode 21, and the Si3N+ 1113 and the capacitor electrode 121 are etched. Using the upper oxide film 24 as a mask, the Si substrate region is etched. At this time, an isotropic etching method such as CD
By using the E method, the ridgeline portion of the substrate adjacent to the capacitor electrode 1fA21 is shaved off with a curved surface, and the recessed portion 2
3 is formed (Figure 7).

Next, the Si3N+1113 used as a mask and the oxide film 12 below it are removed, thermal oxidation is performed to form a gate insulating film 25 in the recess 23, and then a phosphorus-doped second layer polycrystalline silicon film is deposited. The gate electrode 26 is formed by etching the entire surface by RIE and selectively leaving it on the side wall of the recess 23 and the step portion 22 continuous therewith. Then, using the gate electrode 26 as a mask, P or AS
Ion implantation is performed to form an n-type layer 27 that will become a drain region (FIG. 8). As is clear from the figure, the gate electrode 26 is disposed continuously in the same direction as the capacitor electrode 21 and self-aligned with the capacitor electrode 21, and this forms a word square.

Finally, a silicon oxide film 28 is deposited on the entire surface by CVD, a contact hole 29 is opened in this, and a gate electrode 26 is formed.
An AR wiring 30 is formed which commonly connects each n-type layer 27 in the X direction perpendicular to (FIG. 9).

This A2 wiring 30 becomes a bit line.

In this way, according to this embodiment, the capacitor electrode t1 is buried in the element isolation trench, and the ridgeline portion of the substrate region in contact with the capacitor electrode is etched to form a concave portion, in which the gate electrode (quantity) is placed in a self-aligned manner. Therefore, the area of the MOS transistor region is extremely small.Furthermore, the gate electrode is formed using a technique that leaves the sidewalls intact without using a mask alignment process, making it possible to form a MOS transistor with a small gate length. are formed without any variation.

Furthermore, since the region where the gate electrode is embedded is formed into a rounded shape by isotropic etching, even if the gate length is short in plan view, the effective channel length is longer than that. The short channel effect is effectively prevented. Furthermore, the capacitor is formed so as to cover a part of the corner of the groove having vertical sidewalls.Unlike the conventional example shown in FIG. 10, it faces only the sidewall of the groove, which reduces reliability. As described above, according to this embodiment, a part of the dRAM can be highly integrated and its reliability can be improved.

The present invention is not limited to the embodiments described above. For example, in the embodiment, the capacitor electrode and the gate electrode were formed using a two-layer polycrystalline silicon film, but it is possible to replace all or part of these with other materials such as high melting point gold nail or its silicide. In addition, in this embodiment, element isolation grooves in both the X and Y directions are formed on the substrate at the same time, and the element isolation insulating film is completely buried in the grooves, and then the insulating film in the element isolation groove in one direction is removed halfway. By etching, a region for embedding the capacitor was provided.

On the other hand, first, an element isolation groove in the X direction is formed by etching, and after the element isolation insulating film is completely buried therein,
An element isolation structure similar to that of the embodiment can be obtained by etching an element isolation groove in the Y direction and burying an element isolation insulating film partway therein. The present invention is also effective when such a process is employed.

In addition, the present invention can be modified in various ways without departing from its spirit.

[Effects of the Invention] As described above, according to the present invention, a capacitor electrode is embedded in an element isolation groove, and a concave portion is formed by etching the ridgeline of the element isolation groove by isotropic etching. By embedding the gate electrode in the gate electrode, it is possible to reduce the area of the MOS transistor region without causing variations in characteristics, and it is possible to achieve higher integration and reliability of the dRAM.

[Brief explanation of the drawing]

FIGS. 1(a) to (d) are diagrams for explaining the outline of the dRA＼1 Rakuzo Kumat of the present invention, and FIGS. 2(a), (b), and (C) (
d) to FIG. 9(a), (b), (C), and (d) are diagrams for explaining the manufacturing process of dRAM according to an embodiment of the present invention,
FIG. 10 is a diagram showing the structure of the conventionally proposed dRA~1. DESCRIPTION OF SYMBOLS 1... Semiconductor substrate, 2... Mask material, 3... Element isolation trench, 4... Element isolation insulating film, 5... Capacitor electrode, 6... Concave portion, 7... Melting Film, 8... Gate electrode (word gland), 9... N-type layer, 10... Wiring (bit line), 11... P-type 3i substrate, 12... Oxide film, 13...・Si3N4 film, 14... Oxide film, 1
51 to 153... Photoresist, 16... Element isolation trench, 17... P'' type 1.18... Oxide film (element isolation insulating film), 19... N- type resist, 20... Capacitor insulating film, 21... Capacitor electrode, 22...
Stepped portion, 23... Concave portion, 24... Tempered membrane, 25...
・Gate insulating film, 2G...gate electrode, 27...n
Mold layer, 28...Oxide film, 2...Contact holes, 30...2 wirings (bit; 1). Applicant's Representative Patent Attorney Takehiko Suzue Figure 1 (1) Figure 1 (2) Figure 2 (2) Figure 3 (2) Figure 4 (2) Figure 5 ( 2) Figure 6 (2) of - Figure 7 (2) Figure 8 (2) of -

Claims (1)

[Claims] a step of forming an element isolation trench in a semiconductor substrate; a step of embedding a capacitor electrode by providing an element isolation insulating film at the bottom of the unidirectional element isolation trench and a capacitor insulating film on the side wall of the trench; A step in which the ridgeline of the substrate in contact with the element isolation groove in which the capacitor electrode is embedded is removed using an isotropic etching method to form a concave portion with a curved surface, and a word line is formed by passing a gate insulating film into the formed concave portion. The method includes a step of embedding a gate electrode, a step of introducing impurities into a substrate using the gate electrode as a mask to form a drain layer, and a step of forming a wiring to be a bit line in contact with the drain layer. A method for manufacturing a semiconductor memory device, characterized by: