JPH0382156A - Semiconductor memory cell and manufacture thereof - Google Patents

Abstract

PURPOSE:To obtain a micro-semiconductor memory cell adapted for high integration by a method wherein a folded bit line type memory cell is provided, where a laminated capacitive section is formed on the side walls of two gate electrodes and a protrudent insulating film provided onto the gate electrodes which run through the memory cell. CONSTITUTION:A laminated type capacitive section is composed of a first and a second storage electrode, 3 and 4, connected a first diffusion layer 2 of a silicon substrate 1 and an opposed electrode 6 formed through the intermediary of a capacitor insulating film 5. The laminated type capacitive section is formed on the protrudent side wall of an insulating film 11 formed on two gate electrodes 7 which pass through a memory region and the side wall of the gate electrodes 7. A first gate electrode 7 of a switching transistor connected to a word line controls the transfer of charges between a second diffusion layer 9 connected to a bit line 8 and the first and the second storage electrode, 3 and 4. A second gate electrode 10 serves as the gate electrode of the switching transistor of an adjacent memory cell.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a semiconductor memory including a capacitor section and an insulated gate field effect transistor, and a method for manufacturing the same.

[Prior Art] Semiconductor memory cells that store binary information in the form of charges have a small cell area, so they are highly integrated, have a large capacity, and are excellent as memory cells. In particular, a memory cell (hereinafter abbreviated as an ITIC cell) consisting of one transistor and one capacitor is important as a memory cell for highly integrated memory because it has few constituent elements and has a small cell area. Incidentally, as the memory cell size is reduced due to higher integration of memories, the area of the capacitor part in the ITIC: cell structure has been reduced.

A decrease in the amount of storage charge due to a decrease in the area of the capacitor section causes problems with resistance to alpha particles and deterioration of the sensitivity of the sense amplifier.

Conventionally, in order to solve these problems, a method has been known in which a large storage capacity section is formed despite the reduction in memory cell area. For example, the International Solid State Devices Conference (Int.
ernational Electron Device
esMeeting) 1978, 348-351
rNovel High Density on the page, 5
In a paper published under the title tacked capacitor MOSRAMJ, as shown in FIG.
A structure formed by 52 is shown. - The polycrystalline silicon 51 of the second layer is electrically connected to the source side of the switching transistor, and the polycrystalline silicon 52 of the second layer is kept at a constant potential as a counter electrode to the polycrystalline silicon 51 of the first layer. . The amount of charge stored in this memory cell is determined by the two-layer polycrystalline silicon 51.
It depends on the size of the capacitance formed between 52 and 52. Therefore, in order to maximize the storage capacity of a memory cell with this structure, the polycrystalline silicon is designed to be large enough to cover most of the area on the memory cell.

In FIG. 3, reference numeral 53 indicates a bit line, 54 a diffusion layer connected to the bit line, 55 a gate electrode of a switching transistor, and 56 an insulating film.

[Problems to be Solved by the Invention] However, in such a structure, there is a problem in that as the memory becomes highly integrated, the memory cell area is reduced and the storage capacity is gradually reduced.

In addition, in order to secure the accumulated charge necessary for reading, −
If the thickness of the layer polycrystalline silicon 51 is increased to increase the side wall area, there is a problem that the unevenness of the element surface becomes larger and the manufacturing process such as processing of the -th layer polycrystalline silicon 51 becomes extremely difficult. .

An object of the present invention is to eliminate such conventional drawbacks and provide a fine semiconductor memory cell suitable for high integration and a method for manufacturing the same.

[Means for Solving the Problems] In order to achieve the above object, the semiconductor memory cell according to the present invention is a folded bit line type memory cell, in which a convex shape is provided on two gate electrodes passing through one memory cell region. A stacked capacitor portion is formed on the sidewall of the insulating film and the sidewall of the gate electrode.

Further, the method for manufacturing a semiconductor memory cell according to the present invention includes forming an element isolation region and a gate insulating film on a semiconductor substrate.

After each gate electrode is formed, a step of forming a convex portion of a convex insulating film on the gate electrode, a step of opening a contact hole between the gate electrodes passing through one memory cell region,
a step of covering at least a side wall of the convex insulating film with a charge storage electrode; a step of covering at least the charge storage electrode with a capacitive insulating film; and a step of covering at least the charge storage electrode via the capacitive insulating film. The method includes a step of forming a counter electrode.

〔Example〕

Hereinafter, typical embodiments of the present invention will be described in detail with reference to the drawings.

FIG. 1 is a schematic cross-sectional view of a memory cell formed according to the present invention, and FIGS. 2(a), (b), (C), (
6).

(e), ■, (2), and (11) are schematic cross-sectional views sequentially showing the manufacturing process in the present invention.

In FIG. 1, a stacked capacitor section of a semiconductor memory cell according to the present invention is formed by first and second storage electrodes 3 and 4 connected to a first diffusion layer 2 of a silicon substrate l and a capacitor insulating film 5. The stacked capacitor section includes two gate electrodes 7 passing through one memory cell region.
It is formed on the side wall of the convex portion of the insulating film 11 provided above and the side wall of the gate electrode 7. 7 is a first gate electrode of a switching transistor connected to a word line, which is connected to a second diffusion layer 9 connected to a bit line 8;
Controls the movement of charges between the second storage electrodes 3 and 4. The second gate electrode 10 indicates the gate electrode of a switching transistor of an adjacent memory cell.

Next, a method for manufacturing the semiconductor memory cell of the present invention shown in FIG. 1 will be explained based on FIG. 2.

First, as shown in FIG. 2(a), a p-type silicon substrate 2
After forming an insulating film 22 in the element isolation region above 1 and further forming a gate insulating film 23 on the element region, low resistance polycrystalline silicon and a thick insulating film are successively deposited using the CVD method. After patterning the resist 24 having the shape of a gate electrode, the insulating film and polycrystalline silicon are sequentially etched away using the resist 24 as a mask to form an insulating film 25 and polycrystalline silicon 26 having the shape of the gate electrode.

Next, as shown in FIG. 2(B), the resist 24 is removed, and the resist applied to the entire surface of the wafer is etched using reactive ion etching technology (hereinafter abbreviated as RIE) until the surface of the insulating film 25 is exposed. After backing up and leaving a resist 27 between the gate electrodes, a resist 28 is patterned so as to cover at least the capacitor forming portion, and then the insulating film 28 is patterned using the RIE technique using the resist as a mask.
Etch 5.

Note that FIG. 2(C) is a cross-sectional view taken along the line AA′ of FIG. 2(6).

Next, as shown in FIG. 2(d), the resist 27°2
8, a low concentration n-type impurity such as phosphorus or arsenic is implanted into the silicon substrate 21 using an ion implantation method to form a low concentration impurity layer (diffusion layer) 29.
An insulating film 30 is deposited using a VD method, and a high concentration n-type impurity is implanted into the silicon substrate 21 using an ion implantation method to form a high concentration impurity layer (diffusion layer) 31.

Next, as shown in FIG. 2(e), the resist 32 is buttered so as to open only between the two gate electrodes passing through one memory cell region, and RIE technology is used with the resist 32 as a mask. Then, the insulating film 30 and the gate insulating film 23 are removed by etching in sequence.

Next, as shown in FIG. 2, low-resistance polycrystalline silicon 33 is deposited over the entire surface using the CVD method.

Next, as shown in FIG. 2Q, the polycrystalline silicon 33 is etched using the RIE technique, leaving the polycrystalline silicon 33' on the sidewalls of the insulating film 25, and then CVD or thermal oxidation is performed. A thin insulating film 34 is formed using CVD.
A low resistance polycrystalline silicon 35 is deposited using a method.

Next, as shown in FIG. 2(f), after depositing an insulating film 36 by the CVD method, a low-resistance polycrystalline silicon 37 is formed to at least fill the contact hole connecting the bit line and the drain region of the switching transistor. , and further C
An insulating film 38 is deposited by the VD method, and then a bit line 39 is formed.
and the polycrystalline silicon 37 are connected through contact holes to complete the semiconductor memory cell shown in FIG.

[Effects of the Invention] According to the present invention, the charge storage electrode formation region is extended not only to the sidewalls of the insulating film provided on the gate electrode but also to the sidewalls of the gate electrode, making full use of the surface steps. Even in a small memory cell area, the thickness of the charge storage electrode can be formed thinner than in the conventional structure, and a sufficient amount of stored charge can be ensured. The manufacturing process is facilitated by alleviating such surface steps.

As described above, according to the present invention, it is possible to easily obtain a memory cell suitable for high integration and a method for manufacturing the same.

[Brief explanation of drawings]

FIG. 1 is a schematic cross-sectional view of a memory cell formed by the method of the present invention, FIGS. 1 is a schematic cross-sectional view of a conventionally known ITIC cell. 1.21...Silicon substrate

Claims (2)

[Claims] (1) In a folded bit line type memory cell, a stacked capacitor portion is formed on the sidewalls of a convex insulating film provided on two gate electrodes passing through one memory cell region and on the sidewalls of the gate electrodes. semiconductor memory cell. (2) After forming an element isolation region, a gate insulating film, and a gate electrode on a semiconductor substrate, a process of forming a convex part of a convex insulating film on the gate electrode, and a gap between the gate electrodes passing through one memory cell area. a step of opening a contact hole in the convex insulating film, a step of covering at least the side wall of the convex insulating film with a charge storage electrode, a step of covering at least the charge storage electrode with a capacitive insulating film, and a step of covering at least the side wall of the convex insulating film with a capacitive insulating film; A method for manufacturing a semiconductor memory cell, comprising the step of forming a counter electrode so as to cover the charge storage electrode.