JPS58139461A - Semiconductor memory cell - Google Patents

Abstract

PURPOSE:To obtain a high density dynamic RAM by forming an MOSFET through an insulating layer on an Si substrate, extending a source to a thin insulating film region, superposing the insulating film and forming memory cells above and below the source extension. CONSTITUTION:Ions are implanted to a thin SiO2 film 106 of an n<-> type Si substrate 103 to form an n<+> type layer 108, a polysilicon layer 210 is superposed, a hole is selectively opened, and a thin SiO2 film 209 is covered. Ions are further implanted to form an n<+> type layer 211, and the layer 210 is removed. Subsequently, n<+> type polysilicon layers 215, 216 are selectively formed, an SiO2 film is covered, a mask 302 is formed, a hole 303 is opened, the mask 302 is then removed, and A electrodes 307 are attached. According to this configuration, the memory capacity becomes twice that of the conventional one. Further, alpha- ray is passed through the extended source region 218 to produce electron-hole pairs, but the barrier 106 prevents the pairs produced in the substrate from moving to a depletion layer, the pairs are recombined before moving to the drain 217, thereby preventing erroneous reading.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to the structure of a built-in semiconductor device (MOS) transistor, in particular a random access memory cell.

In VLSI circuits, dynamic random
It is necessary to create an access memory (dRAM). Traditionally, several methods have been used to make dRAM cells more densely packed. For example, IEEE) Ranzak John-on-Electronic Devices, 1
June 979, Vol, ED-26, N006
Nos. 827 to 839 of the above are stated.

As shown in Table 1 of this document, these prior art d FRAM cell structures have more or less all or some of the following disadvantages.

The L cell is large and prevents high-density integration.

2. The storage capacity per unit area of the transistor dRAM is small.

3. Leakage in cell storage capacity is large.

4 Bit-line capacitance is large, reducing high-speed operation of dRAM.

a Sensitivity to alpha particles increases leakage in the capacity.

dRAM cells according to embodiments of the present invention minimize, if not eliminate, the drawbacks of conventional dJIRAM cells discussed above. By creating a cell with an oxide barrier, the susceptibility to K and C1α particles is greatly reduced. Furthermore, the formation of a cell storage container reduces this susceptibility. Also, the structure according to the invention exhibits much less bit-line capacity than the prior art '=*RAM. In general, the bit line capacitance is reduced by creating an in-cell KMO register. MOS transistors are also made to form the plates for cell storage capacitors. This K increases the capacitance value of the cell. For example, the capacitance value can be doubled compared to the conventional technology without increasing the size of the cell. In summary, the present invention provides high-density integration d
BRIEF DESCRIPTION OF THE DRAWINGS A new structure for a RAM cell is provided, which eliminates many of the disadvantages of cells according to the prior art.

FIG. 9A is a cross-sectional view of a semiconductor memory cell according to an embodiment of the present invention, FIGS. 1 to 8 are diagrams showing manufacturing steps of the semiconductor memory cell of FIG. 9A, and FIG. 9B is a cross-sectional view of a semiconductor memory cell according to another embodiment of the present invention. FIG. 2 is a cross-sectional view of a semiconductor memory cell. Figure 10A is 9A
FIG. 9B is an electrical equivalent circuit diagram of the semiconductor memory cell of FIG. 9 and FIG. 9B. 103 is, for example, a lightly doped n'' type silicon substrate. A thin stress-relieved oxide layer (SRO) 104 is deposited on the substrate 103 and then K Si
n N4 layer 1 (11) is formed. A first mask 102 defining a capacitive region 105 to be finally formed is
5isNn formed on the Na layer 101 (FIG. 1)
Layer 101 is eroded away, leaving only capacitive region 105 behind. Next, a thick oxide layer 107, e.g. 6.00 OA, is grown on the substrate not covered by the 5iaNa layer 105K. Next, the remaining S
The isNa layer 105 is removed along with the 5RO 104, and a thin oxide layer 106 is grown in its place. Ion implantation is then performed through this new oxide layer 106 to form a layer 108 of heavily doped n-type material, or n+, in the n- substrate (FIG. 2).

It is then laser annealed to create a polycrystalline silicon layer or polysilico grains. but,
Other processes for forming a large grain polysilicon layer 201 on the surface #202 can also be used (FIG. 3). This layer is then lightly doped as follows to create the P- material that constitutes the MOS transistor.

The MOS transistor is constructed as follows. Initially, another Sin Na layer 203 is added to the polysilicon layer 201.
Formed on top of a thin SRO layer grown above. A second mask 205 is formed over the Si,N4 layer 203 to define an island region over the implanted area 108. 5
The isNn layer 203 is etched away, leaving only the island region 206, and an oxide layer 207 surrounding the island region 206 is grown. The remaining 5isN4 layer 203 is removed and a gate oxide layer 209 of approximately 1,000 A is grown in its place (FIG. 5). The third mask 210 is formed to implant ions into the polysilicon layer 210 on the previous ion implantation part 108 to perform heavy doping. This ion implantation step forms an n+ region 211.

Third mask 210 is removed. A polysilicon layer 212, a heavily doped n-soil layer, is then formed over the exposed oxide layer 209 by chemical vapor deposition. Next, a fourth mask 214 is formed to define the gate region 215 and the source extension region 216 for the storage capacitor region. The exposed areas of polysilicon layer 212 are etched away, leaving masked areas 215, 216 (FIG. 6). The exposed areas of the oxide layer 209 are then ion-implanted into the P-polysilicon layer 201 (MOS).
N- source and n+ drain regions 21 of transistor
8,217 is formed. The fourth mask 214 is then removed and the structure undergoes an anneal and drive-in step.C, n+, P- and extended n+ regions 17.201
．． 218 is formed (FIG. 7).

Next, for example, a thickness of 6,000A I) 8402 layers 301
is formed on the surface. Next, a fifth mask 30 is used to form an access region 303 for the insulated gate 215.
2 is formed. This access area 303 is etched away and the fifth mask 302 is removed (FIG. 8).

Next, for example, metal 43 which is 7.00OA of aluminum
07 is formed on the surface, or (°[access area 303
is filled and connected to the transistor gate 215 (MOS). A final mask is then formed to further define portions of metal layer 307 and passivation areas for interconnects and pads are formed (Figure 9A).

FIG. 11 is a perspective view of various isolated parts of the semiconductor memory cell shown in FIG. 9A.

Next, a conventional semiconductor memory cell will be explained, and the advantages of the semiconductor memory cell according to the present invention will be explained. FIG. 10B is a sectional view of a conventional dynamic random access memory, and FIG. 10C is an electrical equivalent circuit diagram thereof. It is. 10th
In the JIOC diagram, I Cs can be expressed as the oxide layer capacitance tea and depletion layer capacitance It Cb f) tL column coupling.

That is: Cs ” Ca If cb where C,=CB'x area of oxide layer, Cb=Cb'×
It is expressed by the area of the depletion layer, Cj = 8a/l = (Ca is the dielectric constant of the oxide layer, ta is the thickness of the oxide layer), Cb' = ε
b/xb (sb is the dielectric constant of silicon, xb is the depth of the depletion layer). It is clear from Figure 10B that Ca is much larger than Cb, so the storage capacity of the conventional cell is 1 cm.
is c, = ca = ca'·AH where Aa is the surface area of the upper grate that constitutes the capacity.

In the embodiment of FIG. 9A, the storage capacitance is expressed by the following equation, ignoring the depletion layer capacitance.

C3=Ce@Ac·+Cf·Af Here, Ae is the area of the lower plate, and Af is the area of the upper grate. The area of the upper and lower plates ke,i
f is made by a person of approximately the same size CB = 2 C
If a'.A, (A=Ae) is 1, this is twice the 1 each of the prior art cell of FIG. 10B.

When an alpha particle passes through a semiconductor material, a plurality of electron-hole pairs are generated in the particle passage. In the conventional technology
, when an alpha particle hits a region of the cell close to the storage capacitor, the generated electron-hole pairs are collected by the depletion region. These collected electron-hole pairs change the charge Rt in the storage capacitor [generating inaccurate data]. In contrast, the embodiment has an oxide barrier layer 106 and a substrate 103
The electron-hole pairs created therein are prevented from moving into the depletion region. Since the depletion region does not collect these electron-hole pairs, the stored charge in the embodiment is not changed. Although it is possible for electron-hole pairs to form in the extended source region 218 that constitutes the cell storage capacitor, these electron-hole pairs must be recirculated before moving to the drain region 217 where they are collected. Since they are combined, there will be no erroneous reading.

Another advantage of the embodiment is that the bit-line capacity 1l is smaller than the pit-line capacity produced by prior art cells.
It is to have tIt. The pit-line capacitance of the prior art cell of FIG. 10B is shown in FIG. 10D. FIG. 10E is an electrical equivalent circuit diagram of FIG. 10B showing the bit-line capacitance. Capacitance 1cI is the junction capacitance of the domain region to which the pit-line is connected. The size of the capacitance 1cI depends on the area of the drain region. Capacitance Ca occurs at the junction formed by the heavily doped medium and P medium. This n+ and p-decade junction has a large tIk value. Write or read operation is θ
~5V, the substrate bias is -3V, the bit-line voltage is 2.5V, the substrate dog concentration N is 5 x 1014A, and the reverse voltage is 5V, then C1 is given by It will be done.

C+' = 0.03 fF / #F11" Doping concentration Nm/= 2 X to"/d for C2.
And assuming that a reverse voltage of 5V is used, C'2''
It becomes 0.16 fF/fi♂.

A typical prior art cell may have a diffusion layout as shown in FIG. In this structure: C+=(0,03fF/am”)((20X4+4X
4) #m') = 2.9fF/cell, and Cz = (0,16fF/xz") x (20am"
)=3.2fF/cell.

Cy == Cr + Cz = 6.1 f F/cell The bit-line capacitance in one embodiment depends on two capacitances, tCs and CxK. Here, it is a Cr+tMOS capacitor and depends on the area, and C! is the junction capacitor at the bit-line (also area dependent). In the example, the substrate was biased to obtain a minimum of 1 cm of oxide capacitance and the bit-line voltage was 2.5
v and Dawg density Nm = 2 x 10”/1iW
L'' and the oxide thickness 1. is 7.000 mm, then Cm'/(:'', =: 6.6 C'a = Ca/la = 0.049fF/〃@'' Become.

Then Cam' = 0.02 g 1 F7,1rL
* = (,1"2" 0.03 f F15 m"
C,: c, + C.

= (0,029f F/#FF!”)((20X4+
4X4 ) am"J ten (0,03fF/a@") (4X
0.5a@') = 2,8 f F/cell.

This total pit-line capacity 1c is less than 1×2 of the total capacity in the prior art described above. Thus, by having a small bit-rhi/capacity, the d R
AM cells provide faster operation without signal degradation.

Embodiments of the present invention also have the advantage of reduced leakage. IEEE) Ranzaxiron on Elect o = Tsuku Debye x Vol ED-26, No. 4 (April 1979 issue), pages 564 to #76, shows that the following five major leakage sources exist in cells of the prior art. There is C.

L　Peripheral and field damage due to inherent crystal damage Generation of electron-hole pairs.

2 Generation of electron-hole pairs from the storage gate or depletion region.

3 Generation of electron-hole pairs due to avalanche or multiplication effect.

4 Generation of electron-hole pairs under the transfer gate.

a Electron-hole pairs created in the bulk substrate that diffuse into the region where they are collected.

The authors of the above article conclude that the primary source for leakage in dRAM begins at the source just outside the storage gate region. In embodiments of the invention, this cause is eliminated. That is, embodiments include an oxide barrier to prevent electron-hole pairs from being collected near the storage capacitor. In addition, since the structure according to the example has few electron-hole pairs,
Avalanche or multiplication effects are greatly reduced and another source of leakage is eliminated or minimized. therefore,
Compared to prior art cells, the leakage of the cell of the present invention is significantly reduced.

[Brief explanation of the drawing]

1X1 to FIG. 8 are manufacturing process diagrams of a semiconductor memory cell according to the present invention, FIG. 9A is a cross-sectional view of a semiconductor memory cell according to an embodiment of the present invention, and FIG. 9B is a semiconductor memory according to another embodiment of the present invention. A sectional view of a cell, FIG. 10A is an electrical equivalent circuit diagram of the semiconductor memory cell shown in FIG. 9 and FIG. 98, and FIG. 108 is a sectional view of a conventional semiconductor memory cell.
@Figure 10C is an electrical equivalent circuit diagram of the semiconductor memory cell shown in Figure 108, and Figure 10D is a partial cross-sectional view of the semiconductor memory cell shown in Figure 10B. FIG. 108 is an electrical equivalent circuit diagram showing the bit-line capacitance of the semiconductor memory cell shown in FIG. 10B, FIG. 11 is an exploded perspective view of each part of the semiconductor memory cell shown in FIGS. 9A and 9B, FIG. 12 is a diagram showing the layout of the semiconductor memory cell shown in FIG. 10B. Two semiconductor substrates 103, tRT107, 106, 209, 301: Oxide layer 2
01.212: Polysilicon layer ios: Ion implantation layer 215: Insulated gate 102.205, 207, 210, 214.302:
Mask applicant: Yokotsutsu - Hugh V. Nodo Patsu Card Co., Ltd. agent Patent attorney and Tsugu Tanigawa FIG
10B '''' FIG IOc FIG
12lG11 Procedural Amendment 1978 388 0 Office Commissioner's Palace l - Indication of Case 1981 Patent Asaho 1
1195 No. 2, Title of the invention Semiconductor memory cell 3, Relationship with the case of the person making the amendment Patent application Person Sasa
Oh Ganozou Representative Director and President Ken Sasaoka Address 3-6 Agent Address 911 Takakuracho, Heoji City, Tokyo
No. 1-9, 1 7, C3-ζIIcゎ on page 7, line s1 of the letter detailing the contents of the amendment, Cs-Ca
” Correct as Cb.

Claims (1)

[Scope of Claims] A semiconductor memory cell consisting of the following (a) a semiconductor substrate-) a first insulating layer formed on the substrate and having a thin insulating region in a part; a MOS transistor formed on one insulating layer and having a source, a gate and a drain/region, the source region having an extended source region extending over the thin insulating region; a first semiconductor layer formed under the thin insulating region in the semiconductor substrate and forming a first storage capacitor in the second insulating layer, the spread source region, and the second insulating layer; an extended source region, a second semiconductor layer forming a second storage capacitor with the first insulating layer;