JPS56126978A - Manufacture of junction type field effect transistor - Google Patents

Manufacture of junction type field effect transistor

Info

Publication number
JPS56126978A
JPS56126978A JP3143180A JP3143180A JPS56126978A JP S56126978 A JPS56126978 A JP S56126978A JP 3143180 A JP3143180 A JP 3143180A JP 3143180 A JP3143180 A JP 3143180A JP S56126978 A JPS56126978 A JP S56126978A
Authority
JP
Japan
Prior art keywords
groove
substrate
layer
region
gate
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP3143180A
Other languages
Japanese (ja)
Other versions
JPS6222462B2 (en
Inventor
Kiyoshi Sakai
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp, Nippon Electric Co Ltd filed Critical NEC Corp
Priority to JP3143180A priority Critical patent/JPS56126978A/en
Publication of JPS56126978A publication Critical patent/JPS56126978A/en
Publication of JPS6222462B2 publication Critical patent/JPS6222462B2/ja
Granted legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/80—Field effect transistors with field effect produced by a PN or other rectifying junction gate, i.e. potential-jump barrier
    • H01L29/808—Field effect transistors with field effect produced by a PN or other rectifying junction gate, i.e. potential-jump barrier with a PN junction gate, e.g. PN homojunction gate

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Ceramic Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Electrodes Of Semiconductors (AREA)
  • Junction Field-Effect Transistors (AREA)

Abstract

PURPOSE:To reduce the parasitic capacity of a junction type field effect transistor by forming a groove on a semiconductor substrate, forming a reverse conductivity type region confronting the groove and forming one conductivity type region in the groove as a gate electrode. CONSTITUTION:An N type impurity containing layer 2 and an insulating layer 3 are formed on a P type Si substrate 1. A groove is formed at the layers 3, 2 and substrate 1. An insulating layer 5 for the substrate 1 and the surface of the groove is then formed. The bottom part of the layer 5 is subsequently selectively removed. An N type region 7 is formed on the exposed part of the substrate 1 on the bottom of the groove. Thereafter, with region 2 as a diffusion source an N type impurity diffused layer 8 is formed. Thereafter, a P type impurity region 9 is formed on the bottom of the groove. Then, a hole is opened at the layer 3, and gate, drain and source electrodes 10, 11 and 12 are formed. Thus, the parasitic capacities between the gate and the drain and between the gate and the source can be largely reduced.
JP3143180A 1980-03-11 1980-03-11 Manufacture of junction type field effect transistor Granted JPS56126978A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP3143180A JPS56126978A (en) 1980-03-11 1980-03-11 Manufacture of junction type field effect transistor

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP3143180A JPS56126978A (en) 1980-03-11 1980-03-11 Manufacture of junction type field effect transistor

Publications (2)

Publication Number Publication Date
JPS56126978A true JPS56126978A (en) 1981-10-05
JPS6222462B2 JPS6222462B2 (en) 1987-05-18

Family

ID=12331041

Family Applications (1)

Application Number Title Priority Date Filing Date
JP3143180A Granted JPS56126978A (en) 1980-03-11 1980-03-11 Manufacture of junction type field effect transistor

Country Status (1)

Country Link
JP (1) JPS56126978A (en)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6375439A (en) * 1986-09-18 1988-04-05 Toho Kasei Kk Fluid heater

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5469388A (en) * 1977-11-14 1979-06-04 Matsushita Electric Ind Co Ltd Junction type field effect semiconductor device and its production

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5469388A (en) * 1977-11-14 1979-06-04 Matsushita Electric Ind Co Ltd Junction type field effect semiconductor device and its production

Also Published As

Publication number Publication date
JPS6222462B2 (en) 1987-05-18

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