JPS5779660A - Semiconductor memory device - Google Patents
Semiconductor memory deviceInfo
- Publication number
- JPS5779660A JPS5779660A JP55156084A JP15608480A JPS5779660A JP S5779660 A JPS5779660 A JP S5779660A JP 55156084 A JP55156084 A JP 55156084A JP 15608480 A JP15608480 A JP 15608480A JP S5779660 A JPS5779660 A JP S5779660A
- Authority
- JP
- Japan
- Prior art keywords
- layer
- region
- diffusion
- poly
- capacitor
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B12/00—Dynamic random access memory [DRAM] devices
- H10B12/30—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
Abstract
PURPOSE:To reduce the area of a memory cell, by longitudinally and cubicly constituting a capacitor between a separation layer formed on a 1st conductor substrate and a 2nd conductor epitaxial region diffused below, and a diffusion layer connected to a transfer gate and a bit line. CONSTITUTION:An N<+> diffusion region 8 for a memory capacity is formed to extend as far as beneath a separation oxide film 2 on a P type semiconductor substrate 1. A P type region 9 and N<+> diffusion layer 10 are formed by epitaxial growth on the region 8. A poly-silicon layer for a transfer gate is connected to the layer 9 via a dielectric thin film 7. The P-N junction capacitance between the N<+> region 8 of a large area and the substrate acts as capacitor. This partial charge is controlled by an FET which holds the P type layer 9 and the poly- silicon layer 5 with the thin film layer 7. The N<+> layer 10 is connected to a bit line. This reduces a cell area and makes high-dense.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP55156084A JPS5779660A (en) | 1980-11-05 | 1980-11-05 | Semiconductor memory device |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP55156084A JPS5779660A (en) | 1980-11-05 | 1980-11-05 | Semiconductor memory device |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS5779660A true JPS5779660A (en) | 1982-05-18 |
Family
ID=15619943
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP55156084A Pending JPS5779660A (en) | 1980-11-05 | 1980-11-05 | Semiconductor memory device |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS5779660A (en) |
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
EP0098111A2 (en) * | 1982-06-24 | 1984-01-11 | Harris Semiconductor Patents, Inc. | Vertical IGFET device and method for fabricating same |
US4554570A (en) * | 1982-06-24 | 1985-11-19 | Rca Corporation | Vertically integrated IGFET device |
-
1980
- 1980-11-05 JP JP55156084A patent/JPS5779660A/en active Pending
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
EP0098111A2 (en) * | 1982-06-24 | 1984-01-11 | Harris Semiconductor Patents, Inc. | Vertical IGFET device and method for fabricating same |
US4554570A (en) * | 1982-06-24 | 1985-11-19 | Rca Corporation | Vertically integrated IGFET device |
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