JPS5996762A - Semiconductor device - Google Patents

Abstract

PURPOSE:To enable to increase the capacitance of a capacitance element without increasing the number of processes by providing a plurality of grooves of the same depth as that of a groove for forming an island region on the surface of each capacitor element at the same with the formation of the island region. CONSTITUTION:A system wherein grooves 100 formed by etching in N type epitaxial layer 2 and P type impurity regions 4 are both used is used for isolating elements. A plurality of grooves 200 having the same depth as the etched groove 100 used for the element isolation are formed on the surface of each capacitance element at the same time with the formation of the grooves 100, an insulation film 3 is formed thereon, and further an electrode 6 is formed thereon, resulting in the formation of an MOS capacitor structure by means of the electrode 6, the insulation film 3, and the P type impurity region 5. An electrode 7 provided by penetrating through the insulation film 3 conducts with the P type impurity region 5. The MOS capacitor having this structure can utilize also the area of the side wall surface of the groove 200 formed on the surface of the capacitor element as a charge accumulation area, therefore the capacitor increases by the increment of this side wall area.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Application of the Invention] The present invention relates to the structure of a semiconductor device, and more specifically, a second conductive type semiconductor layer is formed on a first conductive type semiconductor substrate, The second conductivity type semiconductor layer is separated into a plurality of island regions by a groove formed in the second conductivity type semiconductor layer and a channel blocking region formed below the groove so as to reach the first conductivity type semiconductor substrate.

An insulating film is formed on the surface of this island region, and an MIS (metal-insulating film-semiconductor) type capacitive element is formed by the metal layer formed on this insulating film, the insulating film, and the semiconductor region below it. The present invention relates to a semiconductor device which is designed to increase the capacitance of a capacitive element. [Prior Art] Conventionally, an MIS type capacitive element whose cross-sectional structure is shown in FIG. 1 has been used. That is, a second conductivity type (n type) semiconductor layer 2 is formed on a first conductivity type (for example, p type) semiconductor substrate 1.
A trench 100 formed in this semiconductor layer 2 and a channel blocking region (p+ type region 4) formed below this trench 100 to reach the semiconductor substrate 1 form an island region. An insulating film 3 is formed on the surface of the island region, and a capacitive element is formed by the metal electrode 6 formed on the insulating film 3, the insulating film 3, and the semiconductor region (p-type impurity region) 5 below it. In addition, 7 in Fig. 1 is an electrode for extracting electric charges (see Japanese Patent Application No. 177201/1983).
In the diagram structure, since the area in which charges are accumulated is determined by the plane area of the electrode 6, there is a problem in that the capacitance decreases as the element becomes finer. To deal with this,
Dig a groove in the MO8 capacitor.

A method was proposed in which the capacitance was increased by using the surface of the inner wall of this groove as a capacitor (in Japanese Patent Application Laid-Open No. 2002-121000), an insulating film (e.g. 5102) was formed as an etching mask, and an etching hole 29 was formed in this insulating film. is formed by the both etching method. Then, orientation-dependent enching (orje
ntation dependent etching
) - that is, 1. For example, the pores 26 are formed by etching that takes advantage of the property that the etching rate of the I011 plane of silicon is as slow as 1/400 of that of other planes under appropriate conditions. As shown, a region 5 having a conductivity type opposite to that of the semiconductor layer 22 is formed by a known thermal diffusion or ion implantation method except for the region to be the source and the insulating film in the pore portion. Next, as shown in Figure 1(C), the insulating film part is ruptured by thermal oxidation or the like, and electrode connection holes 2o are formed by bottom etching or the like, and then the gate electrode path and the source electrode are formed as shown in Figure 1(a). form 27. and 1MB hole 2
In this method, the region 5 formed in the semiconductor layer 6 is used as a drain, and the junction capacitance between the drain and the semiconductor layer 22 is used as an information storage section.

However, the method shown in Figure 2 requires the addition of a step to form pores, which complicates the process (5 problems).

[Purpose of the invention]

SUMMARY OF THE INVENTION An object of the present invention is to provide a semiconductor device having a structure that solves the above-mentioned problems in the prior art and allows the capacitance of a capacitive element to be increased without increasing the number of steps.

[Summary of the invention]

The features of the present invention are to achieve the above object.

A plurality of grooves having the same depth as the groove for forming the island region are provided on the surface of each capacitive element at the same time as the island region is formed, thereby forming an uneven structure on the surface of each capacitive element.

[Embodiments of the invention]

An embodiment of the present invention will be described below with reference to FIG. Third
The figure shows a cross-sectional structure of a MOS capacitor formed using the present invention. The element portion mK is obtained by using a method in which a trench 100 formed by etching the n-type epitaxial layer 2 and a p-type impurity region 4 are used together. A plurality of grooves 200 (four in the example) are formed on the surface of each capacitive element at the same time as the grooves 100 are formed, an insulating film 3 is formed thereon, and an electrode 6 is formed thereon. 6
A MOS capacitor structure is formed by the insulating film 3 and the p-type impurity region 5. Reference numeral 7 denotes an electrode provided penetrating through the insulating film 3, and is electrically connected to the p-type impurity region 5.

In the capacitive element of the conventional structure shown in FIG. 1, the area where charges are accumulated is the area of the plane of the electrode 6, but in the MOS capacitor with the structure of the embodiment shown in FIG. Since the area of the side wall surface can also be used as a charge storage area, the capacitance increases by the increase in side wall area.
Since this is carried out simultaneously with the formation of 0, there is also the advantage that there is no need to add the groove forming step which was necessary in the case of the conventional example shown in FIG. Although the T-type impurity region 5 is in contact with the n+ impurity region 8 at .degree. C. in FIG. 3, this is not essential. That is, p-type impurity region 5 only needs to be formed within the n-type impurity region, and the same effect can be obtained whether it is in contact with n+-type impurity region 8 or apart. Furthermore, a similar effect can be obtained with a structure in which n impurity region 8 in FIG. 3 is removed.

〔Effect of the invention〕

According to the present invention, the capacitance of a MIS type capacitive element can be increased without increasing its planar area, and in this case, the grooves formed on the element surface are formed at the same time as the etching grooves for element isolation are formed. Since the manufacturing process is similar, there is no need to increase the number of manufacturing steps. For example, if an etched groove with a depth of 1 μm is formed on the element surface, it will take 20 to 30% less to obtain the same capacitance.
This makes it possible to reduce the plane area of the product, and there is no increase in the number of manufacturing steps.

If applied to highly integrated LSIs, the economic effect will be extremely large.

[Brief explanation of drawings]

FIG. 1 and FIG. 2 are sectional views for explaining the prior art, respectively;
FIG. 3 is a sectional view for explaining the present invention in detail. Explanation of symbols 1...P-type semiconductor substrate 2...N-type epitaxial layer 3...Insulating film 4...P shadow region 5...
P-type impurity region 6, 7... Electrode 8... n Shadow region 100, 200... Mizo Patent attorney Junnosuke Nakamura 1 Figure continued from page 1 0 Inventor Minoru Nagata Higashi Koigakubo, Kokubunji City - 280-chome Central Research Laboratory, Hitachi, Ltd. Applicant Hitachi Microcomputer Engineering Co., Ltd. 1479 Josui Honmachi, Kodaira City

Claims (1)

[Claims] A second conductivity type semiconductor layer is formed on the first conductivity type semiconductor substrate, and a groove is formed in the second conductivity type semiconductor layer and a groove is formed below the groove so as to reach the first conductivity type semiconductor substrate. The second conductivity type semiconductor layer is separated into a plurality of island regions by the channel blocking region, an insulating film is formed on the surface of the island region, and a metal layer formed on the insulating film and the above-mentioned insulating/insulating film are separated. In a semiconductor device in which an MIS (metal-insulator-semiconductor) type capacitive element is formed with the semiconductor region below, a plurality of grooves having the same depth as the groove for forming the island region are formed on the surface of the capacitive element. A semiconductor device characterized in that grooves are provided at the same time as island regions are formed to form irregularities on the surface of a capacitive element.