JP3421569B2 - Semiconductor device and manufacturing method thereof - Google Patents

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device and its manufacturing method.

[0002]

2. Description of the Related Art In a conventional semiconductor device, an impurity diffusion layer, a gate and a contact hole are formed on a surface portion of a semiconductor substrate having no unevenness by using a resist pattern. Figure 6
The cross-sectional structure of a conventional MOS transistor is shown in FIG. A drain 62 and a source 63 made of an n-type impurity diffusion layer are formed at a predetermined interval on the surface of a flat p-type semiconductor substrate 61, and a gate electrode 65 is formed on the surface of the drain 62 and source 63 via a gate oxide film 64. The N-channel type MOS transistor 66 is constituted by this. However, in such a conventional semiconductor device, the size of a transistor that can be manufactured is inevitably larger than the minimum processing size F corresponding to the limit of the photo-etching technique, and a size of 2F is generally required. . For this reason, there has been a limit in improving the degree of integration in the past.

[0003]

As described above, devices are conventionally formed on the surface of a flat semiconductor substrate, and a size larger than the minimum processing size F is required, and the degree of integration cannot be improved. There was a problem.

The present invention has been made in view of the above circumstances, and an object thereof is to provide a semiconductor device capable of improving the degree of integration and a manufacturing method thereof.

[0005]

The semiconductor device of the present invention comprises:
The surface is processed into a sawtooth shape with a periodic triangular shape,
A mountain portion and a valley portion that respectively extend along the column direction are alternately formed in the row direction, and a gate formed so as to extend in the column direction through an insulating film in the valley portion, and An active element including a source and a drain formed in the respective peaks along the two side surfaces of the valley in which the gate is formed, and an insulator selectively buried in the row direction in the valley. And an element isolation layer for electrically isolating between the two active elements or between the impurity layers respectively disposed on two side surfaces of the valley along the row direction. .

The surface of the semiconductor substrate is processed into a sawtooth shape having a periodic triangular shape, and at a portion where a gate is formed in a valley portion, impurities formed in the gate and a mountain portion on both sides of the valley portion are formed. An active element is formed with the diffusion layer, and the impurity diffusion layer of this active element is isolated by the adjacent valley portion acting as an element isolation region. By thus forming the active element or the element isolation region in the valley, the element area is reduced.

Here, the active element has a first conductivity type impurity diffusion layer formed in adjacent first and second ridges and a first ridge between the first and second ridges. A first-conductivity-type active layer including a second-conductivity-type impurity diffusion layer formed in the valley and a first gate formed in the first valley along the column direction through the insulating film. Element and third adjacent
And a second conductivity type impurity diffusion layer formed in the fourth crest, and a first conductivity type impurity diffusion layer formed in the second valley between the third and fourth crests. And a second conductive type active element including a second gate formed in the second valley portion along the column direction via the insulating film. Further, in the surface processed in a sawtooth shape having a periodic triangular shape, an element in a column direction formed by filling an insulator deeper than the valley portion in the valley portion extending along the column direction. It is also possible to further include a separation region.

In order to increase the driving current and to reduce the area occupied by the active element, the direction of the driving current flowing in the active element is the sawtoothed surface having a periodic triangular shape. May be in the row direction.

According to the method of manufacturing a semiconductor device of the present invention, the surface of a semiconductor substrate on which an impurity diffusion layer is formed is processed into a sawtooth shape having a periodic triangular shape, and a peak portion formed of the impurity diffusion layer is formed. A step of forming a trough separating the impurity diffusion layer, and a step of selectively forming a gate in a predetermined portion of the trough, wherein the trough having the gate is formed. It is characterized in that an active element is constituted by the impurity diffusion layer and the gate on the peaks on both sides of the valley, and the peaks where the gate is not formed are used as element isolation regions.

The method of manufacturing a semiconductor device according to the present invention further comprises a step of introducing an impurity into a surface portion of a semiconductor substrate to form an impurity diffusion layer, and forming a predetermined shape on the surface of the impurity diffusion layer at predetermined intervals. A step of forming a patterned mask material, a step of performing crystal anisotropic etching on a surface portion of the semiconductor substrate using the mask material as a mask to dig a V-shaped groove deeper than the impurity diffusion layer, and a step of forming the groove. Filling the inside with a first insulating film, removing the mask material,
A step of exposing the surface of the semiconductor substrate, and a crystal anisotropic etching are performed on a surface portion of the semiconductor substrate which is not covered with the first insulating film and whose surface is exposed, to form a V-shaped deeper than the impurity diffusion layer. A step of digging a groove of a mold, a step of removing the first insulating film to form a sawtooth semiconductor substrate in which peaks and valleys are periodically arranged at predetermined intervals, and a surface of the semiconductor substrate A step of forming a second insulating film so as to cover,
A step of selectively forming a gate on the second insulating film at a predetermined location in the valley on the surface of the semiconductor substrate.

Further, the method of manufacturing a semiconductor device according to the present invention comprises a step of forming a first resist film for separating elements in the column direction on the surface of a semiconductor substrate on which an impurity diffusion layer is formed. A step of digging a trench type groove in the surface portion of the semiconductor substrate which is not covered with the first resist film so that the surface of the semiconductor substrate is exposed at the bottom surface;
Filling the inside of the groove with a first insulating film;
Removing the resist film, forming a second resist film for processing the surface of the semiconductor substrate into a sawtooth shape having a periodic triangular shape in the row direction at predetermined intervals, and the second A step of performing crystal anisotropic etching on the surface portion of the semiconductor substrate which is not covered with the resist film, and digging a V-shaped groove deeper than the impurity diffusion layer so that the surface of the semiconductor substrate is exposed on the bottom surface. A step of filling the inside of the V-shaped groove with an insulating film, a step of removing the second resist film to expose the surface of the semiconductor substrate, and a step of covering the surface of the semiconductor substrate without being covered with the insulating film. A step of performing crystal anisotropic etching on the exposed surface of the semiconductor substrate to dig a V-shaped groove deeper than the impurity diffusion layer, the groove being separated in the column direction by the trench type groove and in the row direction. At a certain interval A step of forming a sawtooth semiconductor substrate in which valleys are periodically arranged, further forming a second insulating film so as to cover the surface of the semiconductor substrate, and among the valleys on the surface of the semiconductor substrate, A step of selectively forming a gate on the second insulating film at a predetermined location.

According to the method of manufacturing a semiconductor device of the present invention, the first trench groove in which the elements are separated in the column direction and the inside is filled with the first insulating film is formed, and the peak portions are formed at predetermined intervals in the row direction. Valleys are arranged in a sawtooth shape having a periodic triangular shape, impurity diffusion layers are formed in the ridges, and the first trench grooves are formed in the surface portion of the semiconductor substrate separated from each other by the valleys. In the formed region, a step of digging a second trench groove deeper than the bottom surface of the valley adjacent to the valley forming the gate, and the peak and valley of the semiconductor substrate not covered with the insulating film. Forming a second insulating film on the surface of the first portion, covering a predetermined valley portion of the valley portion where a gate is not formed with a first mask material,
By depositing a conductive material on the valley portion not covered with the mask material and on the bottom surface of the second trench groove adjacent to the valley portion, a gate is formed on the bottom surface of the valley portion and Forming a conductive film connected to the gate on the bottom surface of the second trench groove; removing the first mask material;
A step of forming a second mask material so as to cover the entire region where the trench groove is formed, and a third insulating film is deposited on a portion not covered with the second mask material, and a planarization process is performed. After that, a step of removing the second mask material and a step of depositing a conductive material on the surface of the conductive film formed on the bottom surface of the second trench groove to form a gate contact are provided. It is characterized by that.

[0013]

BEST MODE FOR CARRYING OUT THE INVENTION An embodiment of the present invention will be described below with reference to the drawings.

The present embodiment is based on the following idea. As shown in FIG. 3, when the flat semiconductor substrate 1 having no unevenness on the surface is used, the occupied area becomes large. However, if the semiconductor substrate 2 having a sawtooth-shaped surface with a constant surface area is used, the occupied area can be reduced and the degree of integration can be improved.

As described above, in the present embodiment, the active element or the element isolation region is selectively formed in the surface portion of the semiconductor substrate 2 whose surface is processed into the sawtooth shape, thereby improving the integration degree. ing. Here, when processing on a sawtooth, the distance between peaks corresponds to the minimum processing size F, and a horizontal VMOSFET (V-SHAPED METAL OXIDE) in which a drive current flows horizontally in the horizontal direction on the substrate surface with one valley as a unit. SEMICONDUCTOR
Form one FIELD EFFECT TRANSISTOR). When a gate is formed in the valley, one functional element corresponding to one MOS transistor is formed by this gate and the impurity diffusion layers on both sides of the valley. When no gate is formed in the valley, this valley is formed. The portion acts as an element isolation region.

Next, a procedure for forming the peaks and valleys by processing the surface of the semiconductor substrate into a sawtooth shape by the manufacturing method according to the present embodiment will be described.

First, as shown in FIG. 2A, an n-type impurity is introduced into the (100) plane of the p-type semiconductor substrate 11 to form an n-type impurity diffusion layer 12. The diffusion layer 12 is formed, for example, by forming a silicon oxide film or a silicon nitride film on the surface of the semiconductor substrate 11 while introducing an n-type impurity, or by forming a film and then implanting impurity ions,
The thermal diffusion can be performed by diffusing the impurities introduced into the film to the surface of the semiconductor substrate 11.

CV is formed on the entire surface of the n-type impurity diffusion layer 12.
The silicon nitride (SiN) film 13 is formed as a mask material by using the D (CHEMICAL VAPOR DEPOSITION) method. A resist is applied on the surface of the silicon nitride film 13 and patterned into a desired shape to form a resist film 14.
Here, the distance between the resist films 14 corresponds to the minimum processing dimension F.

As shown in FIG. 2B, the silicon nitride film 13 is subjected to reactive ion etching (REACTIVE ION ETCHING) using the resist film 14 as a mask to obtain a patterned silicon nitride film 13. After this, the resist film 14
To remove.

As shown in FIG. 2C, the silicon nitride film 13 is formed.
Is used as a mask material to perform crystallographic plane anisotropic etching (see LSI Handbook, Ohm Co., pages 264 to 265) on the surface of the semiconductor substrate 11 to form a V-shape so that the (111) plane is exposed. Dig the groove 15. Where the groove 15
It is necessary to set the depth of the n-type diffusion layer 12 and the depth of the groove 15 so that the surface of the p-type semiconductor substrate 12 is exposed at the valley portion of the. As a result, the n-type diffusion layers 12 remaining in the ridges are separated from each other by the grooves 15.

As shown in FIG. 2D, a silicon oxide film (Si) is formed by the CVD method so as to fill the inside of the groove 15.
O ₂ ) 16 is deposited.

As shown in FIG. 2E, H _{3 is} generated at 180 degrees Celsius.
The PO ₄ solution is used to remove the silicon nitride film 13 to expose the surface of the semiconductor substrate 11 at this portion.

As shown in FIG. 2F, the silicon oxide film 16
Using as a mask, the exposed surface of the semiconductor substrate 11 is again subjected to crystallographic plane anisotropic etching. As a result, the semiconductor substrate 1 not covered with the silicon oxide film 16
A V-shaped groove 17 is formed on the surface of 1. After that, the silicon oxide film 16 is removed using hydrofluoric acid. As a result, as shown in FIG. 2 (g), the n-type impurity diffusion layers 12 are separated from each other by the grooves 15 and 17 formed by two crystallographic plane anisotropic etchings. Can be obtained.

By the way, in order to arrange a plurality of cells in a matrix on the surface of the substrate, it is necessary to separate the cells arranged in adjacent rows from each other along the column direction. As a pre-step of processing the surface of the semiconductor substrate into a sawtooth shape through the above-described steps, the procedure for forming trench-type element isolation regions in the column direction along the row direction will be described with reference to FIG. explain. Here, it is assumed that the n-type impurity diffusion layer 21 is previously formed on the surface of the semiconductor substrate.

As shown in FIG. 4A, on the n-type impurity diffusion layer 21 formed on the surface of the semiconductor substrate, elements are isolated in the column direction which is patterned at the interval of the minimum processing dimension F. A resist film 22 is formed. Using the resist film 22 as a mask, the surface of the semiconductor substrate is etched to form a trench type groove. A silicon oxide film (SiO ₂ ) 23 is deposited by the CVD method as shown in FIG. 4B so as to fill the formed trench groove.

As shown in FIG. 4C, the resist film 22 is peeled off to expose the surface of the n-type impurity diffusion layer 21.

After performing element isolation in the column direction, the surface of the semiconductor substrate is processed into a sawtooth shape. As shown in FIG. 4D, a resist film 24 for processing in a sawtooth shape is formed at intervals of the minimum processing dimension F in the row direction. Using the resist film 24 as a mask, the surface of the semiconductor substrate is subjected to two crystallographically anisotropic etchings to dig a V-shaped groove in which peaks and valleys are arranged in the row direction.

Through the above steps, FIG.
As shown in FIG. 5, it is possible to obtain a semiconductor substrate in which the element isolation regions in the column direction are formed by the trench grooves, and the ridges 33 and the valleys 34 are alternately arranged in the row direction to form a sawtooth shape. Here, although the sawtooth-shaped processing is performed after the element isolation in the column direction, the element isolation in the column direction may be performed after performing the sawtooth-shaped processing by reversing the processing order.

After the elements are separated in the column direction as shown in FIG. 5 and processed into a sawtooth shape so that the valley portions 34 and the peak portions 33 are arranged in the row direction, they are shown in FIG. As described above, the silicon oxide film 58 is formed on the entire surface by using the thermal oxidation method. Then, of the plurality of valleys, a metal material is selectively epitaxially grown using a mask material, or silicon is epitaxially grown or graphoepitaxially grown and deposited to form the gate 53. Further, a silicon oxide film (not shown) is deposited by the CVD method so as to cover the entire surface.

Here, the gate 53 is selectively formed among the plurality of valleys. In the valley portion where the gate 53 is formed, the lateral VMOSFET 55 is formed by the source 52 and the drain 51 which are the n-type impurity diffusion layers on both sides of the valley portion.
Will be configured. The valley portion 59 in which the gate 53 is not formed has the n-type impurity diffusion layer 42 in the mountain portion on both sides thereof.
And 43 are separated, a V-shaped element isolation layer 59 in the row direction is formed.

According to this embodiment having the lateral VMOSFET and the V-shaped element isolation layer as described above, one active element has the same size as the minimum processing dimension F as shown in FIG. It is formed. As described above with reference to FIG. 6, in comparison with the conventional case where the size of at least 2F is required to form one active element, the present embodiment significantly improves the degree of integration. It is possible.

Further, according to the manufacturing method described above, it is possible to form one transistor with the minimum processing dimension F regardless of the type of the photo-etching technique. Therefore, even when the minimum processing dimension F is further reduced by using an electron beam or an X-ray, the present embodiment can be applied to increase the degree of integration.

Further, in the element structure according to the above-mentioned embodiment, since the impurity diffusion layers of the adjacent peaks are separated by the V-shaped valleys located between them, punch through is effectively performed. It is possible to prevent.

FIG. 7 shows a sectional structure of a CMOS circuit formed by combining the lateral VMOSFET and the V-shaped element isolation layer described above. The surface of the p-type semiconductor substrate 101 is processed into a saw-tooth shape by the above-described procedure to form peaks and valleys, and the n-type impurity diffusion layers 111 and 11 are formed in the peaks.
2 is formed, or p is formed on the surface of the n-well 102.
The type impurity diffusion layers 104 and 105 are formed and are separated by valleys. Gate 11 formed in the valley
3 and the n-type impurity diffusion layers 111 and 112 formed on the peaks on both sides of the valley, the n-type MOS transistor 11
4 is formed, the gate 106 is formed in the valley so as to be adjacent to the transistor 114, and the p-type impurity diffusion layers 104 and 105 are formed in the peaks on both sides of the valley.
And form a p-type MOS transistor 107.
Here, one diffusion layer 111 of the n-type MOS transistor 113 and one diffusion layer 105 of the p-type MOS transistor 107 are electrically connected by the metal wiring layer 121. Further, the other diffusion layer 112 of the n-type MOS transistor 114 and the other diffusion layer 115 adjacent thereto are separated from each other by the valley portion 114 in which the gate is not formed, and similarly, the other diffusion layer 112 of the p-type MOS transistor 107 is separated. The diffusion layer 104 and the other diffusion layer 116 adjacent thereto are isolated from each other by the valley portion 103 in which the gate is not formed.

As described above, by applying the present embodiment to the CMOS circuit, a set of n-type MOS transistor 114 and p-type MOS transistor 107 and valleys 114 and 103 acting as element isolation regions are formed. It can fit in the size of 5F.

Similarly, the above-mentioned lateral VMOSFET and V
DRAM formed by combining with a V-shaped element isolation layer
Fig. 8 shows the cross-sectional structure of the (DYNAMIC RANDOM ACCESS MEMORY) circuit. The surface of the p-type semiconductor substrate 130 is processed into a sawtooth shape to form peaks and valleys, and n-type impurity diffusion layers 132 and 133, 141 and 142 are formed in the peaks, and the valleys form the valleys, respectively. It is separated. The gate 134 formed in the valley and the n-type impurity diffusion layers 132 and 133 on both sides of the gate form an n-type MOS transistor 135. Similarly, the gate 143 formed in the valley and its An n-type MOS transistor 137 is formed by the n-type impurity diffusion layers 141 and 142 located on both sides of the mountain. One diffusion layer 136 of the n-type MOS transistor 135 and one diffusion layer 142 of the n-type MOS transistor 137 are connected by a bit line 146, and a silicon oxide film 144 is formed on the upper surface of the bit line 146. ing.

The n-type MOS transistor 135 and n
A trench groove 145 used as a capacitor is formed between the MOS transistor 137 and the type MOS transistor 137. The trench groove 145 has an n-type impurity diffusion layer 138 and a silicon oxide film 141 formed on the inner surface, and polycrystalline silicon 142 is deposited so as to fill the inside of the groove. As described above, by applying this embodiment to a DRAM, one MOS transistor, a valley portion functioning as an element isolation, and a trench groove 145 as a capacitance can be accommodated in a total size of 3F. it can.

Next, a method of forming a gate contact according to this embodiment will be described. As described above, according to the present embodiment, the substrate surface is processed into the sawtooth shape at the interval of the minimum processing dimension F, and the gate is formed in the valley portion. Therefore, it is dimensionally difficult to form a gate contact directly with respect to the gate formed in the valley. Therefore, a gate contact is formed in a portion adjacent to the gate in the element isolation region that is isolated in the column direction by the following method.

FIG. 9A shows a planar structure of the device. p
The surface of the n-type impurity diffusion layer 154 is formed on the surface of the n-type semiconductor substrate 153.
Are processed into a sawtooth shape so that the peaks 151 in which the ridges are formed and the valleys 152 in which the surface of the substrate 153 is exposed are aligned in the row direction,
A trench groove that separates in the column direction is formed as an element isolation region, and the inside of the trench groove is filled with a silicon oxide film 155. Here, the depth of the trench groove is formed sufficiently deeper than the valley portion 152 as described later.

As shown in FIG. 9B, a mask material is selectively formed to form a trench groove 156 shallower than the trench groove and having a smaller area in the element isolation region where the trench groove is formed. The trench groove 156 is provided adjacent to the valley forming the gate. Further, it is necessary to dig the bottom of the trench groove 156 so as to be deeper than the bottom of the valley 152. Further, the trench groove separating in the column direction needs to have a sufficient depth so that the silicon oxide film 155 is sufficiently deposited on the bottom surface of the trench groove 156.

As shown in FIG. 9C, a thermal oxidation method is used so as to cover the entire surfaces of the semiconductor substrate 153 and the impurity diffusion layer 154 except the element isolation region where the silicon oxide film 155 is formed. A silicon oxide film 158 is formed. The silicon oxide film 158 is also formed on the side surface of the trench groove 156 where the substrate is exposed 157.

Next, as shown in FIG. 10A, the portion of the valley portion 152 where the gate is not formed is mask material 16.
The surface of the silicon oxide film 158 is exposed in the valley portion 152 which is covered with 1 and forms the gate.

As shown in FIG. 10B, a metal material is deposited by an epitaxial growth method or silicon is deposited on the valley portion 152 which is not covered with the mask material 161 and whose surface is covered with the silicon oxide film 158. Epitaxial growth is performed to selectively form the gate 172 in the valley 152. At this time, at the same time, a conductive film made of a metal material or silicon is deposited on the bottom surface of the trench groove 156 adjacent to the gate 172 while being connected to the gate 172. Then, the mask material 161 is peeled off.

As shown in FIG. 10C, a mask material 182 is formed on the entire element isolation region which is separated in the column direction.

As shown in FIG. 11A, a silicon oxide film 183 is deposited on the region not covered with the mask material 182 by the CVD method and a flattening process is performed. After that, a mask material 182 covering the entire element isolation region that is separated in the column direction is formed.
To remove.

After this, as shown in FIG. 11 (b),
On the surface of the conductive film formed on the bottom surface of the trench 156,
A gate contact 184 is formed by depositing a conductive material using a CVD method or the like.

By such a procedure, the trench groove 156 is formed adjacent to the gate 172 formed in the valley 152 in the element isolation region which is isolated in the column direction, and the trench 156 is formed.
A conductive film is formed on the bottom surface of the gate 172 so as to be connected to the gate 172, and a gate contact 184 is formed on the surface of the conductive film, so that the gate 172 formed at the minimum processing dimension F is separated.
Can be contacted.

The above-described embodiments are merely examples and do not limit the present invention. For example, various manufacturing conditions, film materials, and the like in the above-described manufacturing method can be changed and set as necessary.

[0049]

As described above, according to the semiconductor device and the method of manufacturing the same of the present invention, the surface portion of the semiconductor substrate is processed into a sawtooth shape having a periodic triangular shape, and one trough is used as a unit. It is possible to improve the degree of integration by forming one active element or forming an element region by using one trough as a unit.

[Brief description of drawings]

FIG. 1 is a vertical cross-sectional view showing a structure in which a MOSFET and an element isolation region are selectively formed on a surface portion of a semiconductor substrate processed into a sawtooth shape according to an embodiment of the present invention.

FIG. 2 is a vertical cross-sectional view showing, step by step, a procedure of processing the surface portion of the semiconductor substrate into a sawtooth shape in the method for manufacturing a semiconductor device according to the embodiment of the present invention.

FIG. 3 is an explanatory view showing a principle that the element area is reduced according to the same embodiment.

FIG. 4 is a plan view showing the steps of forming an element isolation region that is isolated in the column direction, step by step, in the method for manufacturing the semiconductor device according to the same embodiment;

FIG. 5 is a plan view showing a planar structure in the case where element isolation regions in a column direction are formed by the method for manufacturing a semiconductor device according to the same embodiment.

FIG. 6 is a vertical cross-sectional view showing the structure of a conventional MOSFET.

FIG. 7 is a CM of a semiconductor device according to an embodiment of the present invention.
FIG. 11 is a vertical cross-sectional view showing a configuration when applied to an OS circuit.

FIG. 8 illustrates a semiconductor device DR according to an embodiment of the present invention.
FIG. 3 is a vertical cross-sectional view showing a configuration when applied to AM.

FIG. 9 is a vertical cross-sectional view showing the steps of forming a gate contact according to the method for manufacturing a semiconductor device according to the embodiment of the present invention.

FIG. 10 is a vertical cross-sectional view showing steps of forming a gate contact by the method for manufacturing a semiconductor device according to the embodiment of the present invention.

FIG. 11 is a vertical cross-sectional view showing the steps of forming a gate contact according to the method for manufacturing a semiconductor device according to the embodiment of the present invention.

[Explanation of symbols]

1, 2, 11, 31, 41, 101, 130, 153
p-type semiconductor substrate 12, 21, 32, 42, 111, 112, 115, 1
16, 132, 133, 141, 142, 154 n-type impurity diffusion layer 13 silicon nitride film 14 resist film 15, 17 trenches 16, 23, 141, 155 silicon oxide film 22, 24 resist film 33, 151 peaks 34, 59 , 152 valley portion 51 n-type impurity diffusion layer (drain) 52 n-type impurity diffusion layer (source) 53, 113, 134, 143, 172 gates 55, 135, 137 n-type MOS transistors 56, 103, 114 element isolation region 58 144, 155, 157, 158, 183 Silicon oxide film 102 N well 104, 105 p-type impurity diffusion layer 121 Metal wiring layer 142 Polycrystalline silicon film 146 Bit line 156 Trench groove 161, 182 Mask material F Minimum processing size

─────────────────────────────────────────────────── --- Continuation of the front page (56) Reference JP-A-4-43677 (JP, A) JP-A-3-241872 (JP, A) JP-A-7-183499 (JP, A) JP-A-55- 65465 (JP, A) (58) Fields surveyed (Int.Cl. ⁷ , DB name) H01L 21/76 H01L 21/8238 H01L 27/092

Claims (8)

(57) [Claims] 1. A surface is processed into a sawtooth shape having a periodic triangular shape, and peaks and valleys extending in the column direction are alternately formed in the row direction. An active layer including a gate formed so as to extend in the column direction through an insulating film, and a source and a drain formed in each mountain portion along two side surfaces in the valley portion in which the gate is formed. An element and an insulator are formed by being embedded selectively in the row direction in the valley portion, and are respectively arranged between the two active elements or on two side surfaces of the valley portion along the row direction. A semiconductor device comprising: an element isolation layer that electrically isolates the impurity layers from each other. 2. The active element comprises a first conductivity type impurity diffusion layer formed in adjacent first and second crests and a first valley between the first and second crests. First-conductivity-type active element including a second-conductivity-type impurity diffusion layer formed in the trench and a first gate formed in the first valley along the column direction through the insulating film A second conductivity type impurity diffusion layer formed in the adjacent third and fourth peaks, and a first conductivity formed in the second valley between the third and fourth peaks. A second conductivity type active element including a second impurity type diffusion layer and a second gate formed in the second valley along the column direction via the insulating film. The semiconductor device according to claim 1. 3. A column direction in which an insulator is embedded deeper than the valleys in the valleys extending along the row direction on a sawtoothed surface having a periodic triangular shape. 2. The semiconductor device according to claim 1, further comprising an element isolation region. 4. The surface of the sawtoothed surface having a periodic triangular shape in order to increase the drive current and to reduce the area occupied by the active element in the direction of the drive current flowing in the active element. 2. The semiconductor device according to claim 1, wherein the semiconductor device is in the row direction. 5. The surface of a semiconductor substrate having an impurity diffusion layer formed on the surface thereof is processed into a sawtooth shape having a periodic triangular shape to separate the peak portion formed of the impurity diffusion layer and the impurity diffusion layer. A step of forming a trough, and a step of selectively forming a gate in a predetermined portion of the trough, wherein in the trough in which the gate is formed, peaks on both sides of the trough are formed. 2. The method for manufacturing a semiconductor device, wherein: the impurity diffusion layer and the gate form an active element, and a mountain portion where the gate is not formed is used as an element isolation region. 6. An impurity is introduced into a surface portion of a semiconductor substrate,
Forming an impurity diffusion layer, forming a mask material patterned on the surface of the impurity diffusion layer in a predetermined shape at predetermined intervals, and crystallizing the surface portion of the semiconductor substrate with the mask material as a mask. Isotropic etching is performed to dig a V-shaped groove deeper than the impurity diffusion layer, a step of filling the inside of the groove with a first insulating film, the mask material is removed, and the surface of the semiconductor substrate is removed. Exposing, and performing crystal anisotropic etching on the surface portion of the semiconductor substrate which is not covered with the first insulating film and whose surface is exposed,
A step of digging a V-shaped groove deeper than the impurity diffusion layer, a step of removing the first insulating film, and making a sawtooth semiconductor substrate in which peaks and valleys are periodically arranged at a predetermined interval. And a step of forming a second insulating film so as to cover the surface of the semiconductor substrate, and a gate on the second insulating film at a predetermined location selectively in the valley portion on the surface of the semiconductor substrate. A method of manufacturing a semiconductor device, comprising: 7. A step of forming a first resist film for isolating elements in the column direction on the surface of a semiconductor substrate having an impurity diffusion layer formed on the surface, and the step of covering with the first resist film. A step of digging a trench type groove so that the surface of the semiconductor substrate is exposed at the bottom surface in the surface portion of the semiconductor substrate which is not present; a step of filling the inside of the groove with a first insulating film; A step of removing the film, a step of forming a second resist film for processing the surface of the semiconductor substrate into a sawtooth shape having a periodic triangular shape in the row direction at predetermined intervals, the second resist Etching a surface portion of the semiconductor substrate not covered with a film, and digging a V-shaped groove deeper than the impurity diffusion layer so that the surface of the semiconductor substrate is exposed at the bottom surface; The inside of the groove is filled with an insulating film And a step of exposing the surface of the semiconductor substrate by removing the second resist film, and crystal anisotropy on the surface portion of the semiconductor substrate which is not covered with the insulating film and whose surface is exposed. Etching, and digging a V-shaped groove deeper than the impurity diffusion layer, and separated in the column direction by the trench-shaped groove,
A sawtooth semiconductor substrate in which ridges and valleys are periodically arranged at predetermined intervals in the row direction, and further, forming a second insulating film so as to cover the surface of the semiconductor substrate, And a step of selectively forming a gate on the second insulating film at a predetermined location in the valley on the surface of the semiconductor substrate. 8. A first trench groove is formed in which elements are isolated in the column direction and the inside is filled with a first insulating film, and the peaks and valleys are periodic at predetermined intervals in the row direction. In a surface portion of the semiconductor substrate which is arranged in a sawtooth shape having a shape, an impurity diffusion layer is formed in the peak portion and is separated from each other by a valley portion, in a region where the first trench groove is formed,
A step of digging a second trench groove deeper than the bottom surface of the valley portion adjacent to the valley portion forming the gate, and a step of forming a second trench groove on the surface of the peak portion and the valley portion of the semiconductor substrate not covered with the insulating film. Two
The step of forming an insulating film, the step of covering a predetermined valley portion of the valley portion where a gate is not formed with the first mask material, and the step of forming the valley portion not covered with the first mask material. And a bottom surface of the second trench groove adjacent to the valley portion to form a gate on the bottom surface of the valley portion and a gate on the bottom surface of the second trench groove. Forming a connected conductive film; removing the first mask material and forming a second mask material so as to cover the entire region where the first trench groove is formed; A step of depositing a third insulating film on a portion which is not covered with the mask material, performing a planarization process, and then removing the second mask material, and forming a third insulating film on the bottom surface of the second trench groove. The process of depositing a conductive material on the surface of the conductive film to form a gate contact. The method of manufacturing a semiconductor device characterized by comprising a, the.