JPS63232459A - Mos memory semiconductor device and manufacture thereof - Google Patents
Mos memory semiconductor device and manufacture thereofInfo
- Publication number
- JPS63232459A JPS63232459A JP62067385A JP6738587A JPS63232459A JP S63232459 A JPS63232459 A JP S63232459A JP 62067385 A JP62067385 A JP 62067385A JP 6738587 A JP6738587 A JP 6738587A JP S63232459 A JPS63232459 A JP S63232459A
- Authority
- JP
- Japan
- Prior art keywords
- region
- oxide film
- trench
- semiconductor substrate
- film
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 49
- 238000004519 manufacturing process Methods 0.000 title claims description 12
- 239000000758 substrate Substances 0.000 claims abstract description 42
- 239000003990 capacitor Substances 0.000 claims abstract description 39
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims abstract description 31
- 238000003860 storage Methods 0.000 claims abstract description 14
- 239000010409 thin film Substances 0.000 claims abstract description 4
- 238000002955 isolation Methods 0.000 claims abstract 2
- 239000010408 film Substances 0.000 claims description 120
- 150000004767 nitrides Chemical class 0.000 claims description 29
- 239000012535 impurity Substances 0.000 claims description 21
- 238000000034 method Methods 0.000 claims description 11
- 238000005530 etching Methods 0.000 claims description 7
- 238000000926 separation method Methods 0.000 claims description 2
- 230000001590 oxidative effect Effects 0.000 claims 2
- 230000015572 biosynthetic process Effects 0.000 claims 1
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 4
- 230000010354 integration Effects 0.000 description 4
- 230000003647 oxidation Effects 0.000 description 4
- 238000007254 oxidation reaction Methods 0.000 description 4
- 229910052710 silicon Inorganic materials 0.000 description 4
- 239000010703 silicon Substances 0.000 description 4
- 229910052698 phosphorus Inorganic materials 0.000 description 3
- 239000011574 phosphorus Substances 0.000 description 3
- VEXZGXHMUGYJMC-UHFFFAOYSA-N Hydrochloric acid Chemical compound Cl VEXZGXHMUGYJMC-UHFFFAOYSA-N 0.000 description 2
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 2
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 description 1
- 238000009825 accumulation Methods 0.000 description 1
- 229910052796 boron Inorganic materials 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 238000005868 electrolysis reaction Methods 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 238000005468 ion implantation Methods 0.000 description 1
- -1 phosphorus ions Chemical class 0.000 description 1
- 238000007790 scraping Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/86—Types of semiconductor device ; Multistep manufacturing processes therefor controllable only by variation of the electric current supplied, or only the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched
- H01L29/92—Capacitors with potential-jump barrier or surface barrier
- H01L29/94—Metal-insulator-semiconductors, e.g. MOS
- H01L29/945—Trench capacitors
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B12/00—Dynamic random access memory [DRAM] devices
- H10B12/01—Manufacture or treatment
- H10B12/02—Manufacture or treatment for one transistor one-capacitor [1T-1C] memory cells
- H10B12/03—Making the capacitor or connections thereto
- H10B12/038—Making the capacitor or connections thereto the capacitor being in a trench in the substrate
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B12/00—Dynamic random access memory [DRAM] devices
- H10B12/30—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
- H10B12/37—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells the capacitor being at least partially in a trench in the substrate
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明はＭＯＳ型メモリ半導体装置およびその製造方法
に関し、キャパシタ間の間隔を狭くしなから複数のキャ
パシタを適格に分離することができ、蓄積電荷のリーク
を招かずに高集積化を達成することができるＭＯＳ型メ
モリ半導体装置およびその製造方法に関する。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a MOS type memory semiconductor device and a method for manufacturing the same. The present invention relates to a MOS memory semiconductor device that can achieve high integration without causing charge leakage, and a method for manufacturing the same.
従来のＭＯＳ型メモリ半導体装置は半導体基板を蓄積電
荷容量側とし、半導体基板表面に不純物をドーピングし
た多結晶シリコンで容を電極を形成することにより容量
部を形成していた。In a conventional MOS type memory semiconductor device, a semiconductor substrate is used as a storage charge capacitor side, and a capacitor portion is formed by forming an electrode on the surface of the semiconductor substrate using polycrystalline silicon doped with impurities.
しかし、従来のＭＯＳ型メモリ半導体装置は半導体基板
側に電荷を蓄積させるため、キャパシタ間の間隔をある
程度までしか縮小することができず、そのため、高集積
化を達成する上で支障をきたすという欠点がある。However, because conventional MOS memory semiconductor devices accumulate charges on the semiconductor substrate side, the spacing between capacitors can only be reduced to a certain extent, which poses a problem in achieving high integration. There is.
本発明は上記に鑑みてなされたものであり、キャパシタ
間の間隔を狭くしなから複数のキャパシタを的確に分離
することができ、蓄積電荷のリークを招かずに高集積化
を達成するため、半導体基板に縦方向の溝を形成し、そ
の溝に多結晶シリコンを埋め込んで蓄積電荷領域とした
ＭＯＳ型メモリ半導体装置およびその製造方法を提供す
るものである。The present invention has been made in view of the above, and in order to be able to accurately isolate a plurality of capacitors without narrowing the interval between capacitors, and to achieve high integration without causing leakage of stored charges, The present invention provides a MOS type memory semiconductor device in which a vertical groove is formed in a semiconductor substrate, and polycrystalline silicon is buried in the groove to serve as a storage charge region, and a method for manufacturing the same.
本発明のＭＯＳ型メモリ半導体装置は
半導体基板に縦方向に形成された溝の底部より壁面に沿
って形成された前記半導体基板と逆導電型の容量電極領
域と、
一前記溝内に埋設されて前記容量電極領域と絶縁薄膜を
介して対向する多結晶シリコンの容量蓄積電極領域と、
前記容量電極領域と前記容量蓄積電極領域を電気的に分
離して電荷のリークを防ぐ分離領域を備え、
前記容量電極領域は隣接する溝型容量の容量電極領域と
電気的に接続されている。A MOS type memory semiconductor device of the present invention includes: a capacitor electrode region of a conductivity type opposite to that of the semiconductor substrate formed along the wall surface from the bottom of a trench vertically formed in the semiconductor substrate; a polycrystalline silicon capacitor storage electrode region facing the capacitor electrode region with an insulating thin film interposed therebetween; and a separation region that electrically separates the capacitor electrode region and the capacitor storage electrode region to prevent charge leakage; The capacitor electrode region is electrically connected to the capacitor electrode region of the adjacent groove-type capacitor.
また、本発明のＭＯＳ型メモリ半導体装置の製造方法は
半導体基板表面に酸化膜および窒化膜を形成し、前記窒
化膜をマスクとしてチャンネルストッパー領域およびフ
ィールド酸化膜を形成し、フィールド酸化膜以外の所定
の場所に溝を形成し、前記溝の底より略１／２の深さの
溝内壁の領域に隣接した溝の対応する領域に連続する前
記基板と逆導電型の不純物領域を形成し、前記溝内壁の
表面に容量絶縁膜を形成し、前記溝の底より略１／２の
深さの前記溝の内部に前記半導体基板と逆導電型の不純
物をドーピングした第１の多結晶シリコンを埋め、前記
溝の開口部より略１／４から１／２の深さの領域にチャ
ンネルストッパーとなる前記半導体基板と同導電型の不
純物領域を形成し、前記第１の多結晶シリコンで埋まっ
ていない領域の前記容量絶縁膜をエツチングし、前記溝
の開口部より略１／４から１／２の深さの領域に形成し
たチャンネルストッパー領域にフィールド酸化膜となる
酸化膜を形成し、前記溝の上部の略１／２に前記半導体
基板と逆導電型の不純物をドーピングした第２の多結晶
シリコンを埋め、前記半導体基板表面に形成した前記窒
化膜および前記酸化膜をエツチングした後前記第１及び
第２の多結晶シリコン層を容量蓄積電荷領域としてゲー
ト絶縁膜、ゲート電極およびソース・ドレイン領域を形
成するものである。Further, in the method for manufacturing a MOS type memory semiconductor device of the present invention, an oxide film and a nitride film are formed on the surface of a semiconductor substrate, a channel stopper region and a field oxide film are formed using the nitride film as a mask, and a predetermined region other than the field oxide film is formed. a groove is formed at the location, an impurity region of a conductivity type opposite to that of the substrate is formed continuous in a corresponding region of the groove adjacent to a region of the inner wall of the groove approximately 1/2 deep from the bottom of the groove; A capacitive insulating film is formed on the surface of the inner wall of the trench, and a first polycrystalline silicon doped with an impurity of a conductivity type opposite to that of the semiconductor substrate is filled inside the trench to a depth approximately 1/2 from the bottom of the trench. , an impurity region having the same conductivity type as the semiconductor substrate and serving as a channel stopper is formed in a region approximately 1/4 to 1/2 deep from the opening of the groove, and is not filled with the first polycrystalline silicon. The capacitor insulating film in the region is etched, and an oxide film to be a field oxide film is formed in the channel stopper region, which is formed at a depth of approximately 1/4 to 1/2 from the opening of the trench. A second polycrystalline silicon doped with an impurity of a conductivity type opposite to that of the semiconductor substrate is buried in approximately 1/2 of the upper part, and after etching the nitride film and the oxide film formed on the surface of the semiconductor substrate, the first and A gate insulating film, a gate electrode, and source/drain regions are formed using the second polycrystalline silicon layer as a capacitance storage charge region.
以下、本発明のＭＯＳ型／そり半導体装置をおよびその
製造方法に説明する。DESCRIPTION OF THE PREFERRED EMBODIMENTS The MOS type/warped semiconductor device of the present invention and its manufacturing method will be explained below.
第１図（ａ）、（ｂｌは本発明のＭＯＳ型メモリ半導体
装置の一実施例を示し、１はＰ型の半導体基板、４はチ
ャンネルストッパー領域、５はフィールド酸化膜、７は
容量電極、１０はチャンネルトソバー領域、１１は容量
絶縁膜、１３はフィールド酸化膜、１４は容量蓄積電荷
領域、１５はゲート酸化膜、１６はゲート電極、１７は
ソース・ドレイン領域であり、容量電極７は隣接するも
の同志で連続している。FIGS. 1A and 1B show an embodiment of the MOS type memory semiconductor device of the present invention, in which 1 is a P-type semiconductor substrate, 4 is a channel stopper region, 5 is a field oxide film, 7 is a capacitor electrode, 10 is a channel tosover region, 11 is a capacitor insulating film, 13 is a field oxide film, 14 is a capacitive storage charge region, 15 is a gate oxide film, 16 is a gate electrode, 17 is a source/drain region, and the capacitor electrode 7 is Adjacent items are continuous.
第１図（Ｃ）、（ｄｌは連続する容量電極７の一端にお
いて溝を形成し、そこに多結晶シリコン１８を埋め込ん
で容量電極コンタクトとしたものである。In FIG. 1C, (dl) is a groove formed at one end of the continuous capacitor electrode 7, and polycrystalline silicon 18 is buried therein to form a capacitor electrode contact.
第２図（ａｌ〜（１）は本発明のＭＯＳ型メモリ半導体
装置の製造方法の一実施例を示す。FIG. 2 (al-(1)) shows an embodiment of the method for manufacturing a MOS type memory semiconductor device of the present invention.
まず、Ｐ型Ｓｔ基板１表面に酸化膜２、窒化膜３を形成
し、周知の方法でチャンネルストッパー領域４、フィー
ルド酸化膜５を形成した後、所定の場所に溝６を形成す
る。−一一一−−・第２図（ａｌ
次に、溝の底部より略１／２の深さの溝内壁の領域に溝
の開口部の酸化膜２および窒化膜３の廂を利用して角度
を調節しなからリンをイオン注入し、隣接した溝６の対
応する領域とつながるようなＮ゛不純物領域（基板側容
量電極）７を形成する。−・−・−第２図（ｂ）ただし
、第２図（ａ）〜（１）では簡略化のため、隣接する溝
は省略している。隣接する溝とＮ゛不純物領域との関係
は第１図（ａｌ、（ｂ）で説明した。First, an oxide film 2 and a nitride film 3 are formed on the surface of a P-type St substrate 1, a channel stopper region 4 and a field oxide film 5 are formed by a well-known method, and then a groove 6 is formed at a predetermined location. -111--・Figure 2 (al) Next, by using the edges of the oxide film 2 and nitride film 3 at the opening of the trench, a region of the inner wall of the trench approximately 1/2 deep from the bottom of the trench is While adjusting the angle, phosphorus is ion-implanted to form a N impurity region (substrate side capacitance electrode) 7 that connects with the corresponding region of the adjacent trench 6. --- Figure 2 (b) However, in FIGS. 2(a) to (1), adjacent grooves are omitted for simplicity.The relationship between adjacent grooves and the N2 impurity region is explained in FIGS. 1(al) and (b). did.
次に、酸化膜、窒化膜、および酸化膜の三層構造からな
る絶縁膜８を溝内壁に形成し、リンをドーピングした多
結晶シリコンで溝６を埋める。次に、この多結晶シリコ
ンを溝の底部より略１／２の深さのところまで残す異方
性エツチングを施し、第１の多結晶シリコンＮ９を形成
する。次に、溝６の開口部より略１／４から１／２の深
さの領域に溝６の開口部の酸化膜２および窒化膜３の廂
を利用して角度を調整しなからボロンをイオン注入して
チャンネルストッパーとなるＰ°型不純物領域１０を形
成する。−−−一−−−第２図（Ｃ１次に、第１の多結
晶シリコンＪｉ９で埋まっていない領域の絶縁膜８をエ
ツチング除去し、酸化膜、窒化膜および酸化膜の三層構
造からなる容量絶縁膜１１を形成する。−−−−−−一
第２図＋ｄ）
次に、Ｐ゛型Ｓｌ基板１表面の窒化膜３および容量絶縁
膜１１の中の窒化膜をマスクにして溝６の開口部より略
１／２の深さの領域の溝内壁および第１の多結晶シリコ
ン９の表面に酸化膜１２を形成する。−・−第２図（ｅ
）次に、Ｐ＋型Ｓｉ基板１の表面の窒化膜３をマスクに
して酸化膜１２の溝開口部より略１／４の深さの領域及
び第１の多結晶シリコン９０表面の領域の酸化膜を異方
性エンチングで除去する。−一一一一一・第２図（ｆ）
次に、酸化膜１２をＳｉ基板１表面の窒化膜３をマスク
にしてバッフアート沸酸で等方性エツチングし、溝６の
開口部より略１／４から１／２の深さの領域にのみ酸化
膜を残し、フィールド酸化膜１３を形成する。−一一一
一一一第２図（ｇ１次に、溝６の開口部より略１／２の
深さの領域をＮ゛不純物をドーピングした第２の多結晶
シリコンで埋めＰ°型Ｓｔ基板１の表面の酸化膜２及び
窒化膜３をストッパーとして異方性エツチングを行い、
基板表面の多結晶シリコンを除去し、容量蓄積電荷領域
１４を形成する。−・−・−第２図（ｈ）
次にＰ゛型Ｓｉ基板１表面の酸化膜２及び窒化膜３をエ
ツチング除去し、周知の方法でゲート酸化膜１５、ゲー
ト電極１６、ソースドレイン領域１７を形成する＊ −
−−一第２図（１）また、セル周辺部において、周知の
方法で形成した溝の内壁にリンをイオン注入し、基板側
容量電極とＮ＋不純物領域を接続した後、溝をＮ゛不純
物をドーピングした多結晶シリコン１８で埋め、基板側
容量電極７とのコンタクトを形成する。−・・−・・第
２，１図（ａｌ （ｂｌ以後は、従来方法と同様の工程
を経て
ＭＯＳメモリ型集積回路を構成する。Next, an insulating film 8 having a three-layer structure of an oxide film, a nitride film, and an oxide film is formed on the inner wall of the trench, and the trench 6 is filled with polycrystalline silicon doped with phosphorus. Next, anisotropic etching is performed to leave this polycrystalline silicon to a depth approximately 1/2 from the bottom of the trench, thereby forming a first polycrystalline silicon N9. Next, using the edges of the oxide film 2 and nitride film 3 at the opening of the groove 6, boron is applied to a region approximately 1/4 to 1/2 deep from the opening of the groove 6, while adjusting the angle. A P° type impurity region 10 which will serve as a channel stopper is formed by ion implantation. ---1---Figure 2 (C1) Next, the insulating film 8 in the area not filled with the first polycrystalline silicon Ji9 is removed by etching to form a three-layer structure of an oxide film, a nitride film, and an oxide film. Form a capacitive insulating film 11.-------Fig. 2+d) Next, trenches 6 are formed using the nitride film 3 on the surface of the P'' type Sl substrate 1 and the nitride film in the capacitive insulating film 11 as masks. An oxide film 12 is formed on the inner wall of the trench and on the surface of the first polycrystalline silicon 9 in a region approximately 1/2 the depth of the opening. -・-Figure 2 (e
) Next, using the nitride film 3 on the surface of the P+ type Si substrate 1 as a mask, the oxide film is removed in a region approximately 1/4 deep from the trench opening of the oxide film 12 and in a region on the surface of the first polycrystalline silicon 90. is removed by anisotropic enching. -11111・Figure 2 (f)
Next, the oxide film 12 is isotropically etched with buffered hydrochloric acid using the nitride film 3 on the surface of the Si substrate 1 as a mask, to a region approximately 1/4 to 1/2 deep from the opening of the groove 6. A field oxide film 13 is formed by leaving only the oxide film. -11111 Fig. 2 (g1) Next, a region approximately 1/2 deep from the opening of the groove 6 is filled with a second polycrystalline silicon doped with N゛ impurity. Anisotropic etching is performed using the oxide film 2 and nitride film 3 on the surface of 1 as a stopper,
Polycrystalline silicon on the surface of the substrate is removed to form a capacitance storage charge region 14. - - - Fig. 2 (h) Next, the oxide film 2 and nitride film 3 on the surface of the P-type Si substrate 1 are removed by etching, and the gate oxide film 15, gate electrode 16, and source/drain region 17 are removed by a well-known method. form * −
--1 Figure 2 (1) In addition, in the cell periphery, phosphorus ions are implanted into the inner wall of the groove formed by a well-known method, and after connecting the substrate side capacitance electrode and the N+ impurity region, the groove is filled with Nₛ impurity. is filled with doped polycrystalline silicon 18 to form a contact with the substrate side capacitor electrode 7. -...Figure 2, 1 (al) After BL, a MOS memory type integrated circuit is constructed through the same steps as in the conventional method.
以上説明したように、本発明のＭＯＳ型メモリ半導体装
置およびその製造方法によれば半導体基板に縦方向の溝
を形成し、その溝に多結晶シリコンを埋め込んで蓄積電
荷領域としたため、キャパシタ間の間隔を狭くしなから
複数のキャパシタを的確に分離することができ、蓄積電
荷のリークを招くことなく高集積化を達成することがで
きる。As explained above, according to the MOS type memory semiconductor device and its manufacturing method of the present invention, vertical grooves are formed in the semiconductor substrate, and polycrystalline silicon is buried in the grooves to serve as storage charge regions. A plurality of capacitors can be accurately separated without narrowing the interval, and high integration can be achieved without causing leakage of stored charges.
第１図Ｃａｌ〜（Ｊｌ）は本発明のＭＯＳ型メモリ半導
体装置の一実施例を示し、第１図（ａｌおよび（ｂ）は
セル内の平面部及び断面図、第１図（Ｃ）および（ｄ弓
よ、Ｎ゛不純物領域で形成された基板側容量電極と外部
電極とのコンタクト部の断面図及び平面図である。第２
図（ａ）〜（１）は本発明のＭＯＳ型メモリ半導体装置
の製造方法の一実施例を工程順に示した断面図である。
符号の説明
１・・−−−−−Ｐ型シリコン基板
２・・・−酸化膜 ３−−−−−・−・窒化膜４−一
−−−・−・チャンネルストッパー５・−・−フィール
ド酸化膜 ６−・・−・溝７・−−−−ｍ−容量電
極（Ｎ＋不純物領域）８−・・〜絶縁膜（酸化膜、窒化
膜および酸化膜の三層構造）
９−・・−・−第１の多結晶シリコン
１０・−・−・チャンネルストッパー
１１・・・・・−・容量絶縁膜（酸化膜、窒化膜および
酸化膜の三層構造）
１２−・−酸化膜 １３・−一−−−・−・フィール
ド酸化膜１４−−−−−・−容量蓄積電荷領域
１５−・・・−ゲート酸化膜 １６・−・−ゲート
電極１７−・−・・−ソース・ドレイン領域１８−・−
−−ｍ−多結晶シリコン（容量電極コンタクト）７−・
−・・古漬電極（Ｎ・不純物領Ｊ或）１７・・・・−・
ソース・ドレインａ ＪＡ１８・・・・・−多結晶シリ
コン（容潰電掻コンタク第１図
（ｃ）
（ｄ）
１・・・−・・〜Ｐ型シリコン基板
２・・・・・−・酸化膜 ３〜・・−窒化膜４・・−
・・・・チャンネルストアパー５−・・・・・・フィー
ルド酸化膜 ６〜・−・−・溝７・・・−・・・容
量電極（Ｎ’不純物領域）第２図
（ａ） 。
１・・・・・−・・Ｐ型シリコン基板
２−・・・・・・酸化膜 ３・・・・・・・窒化膜４
−・・−・−・チャンネルストッパー５・−・−・・・
フィールド酸化１！Ｉ ６・−−−−ｍ−溝７−
・・・・・容量電極（Ｎ’不純物領域）８・・−・・・
絶縁膜（酸化膜、窒化膜および酸化膜の三Ｎ構造）
９−・・・・第１の多結晶シリコン
ｌＯ−・−・・・・チャンネルストッパー第２図
１−・・・−Ｐ型シリコン基板
２・−酸化＋１！Ｊ ３ ・・・・窒化膜４−・
・・・チャンネルストッパー
５・・−・・フィールド酸化膜 ６・−溝７−−一
容量電掻（Ｎ’不純鈍物域）
８−一一一・絶縁膜（酸化膜、窒化膜および酸化膜の三
層構造）
９− 第１の多結晶シリコン
１０−・・−チャンネルストッパー
１１−一・−容量絶縁膜（酸化膜、窒化膜および酸化膜
の三ＩＩ！構造）
１２−−〜酸化膜
第２図
（ｅ）
（ｆ）
１−−−Ｐ型ソリコン基（反
２− 酸化膜 ３・−・−窒化膜
４−−チャンネルストッパー
５ ・・フィールド酸化膜 ６−・・−溝７−・容
鼠電橿（Ｎ゛不純物領域）
８− 絶縁膜（酸化膜、窒化膜および酸化膜の三層構造
）
９− 第１の多結晶シリコン
１０ チャンネルストッパー
１１ ・容量絶縁膜（酸化膜、窒化膜および酸化膜の
三層構造）
１２−−・ 酸化＋１１１ １３ ・・−フィール
ド酸化膜１４・・−・容ｆｆｉ蓄積ＴＬ荷領域
第２図Figures 1 (Cal to Jl) show an embodiment of the MOS type memory semiconductor device of the present invention, Figures 1 (al and (b) are plane and cross-sectional views inside the cell, Figure 1 (C) and (d) A cross-sectional view and a plan view of a contact portion between a substrate-side capacitive electrode formed of an N impurity region and an external electrode.Second
Figures (a) to (1) are cross-sectional views showing one embodiment of the method for manufacturing a MOS type memory semiconductor device of the present invention in the order of steps. Explanation of symbols 1---P-type silicon substrate 2---Oxide film 3---Nitride film 4-1---Channel stopper 5---Field Oxide film 6-...-Groove 7-----m-Capacitor electrode (N+ impurity region) 8--...Insulating film (trilayer structure of oxide film, nitride film, and oxide film) 9-...- -First polycrystalline silicon 10--Channel stopper 11--Capacitive insulating film (three-layer structure of oxide film, nitride film, and oxide film) 12--Oxide film 13-- - Field oxide film 14 - Capacity storage charge region 15 - Gate oxide film 16 - Gate electrode 17 - Source/drain region 18 −・−
--m-Polycrystalline silicon (capacitance electrode contact) 7-・
--- Old pickled electrode (N/impurity area J or) 17 ---
Source/drain a JA18...-Polycrystalline silicon (electrolysis contact Fig. 1 (c) (d) 1...--P type silicon substrate 2...- Oxidation Film 3...-Nitride film 4...-
. . . Channel store aperture 5 - . . . Field oxide film 6 - . . . Groove 7 . . . Capacitor electrode (N' impurity region) Fig. 2 (a). 1...P-type silicon substrate 2-...Oxide film 3...Nitride film 4
−・・−・−・Channel stopper 5・−・−・・
Field oxidation 1! I 6・---m-groove 7-
...Capacitive electrode (N' impurity region) 8...
Insulating film (3N structure of oxide film, nitride film and oxide film) 9-...First polycrystalline silicon lO-...Channel stopper Fig. 21-...-P-type silicon Substrate 2 - oxidation +1! J3...Nitride film 4-...
...Channel stopper 5...Field oxide film 6.-Groove 7--Capacitance electric scraping (N' impurity dull region) 8-111.Insulating film (oxide film, nitride film, and oxide film 9--First polycrystalline silicon 10--Channel stopper 11--Capacitive insulating film (three-layer structure of oxide film, nitride film, and oxide film) 12---Oxide film No. Figure 2 (e) (f) 1--P-type solicon group (anti-2- oxide film 3--nitride film 4--channel stopper 5...field oxide film 6--groove 7--capacitor 8- Insulating film (three-layer structure of oxide film, nitride film, and oxide film) 9- First polycrystalline silicon 10 Channel stopper 11 - Capacitive insulating film (oxide film, nitride film, and oxide film) Three-layer structure of oxide film) 12--・Oxidation +111 13...-Field oxide film 14...Capacity ffi accumulation TL load area Fig. 2
Claims (5)
型メモリ半導体装置において、 半導体基板に縦方向に形成された溝の底部 より壁面に沿って形成された前記半導体基板と逆導電型
の容量電極領域と、前記溝内に埋設されて前記容量電極
領域と絶縁薄膜を介して対向する多結晶シリコンの容量
蓄積電極領域と、 前記容量電極領域と前記容量蓄積電極領域 を電気的に分離して電荷のリークを防ぐ分離領域を備え
、 前記容量電極領域は隣接する溝型容量の容 量電極領域と電気的に接続されていることを特徴とする
ＭＯＳ型メモリ半導体装置。(1) MOS that stores information based on the amount of charge in the trench type capacitor
type memory semiconductor device, a capacitor electrode region of a conductivity type opposite to that of the semiconductor substrate is formed along a wall surface from the bottom of a trench vertically formed in the semiconductor substrate, and a capacitor electrode region is buried in the trench. a polycrystalline silicon capacitor storage electrode region facing the capacitor electrode region with an insulating thin film interposed therebetween; and a separation region for electrically separating the capacitor electrode region and the capacitor storage electrode region to prevent charge leakage; A MOS type memory semiconductor device, characterized in that the device is electrically connected to a capacitor electrode region of an adjacent trench type capacitor.
に沿って設けられたチャンネルストッパ領域および比較
的厚膜のフィールド酸化膜から構成される特許請求の範
囲第１項の ＭＯＳ型メモリ半導体装置。(2) The MOS type memory semiconductor according to claim 1, wherein the isolation region comprises a channel stopper region provided along the wall surface of the trench without the insulating thin film and a relatively thick field oxide film. Device.
前記窒化膜をマスクとしてチャンネルストッパー領域お
よびフィールド酸化膜を形成し、フィールド酸化膜以外
の所定の場所に溝を形成し、前記溝の底より略１／２の
深さの溝内壁の領域に隣接した溝の対応する領域に連続
する前記半導体基板と逆導電型の不純物領域を形成し、
前記溝内壁の表面に容量絶縁膜を形成し、前記溝の底よ
り略１／２の深さの前記溝の内部に前記半導体基板と逆
導電型の不純物をドーピングした第１の多結晶シリコン
を埋め、前記溝の開口部より略１／４から１／２の深さ
の領域にチャンネルストッパーとなる前記半導体基板と
同導電型の不純物領域を形成し、前記第１の多結晶シリ
コンで埋まっていない領域の前記容量絶縁膜をエッチン
グし、前記溝の開口部より略１／４から１／２の深さの
領域に形成したチャンネルストッパー領域にフィールド
酸化膜となる酸化膜を形成し、前記溝の上部の略１／２
に前記半導体基板と逆導電型の不純物をドーピングした
第２の多結晶シリコンを埋め、前記半導体基板表面に形
成した前記窒化膜および前記酸化膜をエッチングした後
前記第１及び第２の多結晶シリコン層を容量蓄積電荷領
域としてゲート絶縁膜、ゲート電極およびソース・ドレ
イン領域を形成することを特徴とするＭＯＳ型メモリ半
導体装置の製造方法。(3) Forming an oxide film and a nitride film on the surface of the semiconductor substrate,
A channel stopper region and a field oxide film are formed using the nitride film as a mask, and a trench is formed at a predetermined location other than the field oxide film, adjacent to a region of the inner wall of the trench approximately 1/2 deep from the bottom of the trench. forming an impurity region of a conductivity type opposite to that of the semiconductor substrate that is continuous in a region corresponding to the groove;
A capacitive insulating film is formed on the surface of the inner wall of the groove, and a first polycrystalline silicon doped with an impurity of a conductivity type opposite to that of the semiconductor substrate is placed inside the groove at a depth approximately 1/2 from the bottom of the groove. an impurity region having the same conductivity type as the semiconductor substrate and serving as a channel stopper is formed in a region approximately 1/4 to 1/2 deep from the opening of the trench, and is filled with the first polycrystalline silicon; The capacitor insulating film is etched in the area where the capacitive insulating film does not exist, and an oxide film to be a field oxide film is formed in a channel stopper region formed at a depth of approximately 1/4 to 1/2 from the opening of the trench. Approximately 1/2 of the top of
A second polycrystalline silicon doped with an impurity of a conductivity type opposite to that of the semiconductor substrate is buried in the semiconductor substrate, and the nitride film and the oxide film formed on the surface of the semiconductor substrate are etched, and then the first and second polycrystalline silicon are etched. A method for manufacturing a MOS type memory semiconductor device, characterized in that a gate insulating film, a gate electrode, and a source/drain region are formed using a layer as a capacitance storage charge region.
化膜の三層構造の膜を形成することを特徴とする特許請
求の範囲第３項のＭＯＳ型メモリ半導体装置の製造方法
。(4) The method for manufacturing a MOS type memory semiconductor device according to claim 3, wherein the capacitor insulating film is formed by forming a film having a three-layer structure of an oxide film, a nitride film, and an oxide film.
半導体基板上に形成された前記窒化膜をマスクとして酸
化を行い、前記溝の開口部より略１／２の深さの領域の
溝内壁に酸化膜を形成した後、前記半導体基板上の前記
窒化膜をマスクとして前記溝の開口部より略１／２の深
さの領域の溝内壁に形成した前記酸化膜を異方性エッチ
ングした後等方性エッチングすることによって形成する
ことを特徴とする特許請求の範囲第４項のＭＯＳ型メモ
リ半導体装置の製造方法。(5) Formation of the oxide film that will become the field oxide film is carried out by oxidizing the nitride film formed on the semiconductor substrate as a mask, and oxidizing the inner wall of the trench in a region approximately 1/2 deep from the opening of the trench. After forming an oxide film on the semiconductor substrate, using the nitride film on the semiconductor substrate as a mask, anisotropically etching the oxide film formed on the inner wall of the trench in a region approximately 1/2 deep from the opening of the trench. 5. The method of manufacturing a MOS type memory semiconductor device according to claim 4, wherein the MOS type memory semiconductor device is formed by isotropic etching.
Priority Applications (4)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP62067385A JPS63232459A (en) | 1987-03-20 | 1987-03-20 | Mos memory semiconductor device and manufacture thereof |
| EP88104391A EP0283964B1 (en) | 1987-03-20 | 1988-03-18 | Dynamic random access memory device having a plurality of improved one-transistor type memory cells |
| DE3851649T DE3851649T2 (en) | 1987-03-20 | 1988-03-18 | Dynamic random access memory device composed of a plurality of single transistor cells. |
| US07/171,094 US4969022A (en) | 1987-03-20 | 1988-03-21 | Dynamic random access memory device having a plurality of improved one-transistor type memory cells |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP62067385A JPS63232459A (en) | 1987-03-20 | 1987-03-20 | Mos memory semiconductor device and manufacture thereof |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS63232459A true JPS63232459A (en) | 1988-09-28 |
Family
ID=13343480
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP62067385A Pending JPS63232459A (en) | 1987-03-20 | 1987-03-20 | Mos memory semiconductor device and manufacture thereof |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS63232459A (en) |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0567749A (en) * | 1991-09-09 | 1993-03-19 | Toshiba Corp | Semiconductor memory device and manufacture thereof |
| JP2004153250A (en) * | 2002-10-30 | 2004-05-27 | Internatl Business Mach Corp <Ibm> | Memory cell and its forming method |
| KR100560647B1 (en) * | 1997-09-30 | 2006-05-25 | 인터내셔널 비지네스 머신즈 코포레이션 | Reduced parasitic leakage in semiconductor devices |
-
1987
- 1987-03-20 JP JP62067385A patent/JPS63232459A/en active Pending
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0567749A (en) * | 1991-09-09 | 1993-03-19 | Toshiba Corp | Semiconductor memory device and manufacture thereof |
| KR100560647B1 (en) * | 1997-09-30 | 2006-05-25 | 인터내셔널 비지네스 머신즈 코포레이션 | Reduced parasitic leakage in semiconductor devices |
| JP2004153250A (en) * | 2002-10-30 | 2004-05-27 | Internatl Business Mach Corp <Ibm> | Memory cell and its forming method |
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