JP3071278B2 - Semiconductor device and manufacturing method thereof - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a semiconductor device and a method of manufacturing the same, and more particularly, to a dynamic RAM (DRAM) having a trench capacitor structure.

[0002]

2. Description of the Related Art In recent years, semiconductor memory devices have been steadily becoming higher in integration and larger in capacity.
In a MOS dynamic RAM (DRAM) composed of a plurality of MOS capacitors, research on miniaturization of the memory cell is progressing.

With the miniaturization of such memory cells, the area of a capacitor for storing information (charge) is reduced. As a result, the memory contents are erroneously read or the memory contents are destroyed by α rays or the like. Soft errors are a problem.

As a method for solving such a problem and achieving high integration and large capacity, the occupied area of the capacitor is substantially increased without increasing the occupied area, and the capacitor capacity is increased and stored. Various methods have been proposed to increase the charge amount.

One of them is a DRAM having a trench capacitor structure as described below. This DRAM is shown in FIG.
4 (a) and 4 (b) show a plan view and a sectional view, respectively, so that a groove (trench) 5 (5
_1, 5 ₂ ...) is formed, on the inner wall of the trench 5 n-
A mold layer 6 (6 ₁ , 6 ₂ ...) Is formed, and a capacitor insulating film 7 and a plate electrode 8 are sequentially buried on the surface thereof to form a capacitor so that the capacitor area can be increased without increasing the element size. Things.

That is, in this structure, the source or drain region 11 (consisting of the n-type layer) is formed in the element region separated by the element isolation field oxide film 3 formed on the surface of the p-type silicon substrate. 11 ₁ , 11 ₂ ...), 12
(12 ₁ , 12 ₂ ...) And a gate electrode 10 (10 ₁ , 10 ₂ ) formed therebetween through a gate insulating film 9.
..), And a source or drain region 12 (12 ₁ , 12 ₂ ...) Disposed on the inner wall of the adjacent trench 5 and made of this n-type layer.
Forming a MOS capacitor comprising an n @--type layer 6 connected to the substrate, a capacitor insulating film 7 formed on the surface of the n @--type layer 6, and a plate electrode 8 embedded in the trench. It is.

In such a structure, since the inner wall of the groove is used as a MOS capacitor, the capacitance of the capacitor is reduced.
It can be increased several times as compared with the conventional structure. Therefore, with such a configuration, it is possible to prevent a decrease in the amount of stored charges even if the occupied area of the memory cell is reduced, and it is possible to obtain a small-sized DRAM having a large storage capacity.

However, in this structure, the distance between the trenches 5 _1, 5 ₂ of adjacent memory cells is shortened,
The stored information charges are likely to be lost due to punch-through, and errors may occur in the data.

[0009] This is, for example, one of the trenches 5 ₁ side of the n- type layer ₆₁ to the information stored charge, the other of the trench 5
When ₂ of the n- type layer 6 ₂ stored is information charges of 0,
n- type layer 6 ₁ of the information charge appears as a phenomenon of moving to the other of the n- type layer 6 _2. And, as the depth of the trench becomes deeper, the diffusion length of the n − -type layer 6 in the horizontal direction becomes larger, so that the distance between the substantially adjacent n − -type layers becomes shorter,
This phenomenon is more likely to occur. For this reason, for example, a depth of 5 μm
In the case of forming a trench of m, it was extremely difficult to make the trench interval substantially 1.5 μm or less.

[0010] This is a major problem which hinders further high integration of the DRAM.

As a method for solving this problem, as shown in FIGS. 35, 36 (a) and (b) (FIG. 36 (a) is a sectional view taken along the line AA of FIG. (b) is a cross-sectional view taken along the line BB of FIG. 35), and a structure has been proposed in which a storage node electrode 6S, a capacitor insulating film 7, and a plate electrode 8 are sequentially formed on the inner wall of the trench 5 via an insulating film 20 to form a capacitor. (JP-A-61-67954). Here, reference numeral 21 denotes an n-type layer for connecting the storage node electrode 6S to the n-type layer 11 constituting the source / drain region, and reference numeral 31 denotes a bit line.

In this structure, the inner wall of the trench is formed by the insulating film 20.
In order to be covered, even by reducing the trench distance, n- -type layer 6 _1, 6 does it up for leakage due to the punch-through between the _two, as the structure shown in FIG. 34.

However, an n-type layer 21 formed on a part of the inner wall of the groove for connecting storage node electrode 6S and n-type layer 11 constituting the source / drain region is provided.
And the element region of the adjacent cell (source / drain region 12)
Between them, there is a possibility that a leak will occur.

In order to connect this n-type layer 21 and storage node electrode 6S, insulating film 20 on the inner wall of the trench is formed.
When patterning the storage node contact 42 formed in a part of the storage node contact, it is necessary to form the hole so as to have a very small hole, and there is a large problem of leakage due to misalignment.

Further, in such a cell structure, the step of the plate electrode may cause disconnection of a word line, a bit line or the like after the plate electrode is formed. Further, if the thickness of the plate electrode is reduced in order to reduce the step of the plate electrode, there is a problem that the resistance increases.

[0016]

As described above, in the conventional trench-type capacitor structure, the n-type layer 21 for connecting the storage node electrode 6S and the n-type layer 11 forming the source / drain region is formed. Since the leakage may occur between the element region (source / drain region 12) of the adjacent cell, the distance t between the storage node contact and the adjacent element region cannot be sufficiently reduced. There was a problem.

[0017] Also, for this reason, patterning of the storage node contact requires very strict resolution and alignment.

The present invention has been made in view of the above circumstances, and when further miniaturizing the element area, an n-type layer for a storage node contact and an element region (source / drain region) of an adjacent cell are required. To prevent leaks during
An object of the present invention is to provide a highly reliable trench capacitor structure.

Further, with further miniaturization, the area occupied by the memory cell is reduced, and in the element isolation by the LOCOS method, there is a limit to the reduction of the area required for the element isolation, which makes the isolation difficult. However, the isolation method using a trench has a problem that it is difficult to isolate a storage node electrode formed of polycrystalline silicon for each cell. In addition, the demand for reduction of the element isolation area in such miniaturization has been the same not only in the cell region but also in peripheral circuits. Furthermore, since the plate electrode is formed so as to reach the surface of the substrate, this step causes disconnection of a word line, a bit line and the like after the plate electrode is formed.

A second object of the present invention is to provide a DRAM capable of separating a storage node electrode for each cell by using trench isolation in view of these points. Another object of the present invention is to provide a cell structure having a flat surface while miniaturizing an element isolation region of a peripheral circuit.

[0021]

Therefore, in a first aspect of the present invention, a so-called SOI substrate having a silicon layer formed on a silicon oxide film is used, and a groove is formed in the silicon oxide film to form, for example, a checkered column. Is formed, and a capacitor is formed below the boundary between the silicon layer and the silicon oxide layer of the pillar.

In a second aspect of the present invention, a trench is formed while leaving an island region serving as an element region, and the trench is filled with polycrystalline silicon so as not to be completely buried, and a capacitor is formed in the recess. In addition, a gate electrode is buried in a trench dug in the element region to planarize the element region, and an electrode for connecting the storage node electrode and a diffusion layer as a source / drain is formed in a self-aligned manner with the gate electrode. Like that.

According to a third aspect of the present invention, a trench is formed while leaving an island region serving as an element region. Of these trenches, the one used for element isolation is completely filled with polycrystalline silicon. A capacitor is formed in a self-aligned manner in this recess so that the insulating film sandwiched between the storage node electrode on the plate electrode and the substrate element region is replaced with an LPD, low-stress nitride film, or LPCVD. It is formed of an LPCVD insulating film such as silicon.

[0024]

According to the first structure, for example, the cell size can be reduced by arranging checker-like element regions, and the capacitor region can be increased. Further, since the capacitor is formed in the groove, the flatness is high and the wiring processing is easy.

Further, since the SOI substrate is used as a starting material, the structure is strong against soft errors because the silicon layer is thin and the charge induced by α rays is small.

Further, according to the second structure, since the gate electrode is formed in the recess, the short channel effect is suppressed and miniaturization is facilitated. Further, since the gate electrode is buried, the upper surface of the silicon pillar after the gate electrode is formed is flat, and the storage node contact can be formed in a self-aligned manner, and the contact area can be increased.
Further, according to the third aspect of the present invention, since a low-stress film by deposition is used as the insulating film, damage to the substrate element region can be prevented as compared with the insulating film due to oxidation of the plate, and junction leakage of the MOSFET can be prevented. be able to. That is, when a silicon oxide film is formed by thermally oxidizing the surface of a polycrystalline silicon film, the volume is expanded, so that a silicon column is put on and a defect is easily generated, and a defect due to a storage node or a plate is easily generated. However, such a problem can be overcome by using a low stress film such as LPD.

[0027]

Embodiments of the present invention will be described below in detail with reference to the drawings.

Embodiment 1 A DRAM having a trench structure will be described as a first embodiment of the semiconductor memory device of the present invention. FIGS. 1, 2 (a) and 2 (b) are plan views showing a DRAM having a trench structure, and FIG.
A B sectional view and a CD sectional view are shown.

In this DRAM, a groove 105 is formed in an SOI substrate 101 on which a silicon layer 101s having a thickness of several tens to several hundreds nm is formed, and columnar protrusions having a height of 3 to 4 μm are left in a checkered pattern. Arrange this silicon layer 10
A plate electrode 108 is formed below 1 s so as to surround the silicon oxide columnar portion, and a storage node electrode 106 is embedded between the checkered corners surrounded by the plate electrode via a capacitor insulating film 107 to form a capacitor. On the other hand, a MOSFET is formed above the columnar protrusion. The MOSFET is formed on the upper surface of the silicon layer, and one of the source / drain regions covers the side wall of the silicon layer. , Which is connected to the storage node electrode 106. A bit line 113 is connected to a surface facing the storage node contact via a bit line contact.

The other parts have the same structure as a normal DRAM.

That is, the gate insulating film 109 is formed on the upper surface of the island-shaped columnar protrusion separated by forming the trench 105 in the substrate having the silicon layer formed on the surface with the silicon oxide film interposed therebetween. And a drain or source region 111 composed of an n-type layer formed so as to be self-aligned with each gate electrode.
In addition, a MOSFET is formed with the gate electrode 112 and the source or drain region 112 formed of the n-type layer is connected to the source or drain region 112 via a storage node contact and a connection electrode 114 formed on an insulating film as a side wall 117 covering an upper side wall of the columnar projection. The storage node electrode 106
Is connected. The other n-type layer 111 is connected to the bit line 113.

The gate electrodes 110 are continuously arranged in one direction of the memory cell matrix to form a word line.

The upper layer of the element region thus formed is a silicon oxide film 1 formed by the CVD method.
19 and a BPSG film 120 as a flattening layer, and a bit line 113 connected to the n-type layer via a contact hole is provided above this.

Next, the manufacturing process of this DRAM will be described.

In each of the figures during the manufacturing process, (a) and
2B shows a cross section corresponding to FIGS. 2A and 2B.

First, as shown in FIGS. 3A and 3B,
A silicon oxide film 1 with a thickness of about 4 μm on the surface of the silicon substrate
After forming an SOI substrate by forming a silicon layer 101s having a thickness of 50 to 100 nm, a silicon oxide film 40 having a thickness of 20 to 30 nm and a thickness of 5
A silicon nitride film 40 having a thickness of 0 to 100 nm is sequentially deposited, and a trench 105 is formed by anisotropic etching using the resist pattern R as a mask, leaving an island region 151 serving as an element region on the substrate surface.

Then, the side surface of the silicon layer above the silicon columnar projections is oxidized by a thermal oxidation method to form a silicon oxide film 117s having a thickness of 80 nm, and a polycrystalline silicon film as a plate electrode 108 is deposited, and the entire surface is exposed to a groove. The plate electrode is processed by the CDE method while leaving the resist pattern inside.

Then, the upper portion of the plate electrode is selectively oxidized by leaving the silicon nitride film below the plate electrode to form an NO film as the capacitor insulating film 107 and bury the polycrystalline silicon film as the storage node electrode 106 (FIG. 4). (a) and (b)).

Then, after removing the NO film other than the capacitor region, a CVD oxide film of about 100 nm is deposited, the second polycrystalline silicon film 106s having the side wall 117 formed therein is buried by RIE, and the upper portion is oxidized to oxidize the silicon oxide film 119. Is formed (FIGS. 5A and 5B).

After that, as shown in FIGS. 6A and 6B, the silicon nitride film 50 and the silicon oxide film 40 used as the etching mask are removed by etching, and the gate insulating film 109 made of the silicon oxide film, the polycrystalline silicon are removed. After simultaneously patterning a gate electrode 110 made of a silicon film and an upper insulating film made of a silicon nitride film 124, a sidewall 124s made of a silicon nitride film is formed, and diffusion layers 111 and 112 to be source / drain regions are formed by diffusion. .

Further, the side wall 124s of the storage node contact region is removed by RIE etching to expose the diffusion layer 112 and the storage node electrode 106, and a polycrystalline silicon film is buried between the gate electrodes and patterned to form a connection electrode 114. . After this BP
An SG film 120 is formed and flattened, a bit line direct contact is opened, and a bit line 113 is formed. Thus, the DRAM shown in FIGS. 1 and 2 is completed.

The fine and highly reliable D
A RAM can be formed. As a modification of the above-described embodiment, as shown in FIGS. 7A and 7B, the connection between the storage node electrode and the diffusion layer 112 is made on the side wall of the columnar body by the second polysilicon layer 106s. It may be. Other parts are formed in the same manner as in the above embodiment.

Although the SOI substrate is used as a starting material in the above embodiment to form an island region by forming a trench, an insulating film and a silicon layer are selectively grown on the substrate surface to form the island region. By doing so, a similar structure can be obtained.

Embodiment 2 FIGS. 8 and 9A show a second embodiment of the present invention.
(b) shows a DRAM having a trench structure. Fig. 9 (a) and
(b) corresponds to the cross-sectional view taken along the line AB and the line CD in FIG.

In this example, the island region 251 serving as the MOSFET formation region is brought close to the edge portion so as to draw a "checkerboard pattern", and a polycrystalline silicon film is buried around these to perform element isolation. A capacitor is formed in a recess formed by the above process, and the gate electrode 210 is buried in a trench Tg dug in the element region.
The surface of the element region is planarized, and the gate electrode 210 is formed.
Electrode 21 for connecting storage node electrode 206 and diffusion layer 212 as a source / drain in a self-aligned manner
4 is formed.

In this example, the checkered corners are separated by setting the exposure time longer than the standard.

That is, a trench 205 is formed on the surface of a p-type silicon substrate 201 so as to leave an island-shaped region serving as an element region 251 in a checkered pattern, and a plate electrode 208 is formed in the trench via a silicon oxide film 203a. Is formed integrally, and a storage node electrode 206 made of a polycrystalline silicon film is buried in an upper layer with a capacitor insulating film 207 interposed therebetween. At this time, since the edge portion of the element region 251 is buried by the silicon oxide film 203a or the plate electrode 208 in the vicinity thereof, the storage node electrode 206 formed inside the silicon oxide film 203a is formed.
Are formed in an individually separated state. Therefore, only in the necessary area, the connection electrode 214 made of a polycrystalline silicon film is used.
With this, the surface is connected to the source / drain region 212 of the NOSFET in the island region. For other parts, normal DRA
It has the same structure as M.

Next, the manufacturing process of this DRAM will be described.

In each drawing during this manufacturing process, FIG.
Is shown. First, specific resistance 5Ωcm
On the surface of the p-type silicon substrate 201, a silicon nitride film S1 serving as a trench mask and a silicon oxide film S2 are formed.
A trench 205 is formed by forming a layer film pattern and using the mask as a mask by anisotropic etching, leaving an island region 251 in a checkered pattern. Then, a silicon oxide film 203a having a thickness of 80 nm is formed on the inner wall of the trench by a thermal oxidation method.

After that, a polycrystalline silicon film 208 as a plate electrode is deposited so that the region where the edge portion of the island region is close is completely buried. The trench bottom is filled with a resist and anisotropically etched to remove the surface polycrystalline silicon film while leaving the polycrystalline silicon film on the side walls. Then, after the surface is oxidized to form a thin silicon oxide film S3, the inside of the trench is covered and protected with a silicon nitride film, and a silicon oxide film 217 is selectively formed on the inner wall of the trench near the trench opening.

After doping by arsenic or phosphorus ion implantation into the plate electrode,
A capacitor insulating film 207 composed of a two-layer film of a silicon nitride film / silicon oxide film is formed, and a phosphorus-doped polycrystalline silicon film is deposited and etched back to bury the storage node electrode 206 in the trench. Then, the surface of the storage node electrode is further oxidized to form a silicon oxide film 2.
29 are formed. Next, the capacitor insulating film 2 on the element region
07 is removed by etching, and an opening is formed in the two-layer film pattern used as the trench mask and the silicon oxide film 229 on the surface of the storage node electrode. Using this as a mask, the trench T for forming the gate electrode is formed by anisotropic etching.
g is formed (FIG. 10) Thereafter, the storage node electrode 206 is formed by low-temperature oxidation.
The silicon oxide film 237 is formed again thereon. Thereafter, a gate insulating film 209 is formed, and a polycrystalline silicon film 210 serving as a gate electrode is buried in the trench Tg. Then, arsenic is diffused to form n-type diffusion layers 211 and 212, and the surface is oxidized to a thickness of 50 nm. Silicon oxide film 224 of about 100 nm
Are sequentially formed on the entire surface (FIG. 11).

Thereafter, as shown in FIG. 12, a part of the silicon oxide film 237 on the upper surface of the storage node is selectively removed by photolithography, and a storage node contact is formed to form a polycrystalline silicon film doped with arsenic. Is formed. Thereafter, the upper portion and side walls of connection electrode 214 are covered with silicon nitride film 238 (FIG. 12).

Thereafter, the exposed portion of the storage node electrode is covered with a silicon oxide film by oxidation, and the surface is flattened with a BPSG film 220. Then, a bit line contact is formed to form a bit line 213. The DRAM shown in 8 and 9 is completed.

The gate electrode thus formed is
Since it is formed in the recess, the short channel effect is suppressed and miniaturization is facilitated. Further, the upper surface of the silicon pillar after the formation of the gate electrode is flat, the storage node contact can be formed in a self-aligned manner, and the contact area can be increased.

Although the trench Tg for forming a gate is formed in both the silicon pillar and the upper layer of the storage node electrode in the above embodiment, the trench for forming a gate is formed only in the silicon pillar as shown in FIG. Tg is formed, and a gate electrode 210 is formed therein. A connection electrode 214 for connecting the storage node electrode and the gate electrode is formed in the embedded gate in a self-aligning manner. The second word line 210s may be buried consistently. This second word line 210s
Are connected to the gate electrode 210 to form a word line wiring portion.

FIGS. 15 to 22 are views showing the manufacturing process.

First, trenches 5 are formed on the surface of a p-type silicon substrate 1 having a specific resistance of about 5 Ωcm by anisotropic etching in the same manner as in the above embodiment, leaving island regions 51 in a checkered pattern. Two-layer film pattern S1 S used for trench formation
A capacitor is formed in the same manner as in the above-mentioned embodiment while leaving 2 as it is (FIG. 15).

Next, an opening is formed in the two-layer film pattern used as a trench mask, and a trench Tg for forming a gate electrode is formed by anisotropic etching using the opening as a mask (FIG. 16). Then, a polycrystalline silicon film 210 to be a gate electrode is buried in the trench Tg (FIG. 17).

Thereafter, the surface is oxidized to a film thickness of 50 to 100.
A silicon oxide film 224 of about nm is sequentially formed on the entire surface, and anisotropic etching is performed through the resist pattern R by photolithography as shown in FIG. 18 to expose the storage node electrode 206 and the surface of the silicon pillar (FIG. 19). ).

Thereafter, as shown in FIG. 20, the resist pattern R is removed to form a connection electrode 214 made of an arsenic-doped polycrystalline silicon film, and the top and side walls of the connection electrode are covered with a silicon nitride film 244. Then, an opening is formed in the insulating film 224 on the gate.

Then, as shown in FIG. 21, a polycrystalline silicon film 210s is formed on the entire surface of the substrate, and a silicon nitride film 244s is further formed thereon.

Thereafter, the polysilicon film 210s is patterned together with the silicon nitride film 244s to form a second word line, and the silicon nitride film 244s
BPSG film 220 is formed, the surface is flattened, and a bit line contact is formed to form a bit line 21.
Form 3

As a modification, as shown in FIG. 23, in order to further planarize, the substrate surface on the storage node contact side is set to be one level lower than the substrate surface on the bit line contact side.
You may make it lower about 00 nm. This structure is formed by RIE or LOCOS prior to the trench opening.
This can be easily realized by keeping the substrate surface low using the method.

As a third embodiment of the present invention, FIGS. 24, 25A and 25B are a plan view, an AB sectional view and a CD sectional view showing a DRAM having a trench structure.

In this example, a silicon oxide film covering the upper layer of the polycrystalline silicon film buried in the element isolation region is formed by the LPD method to form a low-stress insulating film to suppress the stress on the silicon pillar. It is characterized by the following.

That is, trenches 305 are formed vertically and horizontally on the surface of the p-type silicon substrate 301 so as to leave an island-shaped region serving as the element region 351, and the trench 305 is formed to be wider in a region serving as a capacitor. Trench 305
A polycrystalline silicon film 323 is buried therein via a silicon oxide film 303a, and the surface thereof is insulated by a silicon oxide film 324 formed by the LPD method to form an element isolation region, which is wide. A hole is formed in the region without being completely buried, and the hole is widened so that a capacitor is formed in the hole.

As described above, a MOSFET is formed in the island-shaped element region 351 separated by the element isolation region formed by filling the trench 305, and a wide region 305c of the trench 305 is formed.
A plate electrode 308 made of a polycrystalline silicon film, and a capacitor insulating film 3 made of a two-layer film of a silicon nitride film / silicon oxide film formed on the surface of the plate electrode 308
07 and a storage node electrode 306 made of a polycrystalline silicon film embedded in the trench.
An S capacitor is formed.

Next, the manufacturing process of this DRAM will be described.

In each drawing during this manufacturing process, (a) and
(b) shows a cross section corresponding to (a) and (b) of FIG.

First, after an oxide film 301s is formed on the surface of a p-type silicon substrate 301 having a specific resistance of about 5 Ωcm, a silicon nitride film S1 and a silicon oxide film S2 serving as a trench mask are formed.
And a two-layer film pattern is formed as a mask, and anisotropic etching is performed using this as a mask to leave the trench 3
05 (FIGS. 26A and 26B). Here, the trench is formed to be wide in a region to be a capacitor.

After a silicon oxide film 303a having a thickness of 80 nm is formed on the inner wall of the trench by a thermal oxidation method, a polycrystalline silicon film 323 is deposited as shown in FIGS. 27A and 27B. The area other than the wide area is completely embedded.

Further, in this state, as shown in FIGS. 28A and 28B, a resist R is filled in a trench which is not completely filled with the polysilicon film 323 to perform anisotropic etching of the polysilicon. The polycrystalline silicon film 308 functioning as a cell plate is left on the side wall of the wide trench.

Thereafter, as shown in FIGS. 29 (a) and (b), a capacitor insulating film 307 made of a silicon nitride film is formed, and as shown in FIGS. 30 (a) and (b), a storage node electrode is formed. A phosphorus-doped polycrystalline silicon film to be 306 is deposited, the polycrystalline silicon film is etched back, the storage node electrode 306 is embedded in the trench, and the surface of the storage node electrode is oxidized to form a silicon oxide film 316. Next, FIGS. 31 (a) and 31 (b)
As shown in (1), the capacitor insulating film 307 on the element region is removed by isotropic etching, and the polycrystalline silicon film on the plate electrode is partially removed by isotropic etching of polycrystalline silicon. A silicon oxide film 324 is formed in the thus obtained depression as a low stress insulating film by the LPD method, and the depression is filled by performing anisotropic etching.

Further, a gate insulating film 309 is formed, a polycrystalline silicon film 310 is further formed as a gate electrode, and the surface is oxidized to cover the periphery of the gate electrode with a silicon oxide film 317. , 312 are formed (FIG. 32A and
(b)).

Then, as shown in FIGS. 33A and 33B, after forming the storage node contact, a polycrystalline silicon film serving as a pad 314 connecting the storage node electrode 306 and the n-type layer 312 is formed. 24, 25, a BPSG film 320 for planarization and the like are formed, and a bit line contact is formed to form a bit line 331.
The DRAM shown in (a) and (b) is completed.

According to the DRAM thus formed, since a low stress film by deposition is used as the insulating film, damage to the substrate element region can be prevented as compared with the case of the insulating film due to oxidation of the plate. Junction leak can be prevented.

Further, since the capacitor region also serves as element isolation, it is possible to significantly reduce the cell area, and to provide a DRAM which is easy to manufacture and has high reliability. In the above embodiment, the silicon oxide film formed by the LPD method is used as the low stress film. However, the present invention is not limited to this, and another film such as a silicon oxide film formed by the LPCVD method or an LPCVD-based film can be used. is there.

[0078]

As described above, according to the present invention, the capacitor portion of each cell is divided at the same time as the buried isolation between the elements, and the fine and highly reliable cell can be easily formed without increasing the number of steps. A structure can be formed.

[Brief description of the drawings]

FIG. 1 is a diagram showing a DRAM according to a first embodiment of the present invention;

FIG. 2 is a diagram showing a DRAM according to a first embodiment of the present invention;

FIG. 3 is a manufacturing process diagram of the DRAM.

FIG. 4 is a manufacturing process diagram of the DRAM.

FIG. 5 is a manufacturing process diagram of the DRAM.

FIG. 6 is a manufacturing process diagram of the DRAM.

FIG. 7 is a diagram showing a modification of the DRAM of the embodiment of the present invention.

FIG. 8 is a diagram showing a DRAM according to a second embodiment of the present invention;

FIG. 9 is a diagram showing a DRAM according to a second embodiment of the present invention;

FIG. 10 is a manufacturing process diagram of the DRAM.

FIG. 11 is a manufacturing process diagram of the DRAM.

FIG. 12 is a manufacturing process diagram of the DRAM.

FIG. 13 is a manufacturing process diagram of the DRAM.

FIG. 14 is a diagram showing a modification of the DRAM of the embodiment of the present invention.

FIG. 15 is a manufacturing process diagram of the DRAM.

FIG. 16 is a manufacturing process diagram of the DRAM.

FIG. 17 is a manufacturing process diagram of the DRAM.

FIG. 18 is a manufacturing process diagram of the DRAM.

FIG. 19 is a manufacturing process diagram of the DRAM.

FIG. 20 is a manufacturing process diagram of the DRAM.

FIG. 21 is a manufacturing process diagram of the DRAM.

FIG. 22 is a manufacturing process diagram of the DRAM.

FIG. 23 is a diagram showing a modification of the DRAM of the embodiment of the present invention.

FIG. 24 is a diagram showing a DRAM according to a third embodiment of the present invention;

FIG. 25 is a diagram showing a DRAM according to a third embodiment of the present invention;

FIG. 26 is a manufacturing process diagram of the DRAM.

FIG. 27 is a manufacturing process diagram of the DRAM.

FIG. 28 is a manufacturing process diagram of the DRAM.

FIG. 29 is a manufacturing process diagram of the DRAM.

FIG. 30 is a manufacturing process diagram of the DRAM.

FIG. 31 is a manufacturing process diagram of the DRAM.

FIG. 32 is a manufacturing process diagram of the DRAM.

FIG. 33 is a view showing the manufacturing process of the DRAM.

FIG. 34 is a diagram showing a conventional trench memory cell.

FIG. 35 shows a conventional trench memory cell.

FIG. 36 is a view showing a conventional trench memory cell.

[Explanation of symbols]

 Reference Signs List 1 p-type silicon substrate 3 field oxide film 5 trench 6 n-type layer 6 s storage node electrode 7 capacitor insulating film 8 plate electrode 9 gate insulating film 10 gate electrode (word line) 11, 12 source / drain region (N-type layer) 20 insulating film 21 n-type layer 31 bit line 101 p-type silicon substrate 103 field oxide film 105 trench 106 storage node electrode 107 capacitor insulating film 108 plate electrode 109 gate insulating film 110 gate electrode (word) Line) 111, 112 source / drain region (n-type layer) 131 bit line 120 insulating film 121 n-type layer 141 storage node contact 151 element region 201 p-type silicon substrate 205 trench 206 storage node electrode 206h storage Node contact 2 7 the capacitor insulating film 208 plate electrode 209 gate insulating film 210 gate electrode (word line) 211,12 source - scan and drain regions (n-type layer) 220 insulating film 231 bit line 251 the element region

──────────────────────────────────────────────────続 き Continuation of the front page (72) Katsuhiko Hieda, Inventor Toshiba Research Institute, Komukai Toshiba-cho, Sachi-ku, Kawasaki-shi, Kanagawa Prefecture (56) References JP-A-62-136868 (JP, A) 63-255960 (JP, A) JP-A-1-128559 (JP, A) JP-A-5-21747 (JP, A) (58) Fields investigated (Int. Cl. ⁷ , DB name) H01L 27 / 108 H01L 21/8242 H01L 27/12

Claims (3)

(57) [Claims] 1. An SOI substrate in which a silicon layer is formed on an insulating region is formed so as to leave an island region stacked with an element region made of the silicon layer and an insulating region below the element region. A trench and a MOSFET formed in the silicon layer in the island region
A plate electrode made of a polycrystalline silicon layer completely filled with a narrow region inside the trench and leaving a wide region, a capacitor insulating film formed on the plate electrode; , A capacitor formed by a storage node electrode embedded in a concave portion remaining in a wide area, and a storage node electrode of the capacitor and the MO.
And a memory cell connected to one of a source and a drain region of the SFET. 2. A trench formed so as to leave an island-shaped element region on a surface of a semiconductor substrate having one conductivity type, and a gate electrode embedded in a small groove formed on an upper surface of the island-shaped element region. A MOSFET in which a source / drain region is formed; a plate electrode made of a polycrystalline silicon layer filled in the trench while completely closing a narrow region and leaving a wide region; A capacitor insulating film and a capacitor formed by a storage node electrode buried in a concave portion remaining in a wide area of the trench, and a connection electrode formed in a self-aligned manner with the gate electrode, A storage node electrode of the capacitor and the MOSF
A semiconductor device wherein one of a source and a drain region of the ET is connected. 3. A trench forming step of forming a trench while leaving an island-shaped element region on the surface of a substrate of one conductivity type, wherein a narrow region is completely closed and a wide region is left inside the trench. Forming an element isolation region by depositing a polycrystalline silicon film via an insulating film, and further depositing a silicon oxide film on a surface of the polycrystalline silicon film by a CVD method or an LPD method; A capacitor forming step of forming a capacitor in a concave portion remaining in a wide area of an island, and an island-shaped element surrounded by the element isolation region so that a storage node electrode of the capacitor is connected to one of a source / drain region. M to form MOSFET in region
A method for manufacturing a semiconductor device, comprising: an OSFET forming step.