TW564548B - Semiconductor device and the manufacturing method thereof - Google Patents

Abstract

The semiconductor device of the present invention includes: a semiconductor substrate; source and drain regions; a channel region; a gate insulating film; a charge storage layer; and a control gate electrode. The source and drain regions are formed on the semiconductor substrate, which include the first impurities of the first conductivity type. The channel region are formed on the semiconductor substrate between the source and drain regions, which includes the second impurities of a second conductivity type. The gate insulating film are formed on the semiconductor substrate, which includes the second impurities in a region thereof located immediately above at least a portion of the channel region. The charge storage layer is formed on the gate insulating film above the channel region. The control gate electrode is provided on the charge storage layer. The control gate electrode is formed on the charge storage layer, and is electrically connected to the charge storage layer by a connection portion provided on a part of the charge storage layer, which is located immediately above at least a part of the region of the gate insulating film including the second impurities.

Description

564548 A7 __B7 V. Description of the Invention (!) Cross-Relaxation of Related Applications This application is based on Japanese Patent Application No. 2001 · 15 8066 on May 28, 2001, and Japanese Patent Application No. 2001-201866 on July 2, 2001. And claim its priority. The overall contents are shown below. BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device and a method for manufacturing the same. This is particularly relevant to a fine semiconductor device having a transistor in which an impurity is implanted in a channel region. It is also related to the structure of the core part of the NAND flash memory. In recent years, EEPROM (Electrically Erasable and Programmable Read Only Memory), which is a non-volatile semiconductor memory that can perform the electrical writing and erasing of data, is more famous. EEPROM contains flash memory that can be deleted in its entirety. In particular, NAND-type flash memory, which is easily accumulative, is widely used. Conventional NAND flash memory manufacturing methods, for example, IEDM (1994) pp61-64, A 0.67 / zm2 SELF-ALIGNED SHALLOW TRENCH ISOLATION CELL (SA-STI CELL) FOR 3V proposed by S. Aritome et al. -only 256 Mbit NAND EEPROMs ", and 1998 Symposium on VLSI Technology Digest of Technical Papers proposed by Y. Takeuchi et al., pp 102-103 · 'A Self-Aligned STI Process Integration for Low Cost and Highly Reliable 1 Gbit Flash Memories " According to the proposal, the element isolation area between the memory cells is formed by STI (Shallow Trench Isolation, Shallow Trench Isolation) technology. Therefore, in order to have a self-integrating structure for this element isolation area-5- This paper Standards are in accordance with China National Standard (CNS) A4 specifications (210X 297 mm) 564548 A7 ---- * ----------- V. Description of the invention (2) (SA-STI), forming a floating Gate. With this method, a high-density memory cell array with fine memory cells can be realized. In this manufacturing method, the element isolation area will be formed after forming part or all of the interlayer oxide film and floating open-electrode material ... Impurities The channel area of the transistor introduced into the memory cell and the peripheral control system can be implanted with ions before the gate oxide film is formed, and then the gate oxide film is formed. The thermal diffusion of the inductive impurities is followed by The heat treatment is performed in the step of forming the isolation region of the element, and the impurities will be activated due to the diffusion. "~ However, the NAND type flash memory writes" 丨 "data in the memory cell (the floating gate is not implanted with electrons, and it is maintained. When the threshold is deleted), the bit line will be charged to the starting potential. Further, a nesting voltage is applied to the selected word line, and a transmission voltage is applied to the non-selected word line. Secondly, the potential of the channel region of the memory cell transistor is boosted by capacitive coupling, so that the electrons will not be implanted on the floating gate. Reducing the impurity concentration in the channel region will reduce the channel capacitance, so the potential in the channel region is likely to be boosted. As a result, the incorporation characteristics of the "i" data of the memory cells are improved. In view of the aforementioned nesting actions, several flash memory manufacturing methods focusing on the control of the impurity concentration in the channel region of the memory cell crystal have been proposed. For example, in the method of JP-A-2002-009173, after a gate oxide film and a device isolation region are sequentially formed, ions are implanted across the gate oxide film and the floating gate. With this method, the impurity concentration distribution in the channel region is not affected by the thermal steps in the manufacturing process of the device isolation region. Therefore, a rapidly changing impurity concentration distribution can be achieved. Therefore, when the miniaturization of the channel length is promoted, the controllability of the impurity concentration in the channel region can be ensured. -6- 564548

Also, in US Patent Application No. 10 / 058,343 (corresponding to Japanese Patent Application No .: Japanese Patent Application No. 2001-23973), the proposal is mainly directed to a NAND flash memory. That is, after forming a mask on the memory cell transistor, the impurity diffusion layer between adjacent selected transistors is implanted with ions from an oblique direction. With this method, the impurities in the channel region of the cell transistor and the selected transistor are retained; the degree will remain the same, and it is easy to implement the characteristic control of the selected transistor. Secondly, U.S. Patent Application No. 09 / 956,986 (corresponding to Japanese Patent Application No .: 2000-291910) is also a proposal for NAND-type flash memory. That is, a method of removing the gate insulating film that isolates the floating gate and the control gate from the peripheral control system transistor and the gate of the selection transistor. In this way, the floating gate and the control gate can be electrically connected. In Japanese Patent Application Laid-Open No. 59-74677, as shown in FIG. 4 to FIG. 11 and the like, peripheral transistors are provided. An opening is provided on the insulating film between the floating gate and the control gate. As a result, the degree of freedom in wiring design is improved. As mentioned above, various proposals have been made in the past regarding the method of manufacturing flash memory. However, in the method of forming an element isolation region after forming the channel region, impurities in the channel region are likely to diffuse, which may hinder the miniaturization of the transistor < channel length. Because there are many thermal steps after the channel area. This phenomenon is particularly noticeable when the gate length of the memory cell crystal is less than 0.2 μm. In addition, the method of performing ion implantation of the channel portion of the memory cell in a non-synchronized manner and the method of ion implantation of the selected channel portion of the transistor are implemented.

564548 A7 B7 V. The invention (4) has its implementation difficulties. In addition, the increase in lithographic printing steps has increased the manufacturing steps. For example, it is difficult to implement a high-density memory cell structure by selecting a miniaturization with a channel length of 0.3 // m or less and a channel length of 0.15 # m or less for a memory cell transistor. However, if the impurity region of the memory cell transistor and the channel region of the selected transistor is formed at the same time, it is difficult to increase the impurity concentration of the channel region of the selected transistor. As a result, the cut-off characteristics of the selected transistor may be deteriorated. That is, the impurity concentration of the channel region of the selected transistor must be set to a concentration that can satisfy the characteristics of the memory cell necessary for the memory cell transistor. This impurity concentration is usually lower than the concentration necessary to select a transistor. In other words, the impurity concentration of the channel region of the transistor must be lower than the ideal concentration. Therefore, the threshold voltage of the selected transistor will decrease, and the standby leakage current will increase, which will prevent normal operation. In addition, the aforementioned memory cell characteristics refer to, for example, the degree of deterioration of data storage characteristics, write-delete characteristics, and write-delete characteristics. However, NAND-type flash memory EEPROM is also the same as other semiconductor memories such as DRAM (Dynamic Random Access Memory) or SRAM (Static RAM). A row decoder selects a word line and executes the selected memory cell (page ) Write or read. The column decoder includes a column main decoder circuit and a column system core (column auxiliary decoder circuit). The column main decoder circuit generates a specific voltage for controlling the gate line and selecting the gate line in the memory cell according to the column address signal. The core of the line system has the function of a switch between the line main decoder circuit and the memory cell line. The structure of the above-mentioned core system will be described with reference to Figs. 1A and 1B. Figure 1A series-8- This paper size applies Chinese National Standard (CNS) A4 specification (210 X 297 mm) 564548 A7 ___ B7 V. Description of the invention (5) is a plan view of the core part, Figure 1B is 1B in Figure 1A · Sectional view of line 1B. As shown in the figure, the silicon substrate 200 is provided with a plurality of grid-shaped active areas AA (Active Area). Between adjacent active regions AA, a device isolation region STI is provided. In each of the active regions AA which are electrically isolated, transmission gate transistors TGTD, TGTS, TGT, TGT, ... are formed, respectively. These transmission gate electric crystals TGTD, TGTS, TGT, TGT, ... each have a gate TG and an impurity diffusion layer (not shown in the figure). The gate electrode TG is provided on the gate insulating film 210 on the active area AA. At the same time, it has a polycrystalline silicon film 220 and a polycrystalline silicon film 240 provided on the polycrystalline silicon film 220 via an inter-gate insulating film 230. The polycrystalline silicon films 220 and 240 are electrically connected to the active region AA. Next, interlayer insulating films 260, 280 are provided so as to cover the transmission gate transistors TGTD, TGTS, TGT, TGT, .... In the aforementioned core part, the gate TGs of the transmission gate transistors TGTD, TGTS, TGT, TGT, ... on the active area AA in the same row are connected together. The impurity diffusion layer (drain region) on one side of the transmission gate transistor TGTD, TGTS, TGT, TGT, ... is connected to the selection gate line SGD on the drain side and the selection gate line SGS on the source side, respectively. , And control gate lines CG, CG, .... That is, the selected gate lines SGD, SGS, and the control gate lines CG, CG, ... are connected to the core portion by a shunt wiring 290 provided in the interlayer insulating film 260. And, it is connected to the impurity diffusion layers of the corresponding transmission gate transistors TGTD, TGTS, TGT, TGT, ... via the connection hole C20. In addition, a specific voltage generated by the column main decoder is applied to the other impurity diffusion layer (source region) on the other side of the transmission gate transistors TGTD, TGTS, TGT, TGT, ... via the metal wiring layer 300. -9- This paper size is in accordance with Chinese National Standard (CNS) A4 (210 X 297 mm) 564548 A7 B7 V. Description of the invention (6) Figure 1C is an enlarged view of Figure 1B. As shown in the figure, a parasitic MOS transistor exists in the area between the adjacent active areas AA along the direction of the control gate line. In this parasitic MOS transistor system, a polycrystalline silicon film 240 is used as a gate, and a gate insulating film 230 and an element isolation region STI are used as gate insulating films. Transmission When the gate transistors TGTD, TGTS, TGT, TGT, ... are on, a high voltage Vpgm is applied to the gate TG. At this time, the aforementioned parasitic MOS transistor may be in an on state. Therefore, an inversion region CH is formed around the element isolation region STI. Therefore, the active region AA adjacent to the device isolation region STI may be turned on in some cases. In addition, the design of the transmission gate transistor TGT avoids that the on-state transmission gate transistor TGT and the off-state transmission gate transistor TGT in the same column are prevented from being adjacent to each other. In other words, the design of the control gate lines of the transmission gate transistors TGT connected in the same row will not cause the selection and non-selection of the control gate lines to be adjacent. The reason is that, especially when writing, a high voltage Vpgm is applied to the active region AA (heterodiffusion layer) of the selected transmission gate transistor TGT. In contrast, 0 V is applied to the non-selected transmission gate transistor TGT active region AA. As described above, when the potential difference between adjacent active regions AA becomes large, the insulation between the active regions AA cannot be maintained. However, if the transmission gate transistors TGTD and TGTS connected to the gate line SGD or SGS and the transmission gate transistor TGT connected to the control gate line CG are set in the same row, it is difficult to avoid the occurrence of the two. Selection and non-selection relationship. This state is described with reference to FIG. 1C. As shown in the figure, linked to the selection -10- This paper size applies the Chinese National Standard (CNS) A4 specification (210 X 297 mm)

Binding t 564548 A7 B7 V. Description of the invention (7) The transmission gate transistor TGT, which controls the gate line CG, and the transmission gate transistor TGTD, which is connected to the non-selected selection gate line SGD, will be phased in the same row. Adjacency. At this time, sandwiching the element isolation region STI, the potentials of the two active regions AA and AA are the high potential Vpgm and the ground potential GND, respectively. Also, a polycrystalline silicon film 240 is formed on the element isolation region STI as a part of the gate TG. A high voltage Vpgm is applied to the polycrystalline silicon film 240 to make the transfer gate transistors TGTD and TGT into an on state. In this way, the potential difference between the active regions AA and AA will exceed the element isolation withstand voltage of the element isolation region STI. As a result, the element isolation region STI sometimes cannot maintain electrical insulation between the active regions AA and AA. In order to solve the aforementioned problems related to the isolation of the components, a method that can be adopted is to increase the width d10 of the element isolation region STI along the direction of the control gate line CG (see FIG. 1A). However, in controlling the direction of the gate line, the transmission gate transistor TGT and the transmission gate transistors TGTD and TGTS may appear adjacent to each other in a random manner. Therefore, in order to solve the foregoing problem, it is necessary to increase the width d10 of the element isolation region STI in the entire core region. As a result, the area of the core portion becomes larger, and the miniaturization of the NAND-type flash memory EEPROM cannot be obtained. SUMMARY OF THE INVENTION A semiconductor device according to the present invention includes: a semiconductor substrate; a source / non-electrode region formed in the aforementioned semiconductor substrate and containing a first impurity of a first conductivity type; and formed in the aforementioned source / drain region Among the aforementioned semiconductor substrates, there are -11- This paper size applies to the Chinese National Standard (CNS) A4 specification (210 X 297 mm) 564548 A7 B7 8 V. Description of the invention (the channel with the second impurity of the second conductivity type) A region; a gate insulating film containing a second impurity at least in a region directly above a portion of the channel region; a charge storage layer formed on the gate insulating film above the channel region; and The control gate provided on the charge storage layer is electrically connected by the connection portion provided on the charge storage layer and the charge storage layer, and the charge storage layer is located at least in the second place. The gate insulating film region of the impurity is directly above a part of the region. Another semiconductor device according to the present invention includes: an element isolation region is electrically isolated from each other; And a first active region group including a plurality of active regions disposed along the first direction; a second active region electrically isolated from each other by an element isolation region and including a plurality of the foregoing active regions disposed in a vertical direction along the first direction Groups; and MOS transistors provided in the aforementioned active regions, respectively; far MOS transistors having a plurality of gates connected in common to the aforementioned j-th active region groups; control gates connected to the memory cells and selection of MOS transistors The crystal < selects the first impurity diffusion layer of the gate; and the second impurity diffusion layer which bears the voltage provided by the column decoder; the aforementioned MOS transistor connected to the selected gate is provided only in the aforementioned second activity The width of the 7C element isolation region between the first active region group including the Mos transistor connected to the selection gate and the adjacent first active region AA group in the active region at the end of the region group. It is larger than the element isolation region between the i-th active region group containing only the MOS transistor connected to the control gate. -12- This paper size is suitable for towel @ a 家 标准 (CNS) A4 specification (⑽X 29? Public love) 564548

degree. According to another method of manufacturing a semiconductor device according to the present invention, the method includes: implanting a first-conductivity impurity having a first concentration on a surface of a semiconductor substrate; forming a gate insulating film on the surface of the semiconductor substrate as described above; and forming the gate insulating film on the surface of the semiconductor substrate A charge storage layer; forming an element isolation region in the semiconductor substrate and the gate insulation film; forming an inter-gate insulation film on the element isolation region and the charge storage layer; forming at least one inter-gate insulation film A part of the masking material on the opening of the surface of the insulating film between the gates is exposed; the first conductive type impurity is implanted in the semiconductor substrate through the opening of the masking material, and its concentration is higher than that of the first concentration. 2nd concentration \ A control gate is formed on the inter-gate insulation film, and the control gate is connected to the charge storage layer through a region in which the inter-gate insulation film has been removed; the charge storage layer and the gate are connected to each other; An interlayer insulating film and the control gate are patterned to form a laminated gate; and a second semiconductor substrate is planted in the semiconductor substrate around the gate. The conductive impurity ′ forms a source / impulse region. Brief description of the surface: Figure 1A is a plan view of a conventional NAND flash memory, Figure 1B is a cross-sectional view of line 1B-1B of Figure 1A, and Figure 1C is an enlarged view of Figure 1B; ___ «13 · This paper The dimensions are applicable to the Chinese National Standard (CNS) A4 specification (210 X 297 public 564548 A7 B7 V. Description of the invention (10) Figure 2 A is a cross-sectional view of a flash memory according to the first embodiment of the present invention; Figure 2B is provided with The impurity concentration distribution in the channel region of the selection transistor of the flash memory according to the first embodiment of the present invention; FIG. 3 A is a circuit diagram of the NAND flash memory according to the first embodiment of the present invention; FIG. 3B is the first embodiment of the present invention. A plan view of a NAND-type flash memory according to an embodiment; FIG. 3C is a cross-sectional view taken along line 3C_3C of FIG. 3B; FIG. 3D is a selection transistor and a memory cell including a NAND-type flash memory according to the first embodiment of the present invention. FIG. 4A, FIG. 4B to FIG. 15A, and FIG. UB are cross-sectional views of manufacturing steps of a NAND flash memory according to the first embodiment of the present invention; FIG. 16A and FIG. 16B are NAND-type flash memory according to the first modification of the first embodiment of the present invention 16C and 16D are cross-sectional views showing the steps of manufacturing a NAND flash memory according to the second modification of the first embodiment of the present invention; and FIG. 17 is a NAND view of the third modification of the first embodiment of the present invention. Fig. 18 is a circuit diagram of a NAND-type flash memory according to the second embodiment of the present invention, and Fig. 19A is a NAND-type flash memory according to the third embodiment of the present invention. A block diagram of part of the internal structure, FIG. 19B is a NAND-type flash memory with the third embodiment of the present invention. 14- This paper size is applicable to China National Standard (CNS) A4 specification (210 X 297 mm) 564548 A7 B7 5. Circuit diagram of the core of the memory cell and column system of the description of the invention (；); FIG. 19C is a plan view of the core of the memory cell and column system of the NAND flash memory according to the third embodiment of the present invention; 19C is a sectional view taken on line 19D_19D; FIG. 19E is a sectional view taken on line 19E-19E of FIG. 19C; FIG. 19F is a sectional view taken on line 19F-19F of FIG. 19C; FIG. 19G is a sectional view taken on line 19G-19G of FIG. 19C; FIG. 20 shows the writing and writing of a NAND flash memory according to the third embodiment of the present invention. FIG. 21A is a plan view of a memory cell array and a core system of a NAND flash memory according to a third embodiment of the present invention, and FIG. 21B is a plan view of a core portion of the transistor gate voltage during the operation of fetching and deleting. A cross-sectional view taken along line 21B-21B; FIG. 22A is a plan view of a core portion of a row system having a NAND flash memory according to a fourth embodiment of the present invention; FIG. 22B is a cross-sectional view taken along line 22B-22B of FIG. 22A; A sectional view taken along line 22C-22C of FIG. 22A; FIG. 23A is a plan view of a core portion of a column system having a NAND flash memory according to a fifth embodiment of the present invention; FIG. 23B is a sectional view taken along line 23B_23B of FIG. 23A; FIG. 25 is a plan view of a core system of a column system of a NAND type flash memory according to a sixth embodiment of the present invention; and FIG. 25 is a plan view of a core system of a column system of a NAND type flash memory according to the seventh embodiment of the present invention. Detailed description of the invention -15- This paper size applies to China National Standard (CNS) A4 (210 X 297 mm) 564548 A7

564548

The channel diffusion layer 19 is formed so as to cover at least the area directly below the opening 16. The channel diffusion layer 18 has the same impurity concentration as the channel diffusion layer U of the memory cell crystal 2. And the channel diffusion layer 18 has the same diffusion distribution in the vertical direction of the semiconductor substrate as the channel diffusion layer. The channel diffusion layer 19 is formed to have a higher impurity concentration than the channel diffusion layer 18 and is deeper than the transport diffusion layer 18. The height of the gate 13 of the transistor 3 is selected to be substantially the same as that of the gate 7 of the memory cell 2. The gate-to-gate insulating film 9 is composed of a laminated film such as a silicon oxide film, a silicon nitride film, and a silicon oxide film (Oxide-Nitride-Oxide) film. In this configuration, the selection transistor 3 can supply a potential to the charge storage layer 14 from the outside. That is, the selection transistor 3 has the function of a general MOSFET. The laminated gate structure is the same as the memory cell 2 except that it has an opening portion 16. In addition, when this embodiment is applied to a flash memory, generally, the length of the gate 7 of the memory cell 2 and the length of the channel region sandwiched by the source and drain regions 4 and 5 are smaller than those of the selected transistor. The length of the gate 13 of 3 and the length of the channel region sandwiched by the source and drain regions 5 and 12. Of course, because of product specifications, the channel length of transistor 3 is sometimes smaller than the channel length of memory cell 2. That is, the length of the gate 7 of the memory cell 2 may be larger than that of the gate 13 of the selection transistor 3. In addition, because of product specifications, the channel length of transistor 3 may also be equal to the channel length of memory cell 2. The size of the opening 16 is about half the length of the gate electrode 13 of the selection transistor 3. For example, if the length of the gate electrode 13 is about 0.3, the length of the opening 16 is about 0.15 // m. In addition, if the gate electrode 7 of the memory cell 2 is -17- This paper size applies the Chinese National Standard (CNS) A4 specification (210 X 297 mm) 564548 A7 B7 V. Description of the invention (14) The length is, for example, about 0.15 / / m, the channel length is approximately 0 · 15 // m, and the overall channel area of transistor 3 is approximately 0.3 // m. As described above, the length of the channel region 11 of the memory cell 2 will be smaller than the sum of the lengths of the channel diffusion layer 18 and the channel diffusion layer 19 of the selection transistor 3. Also, the length of the channel diffusion layer 19 of the transistor 3 can be selected, and the length of the opening portion 16 can be controlled to change. In addition, the amount of ions implanted under the electrode 13 through the opening 16 can be controlled separately from the memory cell 2, so the concentration of the channel diffusion layer of the transistor 3 can be freely set. The impurity concentration of the channel portion of the electric crystal is selected to be, for example, a degree. Fig. 2B shows the p-type impurity concentration distribution in the channel region of the transistor 3 selected in Fig. 2A. As shown in the figure, the distribution of the impurity concentration is based on a region 'directly below the opening portion 16, that is, a region including the central portion of the channel region as the maximum value. As described above, the semiconductor device of this embodiment can realize a memory cell crystal having an electrode length of 0. 15 # m or less. Selective transistors with a gate length of 0.3 or less can be realized. As a result, a more compact semiconductor memory device can be provided than before. In addition to pursuing the aforementioned miniaturization, the cut-off characteristics of selected transistors can also be improved. Therefore, the selection transistor and the memory cell transistor with different channel length dependence of the threshold voltage are realized. In addition, the impurity regions 4, 5, 11, 12, 18, and 19 of the transistors 2 and 3 in FIG. 2 may be formed in a recessed region provided near the surface of the semiconductor substrate 1. FIG. 3A is a circuit diagram of a NAND-type flash memory memory cell using the semiconductor device shown in FIG. 2. FIG. The non-volatile memory cell MC in FIG. 3A has the same structure as the memory cell transistor 2 in FIG. 2. In addition, the selection transistor of FIG. 3A -18- 564548 A7 B7 V. Description of the invention (15) The bodies ST1 and ST2 have the same structure as the selection transistor 3 of FIG. 2. As shown in the figure, the memory cell array has a plurality of memory blocks MB (NAND cells). The memory block MB contains n (n is a natural number) memory cells MC, MC ..... the drain-side selection transistor ST1 and the source-side selection transistor ST2. The neighbors of the memory cells MC, MC, ... will share the source and sink, and their current paths are connected in series. The selection transistor ST1 is connected to one end (the drain side) of the series-connected memory cell MC current path, and the selection transistor ST2 is connected to the other end (the source side). The gates of each memory cell MC are connected to control gate lines CG1 to CGn (character lines WL1 to WLn). The gate of the drain-side selection transistor ST1 is connected to the selection gate line SGD, and the gate of the source selection transistor ST2 is connected to the selection gate line SGS. The source of the selection transistor ST1 in each memory block MB is connected to the bit lines BL1 to BLm of the data line (m is a natural number). The source of the source selection transistor ST2 is connected to the common source line SL. Not shown in the figure, the plurality of memory blocks MB are arranged along the bit lines BL1 to BLm, and each of the element lines BL1 to BLm is connected to the plurality of memory blocks MB. In addition, along the direction of the control gate lines CG1 to CGn, each element line BL1 to BLm is also provided with the same memory block MB. It is not necessary to select both of the transistors ST1 and ST2. As long as the memory block MB can be selected, only one of them can be set. Next, the planar structure of the aforementioned memory cell array will be described with reference to FIG. 3B. Fig. 3B is a plan view of the memory cell array shown in Fig. 3A. As shown in the figure, the plural active areas 21, 21, ... are parallel in a line shape. -19- This paper size applies the Chinese National Standard (CNS) A4 specification (210X 297 mm) 564548 A7 B7

5. Description of the invention (16) Drain region. Also, each active area

Configuration. A source electrode is formed in the active region 21, and 7, 7 lines are arranged between the domains 21 for line intersection. The gates 13 and 13 of ST1 and ST2 are parallel to the gate 7 of the memory cell! The gates 13, near the selection transistors STI and ST2, are provided with openings 16 as described in FIG. In FIG. 3B, a region 20 in a semiconductor substrate is implanted with impurities. One part of this area has the function of channel area of memory cell 2. In addition, the intersections of the active region 21 and the active region 21 are implanted with impurities from the opening 16 into a silicon substrate. The region where the impurities are implanted has the function of selecting the channel region of the transistors STi and ST2. Its impurity concentration is different from the channel region of the memory cell crystal. The source and drain of each memory cell MC, MC, ... are connected together by neighbors. As described above, the plural memory cells MC, MC, ... take a series current path, so a memory block (nand cell) is formed. Next, the cross-sectional structure of the aforementioned memory cell array will be described. FIG. 2A is a cross-sectional view taken along line 2-2 of FIG. 3B. Therefore, the description of the sectional structure in the 2_2 line direction is omitted. Fig. 3C is a cross-sectional view taken along the line 3C-3C in Fig. 3B, and is also a cross-sectional structure of the selective transistor ST1. As shown in the figure, a plurality of element isolation regions 22 are provided in the semiconductor substrate 1 'and an upper portion thereof protrudes from the surface of the semiconductor substrate 1. A channel diffusion layer 19 is formed on the surface of the semiconductor substrate 1 between the element isolation regions 22. A gate insulating film 6 is formed on the channel diffusion layer 19. The material of the gate insulating film 6 is one of a silicon oxide film and a nitrogen oxide film. The gate insulating film 6 is provided with a charge accumulating layer. The size of the paper is suitable for the country ’s standard (CNS) A4 specification (210 X 297 mm) 564548 A7 B7 V. Description of the invention (17) 14, which will be higher than the element Above the isolation area 22. Above the charge accumulation layer 14 and the element isolation region 22, an inter-gate insulating film 15 is formed. A control gate electrode 17 is formed on the inter-gate insulating film 15. The control gate 17 and the charge accumulation layer 14 of the selection transistors ST1 and ST2 are electrically connected, and have the function of selecting the gate lines SGD and SGS. FIG. 3D is a graph of the channel length dependence of the threshold voltage of the selection transistor ST1 (ST2) and the memory cell transistor M.C in this embodiment. As described above, the impurity concentrations of the channel regions of the selection transistors ST1, ST2, and the memory cell transistor MC are not the same. As a result, as shown in FIG. 3D, for the same channel length, the threshold voltage of the memory cell MC will be lower than that of the selection transistors ST1 and ST2. In addition, when the channel length is as small as possible, the threshold voltage of each transistor will decrease rapidly. In Fig. 3D, when the transistors ST1 and ST2 are selected at point A1 and the memory cell transistor is at point A2 (A2> A1), the threshold voltage will drop rapidly. When the channel length is smaller than the points A1 and A2, the characteristics of the transistor will be unstable. Therefore, when launching as a product, the design must make the length of each channel of the selection transistors ST1, ST2, and memory cell transistor MC greater than points A1 and A2, respectively. The channel lengths A1 and A2 are related to AKA2. However, in the memory cell array, the number of memory cell transistors is much larger than other transistors. Therefore, reducing the channel length of the memory cell crystal is indispensable for miniaturizing semiconductor memory devices. By design, the channel length of the selected transistor will be greater than the channel length of the memory cell transistor. The purpose is to set the threshold voltage of the selected transistor to be greater than the threshold of the memory cell transistor. -21- This paper applies the Chinese National Standard (CNS) A4 specification (210X 297 mm) 564548 A7 B7 V. Description of the invention ( 18) the voltage of the voltage, so that the selection of the transistor can obtain the necessary cut-off characteristics. As described above, according to this embodiment, miniaturization of the selective transistor can be achieved. More specifically, finer selection transistors can be obtained. This is because an opening 16 is provided between the charge storage layer 14 and the control gate 17 of the selection transistor. With this opening portion 16, the ion implantation to the channel portion of the selection transistor can be automatically integrated. In the past, when ion implantation was performed on a memory cell transistor and a selective transistor channel in individual steps, the micro-processing accuracy such as dimensional control and calibration accuracy during lithography was limited. However, with this embodiment, ion implantation can be automatically integrated, and these limitations are eliminated. Therefore, miniaturization of the selected transistor can be achieved. In addition, the channel length of the selected transistor is different from the channel length of the memory cell transistor. The design of this method makes the selection transistor and the memory cell transistor have different threshold voltages. At the same time, by using the ion implantation of the opening portion 16, the impurity concentration in the channel region of the selected transistor can be controlled independently of the memory cell transistor. Therefore, the cut-off characteristics of the selected transistor can be improved. In addition, it is possible to compensate for the deterioration of the switching characteristics of the selected transistor due to the miniaturization of the channel length. Therefore, the short path effect of selecting a transistor can be suppressed. As a result, miniaturization and high density of the memory cell array can be further obtained. Secondly, the channel length of the selected transistor can be greater than the channel length of the memory cell, and the impurity concentration of the channel region of the selected transistor can be higher than that of the channel region of the memory cell. Therefore, the threshold voltage of the selected transistor can be greater than the threshold voltage of the memory cell transistor. As a result, a selection transistor with the necessary cut-off characteristics (current cut-off characteristics) was realized. -22- This paper size applies to China National Standard (CNS) A4 (210 X 297 mm)

F 564548 A7 ___ _ B7 5. Semiconductor memory device of invention description (19). Furthermore, by using the opening 16 provided between the floating gate 14 and the control gate 17, the impurity concentration of the channel region of the selection transistor and the memory cell transistor can be changed. Therefore, a selective transistor having a channel region containing a necessary high impurity concentration, and a fine semiconductor memory device including a cell transistor suitable for miniaturization and a low impurity concentration channel region are realized. Therefore, the characteristics of the self-transistor can be improved, such as the characteristics of data writers, data storage, and resistance to read stress. Next, a method for manufacturing a semiconductor device having the above-mentioned configuration will be described with reference to Figs. 4A and 4B to Figs. 15A and 15B. 4A, FIG. 4B to FIG. 15A, and FIG. 15B are cross-sectional views of the manufacturing steps of the NAND-type flash memory, and FIGS. 4A to 15A are the lines 2_2 of FIG. Section structure. As shown in FIGS. 4A and 4B, a sacrificial silicon oxide film 30 is formed on a semiconductor substrate type silicon substrate. The sacrificial silicon oxide film 30 protects the surface of the semiconductor substrate 1 from damage caused by ion implantation. Second, impurities may be introduced into the semiconductor substrate 1 by ion implantation. Then, the introduced impurities are activated to form a double recessed portion including a P-type recessed portion, or an n-type recessed portion and a p-type recessed portion. Next, when the surface of the semiconductor substrate 1 or a recess is formed, channel ion implantation is performed on the surface of the recess to form an ion implantation layer 31. The implanted impurities depend on the memory cell transistor and the conductivity type of the transistor. For example, when the conductivity of the transistor is n-type, a p-type impurity such as boron is introduced. This ion implantation: The purpose is to implement the pathway control of the transistor, so it simultaneously controls the memory cell and -23-

564548 A7 _______B7 V. Description of the Invention (20) The predetermined formation area of the transistor is selected and implemented as a whole. As shown in FIGS. 5A and 5B, after the sacrificial silicon oxide film 30 is peeled off, a gate oxide film 6 is formed on the semiconductor substrate 1. Next, the gate oxide film 6 is laminated with an electrode material of a floating gate, such as polycrystalline silicon [to form a floating gate layer 32. In addition, since the floating gate layer 32 must be conductive, polycrystalline silicon such as Phosphorus is pre-doped. Of course, it is also possible to stack un-doped polycrystalline silicon and then perform ion implantation of phosphorus. Next, a masking material 33 such as a silicon nitride film (ShN4) is formed on the floating gate layer 32. This masking material 33 is used to form an element isolation region. Next, a resist (not shown in the figure) is applied on the masking material 33, and the resist is formed into a pattern of an element isolation region by a photolithography technique. The patterned resist is used as a mask, and the mask material 33 is patterned. The patterned masking material 33 is used as a mask, and the floating gate layer 32, the gate insulating film 6, and the semiconductor substrate are etched. Etching is usually used (Reactive Ion Etching). In this way, a trench (not shown in the figure) is formed from the surface of the mask material 33 to the semiconductor substrate j. The depth of the groove is, for example, about 0.25 # m. Next, the side and bottom surfaces of the trench are oxidized at a high temperature to form a silicon thermal oxide film. The purpose of forming this thermal oxide film is to restore the damage suffered during etching, protect the interfaces of the layers, or for other purposes. Then, for example, a CVD (Chemical Vapor Deposition) method is used to laminate the silicon oxide film 34 for element isolation. At this time, HDP_CVD (High Density Plasma CVD, high-density plasma CVD) method or the like is used. Then, the laminated silicon oxide film 34 is flattened, so that the surface on the masking material 33 and the surface on the silicon oxide film 34 -24- This paper size is applicable @ ϋ 家 料 (CNS) A4 size (⑽X 297) Love) 564548 A7 B7 5. The invention description (21) is the same. In this planarization step, a CMP (Chemical Mechanical Polishing) method is generally used, and an etch-back method can also be used. When the planarization is performed by the CMP method, the silicon nitride film of the mask material 33 is used as a CMP stopper film. The silicon oxide film 34 is further annealed to increase its density. In this way, the crystallinity of the silicon oxide film 34 is made close to that of the silicon thermal oxide film, and it becomes a good silicon oxide film. As a result, a structure shown in FIGS. 6A and 6B can be obtained. Next, as shown in FIGS. 7A and 7B, the mask material 33 is removed. Then, the upper surface of the silicon oxide film 34 is retracted by RIE or wet etching. In this way, the element isolation region 22 is completed. Next, as shown in FIGS. 8A and 8B, an inter-gate insulation film 35 is laminated on the surface of the exposed element isolation region 22 and the floating gate layer 32. The inter-gate insulating film 35 is, for example, an ONO film. Next, as shown in FIGS. 9A and 9B, a masking material 36 is laminated on the inter-gate insulating film 35. The masking material 36 is, for example, polycrystalline silicon or a silicon oxide film. 10A and 10B, a resist 37 is applied to the masking material 36. The photolithography technique is then used to pattern the resist 37 to remove the resist 37, and its area is at least a part of the area corresponding to the channel area that must be selected as a transistor. As a result, the illustrated opening portion 38 is formed. As shown in Figs. 11A and 11B, the mask material 36 located immediately below the opening portion 38 is removed by etching using the resist 37 as a mask. In the etching step of the mask material 36, for example, a deep UV (Ultraviolet) lithography method is used. With this method, a short-wavelength light source can be used, and extremely high-precision patterning can be implemented. Therefore, the mask material 36 and the opening -25 can be applied to this paper size according to the Chinese National Standard (CNS) A4 specification (210X 297 mm). 22 5. Description of the invention As a result of this step, the edge film 35 is exposed from the bottom of the opening 38. As shown in FIG. 2B and FIG. 2B, in the semiconductor substrate 1 that must be a channel region of the selective transistor I, an ion implantation of impurities is performed to Channel diffusion layer 19. The impurities implanted by the ions will be introduced into the semiconductor substrate 1 through the inter-insulating floating gate layer 32 and the gate insulating film 6. The type of impurities depends on the conductivity type of the selected transistor In the case of η channel, it is possible to use boron and in the case of ρ channel. Phosphorus can be used. In addition, the ion implantation is performed under the state of the remaining resist 37, which can use the resist 37 as a buffer material for ion implantation. In this step, a masking material 36 is present in the area where the memory cell transistor must be formed. The film thickness is set to the extent that the ion species implanted in the masking material 36 will be attenuated in the masking material 36. At the same time, a selective transistor Area, carry off The acceleration of the implanted energy is adjusted so that the ions can penetrate the floating gate layer 32 and reach the semiconductor substrate 1. As shown in FIGS. 13A and 13B, the inter-gate insulating film 35 directly below the opening π is removed by etching. In addition, the ion implantation for the purpose of forming the channel diffusion layer 19 described in FIGS. 12A and 12B may be performed after the inter-gate insulating film 35 is etched in this step. If the inter-gate insulating film remains Implementing ion implantation under the condition of 35 can prevent the surface of the floating gate layer 32 from being contaminated. The inter-gate insulating film 35 has a protective film of the floating gate layer 32, as shown in Figs. 14A and 14B. Remove the masking material 36. The control gate material 39 is formed on the inter-gate insulation film 35. The control gate material 39 contains -26- This paper size applies to China National Standard (CNS) A4 specification (210X 297 mm) 564548 A7 -— _____B7 V. Description of the invention (23) There are metal silicate films such as polycrystalline silicon films and WSi (Tungsten Silicide, crane broken). Of course, instead of using metal silicide films, only polycrystalline silicon films can be used. In addition, Memory cell transistor scheduled The formation area can be a multilayer structure containing a polycrystalline silicon film and a metal silicon compound film, and the selected formation area of the transistor can be a structure containing only a polycrystalline silicon film. Using anisotropic etching such as photolithography and RIE, a control gate Patterning of the electrode, the material 39, the inter-gate insulating film 35, and the floating gate layer 32. As a result, as shown in FIGS. 15A and 15B, a charge storage layer 8, an inter-gate insulating film 9, and a control gate are formed. The gate 7 of the memory cell transistor mc of the pole 10. The gate 13 including the charge accumulation layer 14, the inter-gate insulating film 15, and the selection transistor ST1, ST2 of the control gate 17 is completed. 14A and 14B, when the control gate material 39 is formed of a polycrystalline silicon film, the silicon compound film may be formed by Salidde (Self Aligned Silicide) after performing the patterning of this step. Thereafter, the gate electrodes 7, 13 having a laminated gate structure are used as a mask, and ion implantation is performed to introduce impurities into the semiconductor substrate 1. As a result, source / drain regions 4, 5, and 12 are formed in the semiconductor substrate 1, and the structures shown in FIGS. 2 and 3C are completed. As described above, by using the semiconductor device manufacturing method of this embodiment, a part of the gate-to-gate insulating film 15 that electrically isolates the charge accumulation layer 14 and the control gate π can be removed. This process is also applicable to the gates of the transistors of the peripheral control system and the gates of the selected transistors in the memory cell array. The purpose is to electrically connect the charge accumulation layer 14 and the control gate 17. However, 'Only when the following conditions are met, the aforementioned processing can be performed ____ -27- This paper size is suitable for S ® Home Standards (CNS) M specifications (21GX 297 public directors) Five invention notes (24 in' crossing the floating gate ' The electrode introduces impurities into the semiconductor substrate by ion implantation. A π That is, the impurities will decay in the mask material family of the memory cell without reaching the charge accumulation f, and the charge accumulation can be penetrated through the selected transistor. Layer and gate insulating film and reach the semiconductor substrate. F In this way, between the memory cell and the selection transistor, channel regions with different impurity concentrations will be formed, and the channel regions can meet the necessary characteristics of each transistor. It is not necessary to add new lithographic printing steps to improve the characteristics of each transistor. And the process can be integrated automatically. As mentioned above, the process can be automatically integrated to form a selection transistor with a channel region, and the aforementioned channel region contains a concentration region, Its concentration is different from the impurity concentration in the channel region of the memory cell crystal. As shown in the description of the background of the invention, It is practically difficult to implement ion implantation in each channel region of the transistor and the selected transistor. At this time, the impurity concentration distribution in the channel region of the two will be substantially the same in the horizontal and vertical directions. However, the method of this embodiment is used The ion implantation step through the opening 16 is implemented for the selection of the gate transistor. Therefore, the channel area of the two will have different impurity concentration distributions in the horizontal and vertical directions. Also, in the selection of the transistor, when the channel ion implantation is implemented Part of the ions will remain in the gate insulating film 6. This area is the area containing the area directly below the opening 16. This embodiment can be an n-channel transistor or a p-channel transistor to control the memory cell. Transistors and impurities that are implanted for the purpose of ion implantation can be either boron or phosphorus. In addition, the gate-to-gate insulation film-28- This paper applies the Chinese National Standard (CNS) A4 specification (210X 297) 564548 Five invention descriptions (Ion implantation after forming the open π portion 16 in 25 15 can prevent the increase of lithographic printing steps. As described above, using this The semiconductor device and its manufacturing method can use the openings corresponding to the channel region of the selected transistor to implant the ions in the channel region. Therefore, it is possible to effectively suppress the deviation when the channel is implanted. In a state that the memory cell transistor is covered, ion implantation is performed on the channel region of the selected transistor. Therefore, the concentration of the channel region of the memory cell can be set separately from the channel concentration of the selected transistor. In addition, this embodiment mode Channel regions and the like are formed in the semiconductor substrate. However, it is also possible to form a recessed portion by implanting a low-concentration impurity in a device region of the semiconductor substrate. In addition, a channel region may be formed in the recessed portion. Also, the NAND cell may be Two selection gates are formed by sandwiching eight transistors. However, the number of NAND cell transistors is not limited to eight, and this number is not particularly limited. For example, it can be formed in any number of 8 to 32. In addition, when the distance between the gates of the neighboring memory cell transistor is 0 2 # m or less, the effect of this embodiment is even more significant. In the foregoing embodiment, the description is given when the semiconductor substrate 1 is p-type and the source / non-electrode region is n-type. However, the semiconductor substrate 1 may also be n-type, and the source-drain region 4 may also be? type. The structure of the selection transistor in this embodiment can also be applied to the MOS transistor included in the peripheral circuit. ° As mentioned earlier, channel implantation is not performed via the gate insulating film of the memory cell transistor. Therefore, in particular, it will not lead to a non-floating structure with a floating gate structure. • 29 · This paper is suitable for standardization (CNS) A4 specification (21GX 297 public love)

The characteristics of the volatile 1A memory are deteriorated. In other words, Xi, Xing, and data: stored, but the characteristics of writing and deleting data of the memory cell: =: characteristics may be deteriorated. However, in this embodiment, there is a problem that the characteristics of the memory cell crystal are deteriorated. For the manufacturing method of "= Γ state", it is not necessary to form a lithographic printing step for forming a channel region == an ultra-fine pattern. Instead, it is only used: necessary to select the floating pole of the transistor and control the idle pole. = T technology Yes. Therefore, it will not increase the manufacturing cost nor will it contain the channel area and the memory cell crystal, which is the second choice. The memory cell and the m device with a high-density micro-memory cell crystal need only be added with an ion cloth. It can be realized by planting steps. Also, 'this embodiment is not an edge-hard flash memory that is only effective when a transistor and a memory cell are selected in a regular configuration, and any cell structure can also be used. For example, adjacent The relationship between the distance between the gates and the layered structure of the gates must meet the specific geometric conditions for the purpose of ion implantation, etc., because there are no restrictions that must meet the aforementioned similar conditions at all, so they have a considerable degree of freedom. And FIG. 16B is a cross-sectional view of the semiconductor device manufacturing steps of the aforementioned 丨 embodiment 丨 modification example. The NAND-type flash memory, especially along the control gate Sectional structure in the direction of line CG. First, using the steps described in the first embodiment, the structure of FIG. 7 and FIG. 7 is formed to complete the element isolation region 22. Thereafter, as shown in FIG. 16A, for example, in a floating gate Layer 32 and component isolation area 22 are stacked on top of each other. 30 · This paper ruler New Zealand Customs Group (CNS) A4 specification (after 297) 564548

Scale of polycrystalline silicon layer 40. Then, the polycrystalline silicon layer 40 is planarized by the CMP method. Next, as shown in FIG. 16B, the patterning of the polycrystalline second layer 40 is performed using a light lithography technique and etching. As a result, as shown in the figure, the polycrystalline silicon layers 40 are isolated from each other on the element isolation region 22 along the direction of the control gate line CG, and the ends thereof remain on the element isolation region 22. In this manner, a multi-layered charge storage layer having a floating gate layer 32 and a polycrystalline silicon layer 40 is completed. Next, on the polycrystalline silicon layer 40 and the element isolation region 22, an inter-gate insulating film 35 composed of an ONO film is laminated. Thereafter, the steps described in this embodiment with reference to Figs. 9A and 9B and subsequent drawings are carried out. In the manufacturing method of this modification, after the masking material 33 is removed, a layer of polycrystalline stone is added at an additional 40 °. In this way, the film thickness of the charge storage layer is greater than that of the top of the charge storage layer and the device isolation in the first embodiment. The distance above the area will increase. Therefore, compared with the i-th embodiment, the surface area of the charge accumulation layer in contact with the inter-gate insulating film is increased. The details are that only the area corresponding to the distance between the upper surface of the charge accumulation layer and the upper surface of the device isolation region will increase. Therefore, the storage capacitance of the memory cell will increase. Therefore, controlling the film thickness of the charge accumulation layer, that is, controlling the film thickness of the polycrystalline silicon layer 40, can adjust the memory capacitance of the memory cell portion. Figs. 16C and 16D are cross-sectional views showing the steps of manufacturing a semiconductor device according to the second modification of the first embodiment. The NAND-type flash memory is particularly structured along a cross section along the bit line BL. First, in the steps of the first embodiment described above, the structure of FIG. 9A is formed. -31- This paper size applies to China National Standard (CNS) A4 (210X 297 public directors) 564548 A7 B7

It; a person 'performs the resist 37 and a mask using the steps illustrated in Figs. 10A and 11A.

An impurity is introduced into the semiconductor substrate 丨 through the opening 38. As a result, a plurality of channel diffusion layers 19 are formed in the semiconductor substrate 1. Thereafter, the gate 13 of the transistor is selected through the steps shown in FIGS. 13A and 14A. As shown in the figure, the gate phase is completed, and the gate 13 shown in FIG. 16D has three connecting portions 16, 16, and 16. As described above, the connecting portion 16 may be plural. 16], there are a plurality of channel diffusion layers 19. However, because of the majority of hot steps, Tong # will be integrated. As a result, the impurity concentration distribution in the channel region is roughly shown in FIG. 2B. FIG. 11 is a cross-sectional view of a semiconductor device according to a third modification of the first embodiment, which is a cross-sectional structure of the NAND flash memory, especially along the direction of the control gate line. In the step shown in Figs. 10A and 10B of the first embodiment, the opening is smaller than the gate electrode 13. However, in this modification, as shown in FIG. 7, the opening portion 38 is the same size as the electrode of the selection transistor. Therefore, a selection transistor 47 having a gate electrode 46 in which the inter-gate insulating film 35 is completely removed is formed. A channel region 45 having the same length as the gate electrode 46 is formed. Next, a semiconductor device according to a second embodiment of the present invention will be described with reference to FIG. 18. FIG. 18 is a circuit diagram of a memory cell of an AND flash memory. The paper size of this embodiment applies the Chinese National Standard (CNS) A4 specification (210 X 297 mm) 564548 A7 B7 5. Description of the invention (29) The NAND-type flash memory of the first embodiment is used in place of the first. The semiconductor device of the first embodiment is applied to an AND flash memory. As shown in the figure, the memory cell array has a plurality of memory blocks MB (AND cells). The memory block MB contains η (where η is a natural number and n-4 is shown in the drawing) memory cells MC, a drain-side selection transistor ST1, and a source-side selection transistor ST2. The memory cell transistors MC, MC, ... include a gate connected to the control gate lines CG1 to CG4 (WL1 to WL4), a drain connected in common to the local drain line LD, and a local source line LS in common. Source. The drain-side selection transistor ST1 has a gate connected to the selection gate line SGD, a drain connected to the bit lines BL1, BL2, ..., and a source connected to the local drain line LD. The source-side selection transistor ST2 includes a gate connected to the selection gate line SGS, a drain connected to the local source line LS, and a source connected to the common source line SL. Next, the selection transistors ST1 and ST2 on the drain and source sides have the same configuration as the selection transistors described in the first embodiment. As described above, the memory cell MC and the selection transistors ST1 and ST2 of the AND-type flash memory can also adopt the structures shown in Figs. 2 and 17 described in the first embodiment. The manufacturing methods shown in Figs. 4A, 4B to 16A, and 16B can also be directly applied. Therefore, the flash memory of this embodiment is also the same as the first embodiment described above. Not only can the cut-off characteristics of the selected transistor be improved, but also the miniaturization of the flash memory can be realized. The first and second embodiments are suitable for the entire nonvolatile semiconductor memory device including a selective transistor. Not only can be applied to semiconductor memory devices-3 3-This paper size is applicable to Chinese National Standard (CNS) A4 specifications (210 X 297 mm) 564548 A7 B7 V. Description of the invention (30), can also be used to form peripheral circuits MOS transistor. It can be widely applied to a memory-mixed semiconductor device having a semiconductor memory device. A NAND flash memory EEPROM is taken as an example to describe a semiconductor device according to a third embodiment of the present invention. Fig. 19A is a block diagram showing a schematic configuration of a NAND-type flash memory EEPROM. FIG. 19B is a circuit diagram of the U-series memory cell array and the core of the series. As shown, the NAND-type flash memory EEPROM 60 includes a memory cell 61, an input / output (1/0) circuit 62, a read amplifier 63, an address storage 64, a row decoder 65, a column decoder 66, and High voltage generating circuit 67 and the like. The memory cell array 61 is divided into m memory cell blocks BLK1 to BLKm. Each memory cell block BLK1 to BLKm has a matrix arrangement of NAND cells as shown in FIG. 19B. Each NAND cell contains a plurality of (here, 16 but the number is not limited) memory cells MC, MC, .... Adjacent memory cells MC, MC, ... are connected in series with a common source and drain. One end side of the NAND cell is connected to the bit lines (data lines) BL1 to BLn via the selection transistor ST1, respectively. The source on the other end side of the NAND cell is connected to the source line SL via the selection transistor ST2. The selection gate lines SGD and SGS provided along the column direction of the memory cell row 61 are respectively connected to the gates of the selection transistor ST1 and ST2 in the same row. Similarly, the word lines WL and WL16 arranged along the column direction of the memory cell row 61 are connected to the control gate lines CG1 to CG16 of the memory cells MC, MC, ... in the same row, respectively. For NAND-type flash memory EEPROM, one page is formed by n-bit memory cells MC, MC, ... connected to one word line WL, and 16 pages constitute one of the memory cell blocks BLK1 to BLKm. Piece. Will implement the memory cell sequence in units of 1 page 61 -34- This paper size applies the Chinese National Standard (CNS) A4 specification (210X 297 mm)

Binding

Line 564548 A7 _______ B7__ V. The description of the invention (31) is inserted and read, and the implementation of the deletion is in units of blocks. Various instructions, address signals, and cell data to be written are input to the input / output circuit 62. In addition, the input / output circuit 62 outputs data read from the memory cell 61 and latched in the read amplifier 63. The column address signal and the column address signal input to the input / output circuit 62 are provided to the address register 64. The column address signals latched in the address register 64 are provided to the row decoder 65 and decoded. Furthermore, the column address signals (block address signals, page address signals) latched to the address register 64 are supplied to the column decoder 66 and decoded. The sense amplifier 63 latches the cell data input to the input / output circuit 62 during writing. When reading, the cell data read from the memory cell block BLK1 ~ BLKm selected from the memory cell row 61 to each element line will also be latched. The column decoder 66 includes a column main decoder circuit (not shown in the figure) and a column core (column auxiliary decoder circuit) 68 corresponding to the memory cell blocks BLK1 to BLKm, respectively. The column core portion 68 is a circuit that provides a specific voltage to the selected gate lines SGD, SGS, and 16 word lines WL1 to WL16 in the selected block. With transmission gate transistors TGTD, TGTS, TGT, TGT, ... The gate TG of these transmission gate transistors TGTD, TGTS, TGT, TGT, ... are connected together. Each drain is connected to the selection gate lines SGD and SGS and the control gate lines CG1 to CG16. The column master decoder circuit applies a voltage corresponding to the page address signal to each source. The high voltage generating circuit 67 supplies a high voltage to the aforementioned column decoder 66 and the memory cell 61 according to the input command signal. Next, FIG. 19C to FIG. 19G are used to describe the planar pattern and cross-sectional structure of the core portion of the aforementioned memory cell array and column system. Figure 19C is the core part of the NAND cell. _ -35- This paper size is applicable to the Chinese National Standard (CNS) A4 specification (21 × 297 mm) 564548 A7 B7 V. Description of the plan (32). 19D and 19E are cross-sectional views of a NAND cell, FIG. 19D is a cross-sectional structure taken along a line 19D-19D of FIG. 19C, and FIG. 19E is a cross-sectional structure taken along a line 19E-19E of FIG. 19C. 19F and 19G are sectional views of the core portion, FIG. 19F is a sectional structure taken along the line 19F-19F of FIG. 19C, and FIG. 19G is a sectional structure taken along the line 19G-19G of FIG. 19C. First, the structure of the memory cell is described. As shown in FIGS. 19C to 19E, the silicon substrate 70 has a plurality of strip-shaped active regions AA, and an element isolation region STI is provided between adjacent active regions AA. On the active area AA, a polycrystalline silicon layer 72 is formed through a gate insulating film 71. The polycrystalline silicon layer 72 is a part of the floating gate FG of the memory cell MC and the selection gates SGD and SGS of the selection transistors STI and ST2. The material used for the gate insulating film 71 is, for example, a silicon oxide film or a nitrogen oxide film. A polysilicon layer 74 is provided on the active region AA and the device isolation region STI along a direction intersecting with the active region AA. The polycrystalline silicon layer 74 has a shape covering the polycrystalline silicon layer 72 and is disposed on the polycrystalline silicon layer 72 along the inter-gate insulating film 73. The gate-to-gate insulating film 73 is, for example, a silicon oxide film, a silicon nitride film, a three-layer structure of a silicon oxide film, a single-layer film of a silicon oxide film, and a two-layer structure of a silicon oxide film and a silicon nitride film. ON film or NO film. The polycrystalline silicon layer 74 is part of the memory cell MC,... Bit lines WL1 to WL16, and the selection gate lines S GD, SGS of the selection transistors STI, ST2. Since the impurity diffusion layer 75 serving as a source and an electrode is provided in the broken substrate 70, a memory cell MC and select transistors ST1 and ST2 are formed. In addition, the polycrystalline silicon layers 72 and 74 of the selected transistors STI and ST2 are electrically connected in a shunt region or the like not shown in the figure. In addition, the silicon substrate 70 covers the memory cell MC and the selection transistors ST1, -3 6-This paper size applies the Chinese National Standard (CNS) A4 specification (210 X 297 mm) 564548 A7 丨 B7 V. Description of the invention ( 33) The interlayer insulating film 76 is provided in the ST2 manner. The interlayer insulating film 76 has a metal wiring layer 77 connected to the drain region of the selection transistor ST1 of the selection gate line SGD through the connection hole C1. The metal wiring layer 77 has a function of a bit line BL. An interlayer insulating film 78 is provided on the interlayer insulating film 76 so as to cover the bit lines BL. As described above, 16 memory cells MC ..... and n NAND cells containing the selection transistors ST1 and ST2 are arranged along the word line with the element isolation region STI sandwiched therebetween. Memory cell block BLK. The memory cell array has m memory cell blocks BLK1 to BLKm. The word lines WL1 to WL16 in the memory cell array of the foregoing configuration are connected to the control gate lines CG1 to CG16, and the control gate lines CG1 to CG16 and the selection gate lines SGD and SGS will extend to the column core portion 68. Next, the configuration of the column core portion 68 will be described with reference to Figs. 19C, 19F, and 19G. As shown in the figure, on the Shi Xi substrate 70, a plurality of active regions AA are arranged in a matrix in a region adjacent to the aforementioned memory cell array, and an element isolation region STI is provided between adjacent active regions AA. The electrically isolated active regions AA all form transmission gate transistors TGTD, TGTS, TGT, TGT, .... These transmission gate transistors have a gate insulating film 71 provided on the active region AA, a gate insulating film 73 provided on the gate insulating film 71, and a gate insulating film 73 provided on the gate insulating film 71. A polycrystalline silicon layer 74 and an impurity diffusion layer 75 provided in the active region AA. In addition, the polycrystalline silicon layers 72 and 74 are gate TGs of transmission gate transistors, and the two are electrically connected to each other in the active region AA. -37- This paper size is in accordance with Chinese National Standard (CNS) A4 (210 X 297 mm) 564548 A7 B7 V. Description of the invention (34) The number of rows of the active area AA of the aforementioned core section 68 is, for example, 4 rows. The four transmission gate transistors TG provided in the active area AA of the same row are connected in common. The impurity diffusion layers (drain regions) 75 of the aforementioned transmission gate transistors TGTD, TGTS, TGT, TGT, ... are connected to corresponding selection gate lines SGD, SGS, or control gate lines CG1 to CG16, respectively. That is, the gate lines SGD, SGS, and control gate lines CG1 to CG16 are selected, and the shunt wiring 79 (M0) provided in the interlayer insulating film 76 is extended to the active area where the corresponding transmission gate transistor is provided. AA. Moreover, the impurity diffusion layer 75 (the source region) 75 of the corresponding transmission gate transistor TGTD, TGTS, TGT, TGT, ... is connected to the impurity diffusion layer 75 of the corresponding transmission gate transistor through the connection hole C2. A metal wiring layer 80 is connected to the column master decoder circuit. Next, a voltage is applied to the source region of the transmission gate transistor by the column master decoder circuit via the metal wiring layer 80. The above-mentioned structure is formed in the core region 68 in the active region AA located at the end of the core region, and the transmission gate transistors TGTD and TGTS connected to the selected gate lines SGD and SGS are formed. In the example of Fig. 19C, the transmission gate transistors TGTD and TGTS are provided in the active area AA on the row closest to the column main decoder in the core portion 63. The set of active areas AA on the row closest to the column main decoder is the active area group AA (ST). On the active area AA of the first to third rows near the memory cell 61, only the transmission gate transistors TGT, TGT, ... connected to the control gate lines CG1 to CG16 are provided. In other words, the transmission gate transistors TGTD and TGTS are not formed in the active area AA of the second to fourth rows of the slave master decoder. This column -38- This paper size applies the Chinese National Standard (CNS) A4 specification (210 X 297 mm) 564548 A7 B7 V. Description of the invention (35) The main decoder 2 to 4 rows of active area aa Each set is the active area group AA (MC). The element isolation region STI width dl between the active region group AA (ST) and the adjacent active region group aa (MC) is larger than the element isolation region STI width (dl > d2) between the adjacent active region groups aA (MC). ). As described above, in addition to constituting the column core portion 68, it is connected to the memory cell 61 and the column master decoder. Next, the operation of the aforementioned NAND flash memory EEPROM will be briefly described with reference to FIG. Figure 20 shows the potential relationship between the selected gate line and the control gate line when writing, reading, and deleting. As mentioned earlier, the writing and reading of the memory cell array 6 i is performed in units of one page, and the deletion is performed in units of blocks. The entry of data is implemented sequentially from the memory cell MC farthest from the bit line BL. First, a voltage Vpgm (for example, 20 V) is applied to all the transmission gate transistors TG corresponding to the selected memory cell blocks BLKi to BLKm. In this way, the transmission gate transistors TGTD, TGTS, and TGT, TGT, ... will be in a conducting state. Secondly, the column master decoder applies a write voltage Vpgm (for example, 20 V) to the source regions of the transmission gate transistors TGT, TGT, ... connected to any selected memory cell MC. In addition, an intermediate potential Vppm (for example, 7 V) is applied to the source regions of other (unselected) transmission gate transistors, and Vdd (for example, 5 V) is applied to the source regions of the transmission gate transistors tgTD and TGTS, respectively. And 0 V. As described above, Vdd is applied to the selected gate line SGD of the selected selection transistor ST 1, Vpgm is applied to the control gate line CG of the selected memory cell, and Vppm is applied to the control gate line of the unselected memory cell. 3. Apply 0 -39 to the selection gate line SGS of the selection transistor ST2. This paper size is applicable to China National Standard (CNS) A4 specification (21 × 297 mm)

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Line 564548 A7 B7 V. Description of the invention (36) In the state of V, apply 0 V or an intermediate potential Vm (for example, 7 V) of corresponding data to the bit line BL. When 0V is applied to the bit line BL, this potential is transferred to the drain of the memory cell, and electrons flow into the floating gate FG. In this way, the threshold voltage of the selected memory cell transistor will move forward. This state is a state in which '' 0π data is written. On the other hand, when an intermediate potential Vm is applied to the bit line BL, since no electrons flow in, the threshold voltage does not change and remains negative. This state is the state of writing "Γ" data. In addition, data writing is simultaneously performed on all the memory cells MC, MC, ... of the common control gate line CG. Data is deleted as a whole for all bits in the block. First, a voltage Vpgm (for example, 20 V) is applied to all the transmission gate transistors TG corresponding to any of the selected memory cell blocks BLK1 to BLKm. In this way, the transmission gate transistors TGTD, TGTS, and TGT, TGT , ... will be in a conducting state. Next, the column master decoder applies 0 V to all source regions of the transmission gate transistors TGT, TGT, ... connected to the memory cells MC, MC, ..., and applies the transmission gate voltage In the source regions of the crystals TGTD and TGTS, respectively, a write voltage Vpgm (for example, 20 V) is applied. In this way, under the condition that the potentials of all the control gates CG1 to CG16 are 0 V, the 20 V is applied to the p-type recess (not shown). In this way, all the electrons of the floating gate FG of the memory cells MC, MC, ... will be released to the p-type recess. As a result, the threshold voltage of the memory cell MC will be toward Move in negative direction while executing data Except when data is read, it is the same as when writing and deleting. First of all, the transmission gate transistor -40 of all the corresponding memory cell blocks BLK1 ~ BLKm is selected.-This paper standard applies Chinese national standard (CNS ) A4 specification (210 X 297 mm) 564548 A7 B7 V. Description of the invention (37) TG applies voltage Vpgm (for example, 20 V). The transmission gate transistors TGTD, TGTS and TGT, TGT, ... are in the conducting state. Then The main decoder applies 0 V to the source region of the transmission gate transistor TGT connected to the selected memory cell MC. At the same time, the transmission gate transistor TGT, connected to the unselected memory cell MC, MC, ... In the TGT, ... source region, a read potential Vdd (for example, 5 V) is applied. In addition, a voltage Vdd (for example, 5 V) is applied to the source regions of the transmission gate transistors TGTD and TGTS. In the state where the selected gate lines SGD, SGS of the crystals ST1 and ST2 and the unselected memory cell control gate line are applied with Vdd, and the selected memory cell control gate line is applied with 0 V, whether the selected memory cell is detected A current flows to perform a read operation. Using the NAND-type flash memory EEPROM of this embodiment, the active region AA of the transmission gate transistor TGTD, TGTS, which must be formed, is formed in the end portion of the JJ core portion 68 in a row manner. The adjacent areas of the transmission gate transistors TGTD, TGTS connected to the selected gate line, and the transmission gate transistors TGT connected to the control gate line are arranged in a limited area within the column core portion 68 (Area XI in Figure 19C). Therefore, the withstand voltage between the transmission gate transistor TGTD, TGTS, and the transmission gate transistor TGT only needs to consider this area XI. Therefore, as long as the width d1 of the region XI is larger than the width d2 of the region X2 between adjacent transmission gate transistors TGT, the isolation of the elements in the core portion can be sufficiently maintained. In other words, in order to maintain the withstand voltage between the transmission gate transistors, the element isolation region STI, which has to be widened, is limited to the region XI. The foregoing points will be described more specifically with reference to FIGS. 21A and 21B. Figure -41- This paper size applies to China National Standard (CNS) A4 (210 X 297 mm)

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Line 564548 A7 ___B7 1. Description of the invention (38) _ 21A is a plan view of the core part of a NAND flash memory EEPROM, and FIG. 21B is a cross-sectional view of 21B-21B of FIG. 21A. Moreover, the transmission gate transistors' in the same row in the core need not all correspond to the same memory cell block. As mentioned above, the design of the control gate lines connected to the transmission gate transistors TGT arranged in the same row must prevent the control gate lines from being adjacent to each other in the selected or unselected state. In Fig. 21A, a gate transistor SGD10 is connected to a wire transistor in an unselected block. Therefore, 0 V is applied to the active region AA10 (impurity diffusion layer 75) provided with the transmission gate transistor TGTD10 connected to the selected gate line SGD10. The control gate lines CG11 to CG13 connected to the transmission gate transistors TGT11 to TGT13 in the same column as the transmission gate transistor TGTD10 are selected for writing. Therefore, a high voltage Vpgm is applied to the active regions AA11 to AA13 (impurity diffusion layers) provided with the transfer gate transistors TGT11 to TGT13. Therefore, as shown in FIG. 21B, a potential difference of Vpgm occurs between the active regions AA10 and AA11. Therefore, the width dl of the element isolation region STI between the active regions AA10 and AA11 must be larger than the width d2 of the element isolation region STI between the active regions AA11 and AA12 and the active regions AA12 and AA13. Secondly, the selected gate line SGD connected to the transmission gate transistor TGTD20 on the active region AA20 in a different row from the aforementioned active region AA10 is also an unselected block. Therefore, 0 V is applied to this active region AA20. In addition, the control gate lines CG21 to CG23 connected to the transmission gate transistors TGT21 to TGT23 in the same row as the transmission gate transistor TGTD20 are selected for writing. Therefore, it will also be used for the transmission gate transistor TGT21 ~ TGT23 -42- This paper size applies the Chinese National Standard (CNS) A4 specification (210X 297 mm) 564548 A7 B7 V. Description of the invention (39) AA21 to AA23 apply a high voltage Vpgm. Therefore, as in FIG. 21B, a potential difference of Vpgm occurs between the active regions AA20 and AA21. Therefore, the width dl of the element isolation region STI between the active regions AA20 and AA21 must be larger than the width d2 of the element isolation region STI between the active regions AA21 and AA22 and the active regions AA22 and AA23. Therefore, as shown in the description of the background of the invention, if the width of the element isolation area between the transmission gate transistor connected to the selected gate line and the transmission gate transistor connected to the control gate line is not greater than that connected to the control When a gate line transmits a device isolation region between gate transistors, the device isolation cannot be maintained. As mentioned above, in the conventional method, the isolation region between the transmission gate transistor connected to the selected gate line and the transmission gate transistor connected to the control gate line will appear at the core in a random manner. Inside. However, in this embodiment, the transmission gate transistors TGTD and TGTS connected to the selection gate lines SGD and SGS are provided only in the same row of active regions (AA10, AA20) located at the ends in the core portion. Therefore, as long as the active area (AA10, AA20, AA30, ...) of the row closest to the column main decoder circuit in the core is enlarged, the element isolation area between the active area of the second row (AA11, AA21, AA31, ...) is expanded. Just the width. Element isolation areas in other areas are not necessary to increase the width. Therefore, the area increase in the core portion can be controlled to a minimum, and the insulation resistance of the device isolation area can be sufficiently maintained. Next, a semiconductor device according to a fourth embodiment of the present embodiment will be described with reference to Figs. 22A to 22C. Figure 22A is a plan view of the core. 22B and 22C are cross-sectional views taken along lines 22B-22B and 22C-22C of FIG. 22A. -43- This paper size is in accordance with Chinese National Standard (CNS) A4 (210 X 297 mm) 564548 A7 B7 V. Description of the invention (40) As shown in the figure, in this embodiment, the conventional structure (refer to Figure 1A and In Figure 1B), the gate TG of the transmission gate transistors located in the same column is isolated by the transmission gate transistor as a unit. Furthermore, the metal wiring layer TGMETAL, which is higher than the gate TG level, is used to electrically connect the gates TG of the transmission gate transistors in the same column to each other. That is, as shown in FIG. 22A to FIG. 22C, the polycrystalline silicon layer 74 that transmits a part of the gate transistor TG is on the element isolation region STI between the columns of the isolation active region AA to the inter-gate insulating film Will be removed until 73. As a result, the gates TG can be formed by the polycrystalline silicon layers 72, 74 which are isolated by each transmission gate transistor as a unit. Further, a metal wiring layer 82 is provided in the horizontal interlayer insulating film 76 where the shunt wiring 79 of the selected gate line SGD, SGS, and the control gate line CG is located. The metal wiring layer 82 is connected by the gate TG of the transmission gate transistor and the plug contact 81 in the same column. That is, the metal wiring layer has a function of wiring TGMETAL which connects the transmission gate transistors TG in the same column in common. With the foregoing configuration, the gate isolation electrode TG is not provided on the element isolation region STI between the columns of the isolation active region AA. Therefore, even when a high voltage Vpgm is applied to the gate TG, a high voltage Vpgm is not applied to the element isolation region STI. Therefore, it is possible to prevent a reverse region from being formed in the silicon substrate 70 around the element isolation region STI. As a result, the element isolation can be maintained without increasing the width of the element isolation region. Next, a NAND-type flash memory EEPROM is used as an example to describe a semiconductor device according to a fifth embodiment of the present invention. Figure 23 A Series is a plan view of the core. FIG. 23B is a sectional view taken along line 23B-23B of FIG. 23A. -44- This paper size applies to China National Standard (CNS) A4 (210 X 297 mm)

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Line 564548 A7 B7 V. Description of the Invention (41) As shown in the figure, the column core portion 68 of the NAND flash memory EEPROM of this embodiment is in the structure described in the fourth embodiment, and is along the control gate. An analog gate 83 is added between the transmission gate transistors adjacent to the pole line CG. That is, on the element isolation region STI between the columns of the isolation active region AA, a polycrystalline silicon film 33 is formed along the bit line BL direction. The polycrystalline silicon film 33 passes through the gates TG in the direction of the control gate line CG. The polycrystalline stone film 33 and the gate electrode TG are electrically separated by an interlayer insulating film 73. Regardless of the operating state of the transmission gate transistor, 0 V or -Vdd is applied to the polycrystalline silicon film 33. With the above configuration, 0 V or a negative potential is applied to the analog gate 83. Therefore, the parasitic MOS transistor formed by the analog gate 83, the element isolation region STI, and the silicon substrate 70 is kept off at any time. Therefore, it is possible to prevent the formation of the inverted region in the silicon substrate around the device isolation region STI. As a result, component isolation can be maintained without increasing the width of the component isolation region. In addition, 0 V or -Vdd is applied to the analog gate when the parasitic MOS transistor is η channel. When the parasitic MOS transistor is a P-channel, + Vdd can also be applied to the analog gate. Next, a non-volatile semiconductor memory according to the sixth embodiment of the present invention will be described using a NAND flash memory EEPROM as an example. Figure 24 is a plan view of the core of the series. As shown in the figure, the core of the column system of the NAND flash memory EEPROM of this embodiment is the structure shown in FIG. 22A of the fourth embodiment. The transmission gate transistors TGTD, TGTS, TGT, ... (Rotation. That is, in each active area AA, the gate TG is formed along the direction of the control gate line CG (bit line direction). -45- This paper size applies to the Chinese National Standard (CNS) A4 specification (210 X 297 mm) 564548 A7 _ B7 V. Description of the invention (42) With this structure, the same effect as that of the fourth embodiment can be obtained. In addition, this embodiment is also the same as the fifth embodiment, and can control the direction of the gate line. Analog electrodes are arranged between adjacent active areas AA. Next, a NAND-type flash memory EEPROM is taken as an example to explain the non-volatile semiconductor memory of the seventh embodiment of the present invention. Figure 25 is a plan view of the core part. As shown, the column core of the NAND flash memory EEPROM of this embodiment is the structure of FIG. 22A that explains the fourth embodiment, so that the selection gate line and the control gate line are extended to the column core. Wiring The word lines are at the same level. Using two metal wiring layers TGMETAL1 (MO) and TGMETAL2 (Ml) provided above them, the gate TG of each transmission gate transistor is connected in common. For example, the metal wiring layer TGMETAL1 is provided in the interlayer insulating film 76, and metal wiring layer TGMETAL2 is provided in the interlayer insulating film 78. The metal wiring layers TGMETAL1 and TGMETAL2 of this embodiment are different from the aforementioned third to sixth embodiments in that they are arranged differently The electrodes TG of the transmission gate transistors in the column are connected in common. For example, as shown in FIG. 25, two metal wiring layers TGMETAL1 and TGMETAL2 are alternately connected to two electrodes TG of the transmission gate transistor provided in the column. As described above, a plurality of metal wiring layers that are commonly connected to the gate TG of the transmission gate transistor are arranged in a manner that spans different columns. In addition to the effects of the fourth embodiment described above, the transmission gate can be suppressed. The interaction between the transistors can increase the reliability of the operation of the transmission gate transistor. In addition, in this embodiment, if the gate line SGD (SGS) is selected, the control -46- This paper is applicable to this paper China National Standards (CNS) A4 specification (21 × 297 mm) 564548 A7 B7 V. Description of the invention (43) Extension lines of the gate lines CG, CG, ..., and metal wiring layers TGMETAL1, TGMETAL 2 points separately In the interlayer insulating film that is one layer above, the analog gate described in the fifth embodiment can also be provided. At this time, the insulation withstand voltage of the device isolation region STI can be further increased. As described above, the third to third aspects of the present invention In the seventh embodiment, in the core portion of the NAND-type flash memory EEPROM, the transmission gate transistors connected to the selection gate lines SGD and SGS are collected in a row at the end portion in the core portion. Therefore, only the active region located in this row and the active region adjacent to this region, the transmission gate transistor connected to the selected gate line and the transmission gate transistor connected to the control gate line will be in phase with each other. Adjacency. That is, only the element isolation region in this region needs a high withstand voltage. The withstand voltage here refers to the withstand voltage when a parasitic MOS transistor is used to form a channel region around the element isolation region. Therefore, by simply increasing the width of the element isolation region STI in this region, the other regions are the original element isolation region STI width to obtain the element isolation between the rows of the active region. Therefore, the increase in the area in the core portion can be suppressed to a minimum, and the insulation withstand voltage of the device isolation region can be improved. The gates of the transmission gate transistors are isolated in units of transmission gate transistors. Therefore, a high voltage is not applied to an element isolation region between rows of adjacent transmission gate transistors in the same column to make the transmission gate transistors into a conductive state. Therefore, it does not cause the core area to increase, but it can increase the withstand voltage of the component isolation area. In addition, an analog gate is formed on an isolated area of adjacent elements in the same column. In addition, the potential of the analog gate is a potential at which the parasitic MOS transistor can be turned off. Therefore, it can be further mentioned that -47- This paper size is applicable to Chinese National Standard (CNS) A4 specification (210 X 297 mm) 564548 V. Description of the invention (44) High voltage in the isolation area of the component. In the third embodiment, the inverse-recognition method is used to select the gate transistor of the gate line, which is located closest to the main decoder of the column. ^ ^ ^ 詻 is another example. However, it may be the position closest to the memory cell array. Also, in the third embodiment, all transmission gate transistors j connected to the selection gate line may be collected in the same row at the end of the core. Because of the various factors, do you think that this will not prevent the connection to the control gate line < transmission, any one of the gate transistor and the company's private business ~ the transmission gate transistor is selected in the same gate line In addition, in the aforementioned fourth to seventh embodiments, the transmission pole transistor connected to the selection pole line is located closest to the column main decoder as an example. However, in the fourth to seventh embodiments, In order to improve the withstand voltage of the element isolation area by removing the pole TG on the element isolation area, it is not necessary to arrange the transmission gate transistor connected to the selected gate line on the same end of the core. Link to Select the transmission line transistor of the gate line. In the seventh embodiment, the metal wiring layer TGMETAL spans between two rows of active regions AA, but it can also span more rows. In the third to seventh embodiments, The NAND flash memory EEPROM is taken as an example for description, but it can be applied to all semiconductor memory devices having insulation problems between adjacent active regions. Technically, various attempts and corrections can be made. Therefore, the present invention Views are not limited to the specific description or implementation here. On the contrary, as long as it does not depart from the spirit and scope defined by the patent application and similar inventions, various modifications can be made. Eight) ^^ 297

Claims (1)

564548 1. A semiconductor device characterized in that it contains a semiconductor substrate; a source / drain region formed on the semiconductor substrate and containing a first impurity of a first conductivity type; and between the source and non-electrode regions A channel region containing the second impurity of the second conductivity type formed in the aforementioned semiconductor substrate; and a gate insulating film containing the second impurity at least in a region directly above a portion of the channel region A charge storage layer formed on the gate insulation film above the channel region; and a control gate provided on the charge storage layer, the control gate uses a connection portion provided on the charge storage layer and the foregoing The charge storage layer is electrically connected, and the charge storage layer is located at least directly above a part of the gate insulating film area containing the second impurity. 2. The semiconductor device according to item 1 of the patent application range, wherein the aforementioned channel region contains the same channel region and the surrounding region of the high-concentration channel region, the impurity concentration of which is lower than the aforementioned surface; Concentration channel area. 3. The semiconductor device according to item 1 of the patent application range, wherein the charge storage layer is a floating gate. 4. The semiconductor device according to item 1 of the scope of the patent application, which further includes an inter-gate insulating film, which is provided on the charge accumulation and development area other than the area where the connection portion is provided, and connects the foregoing ^ _ -51 - This paper size is applicable to China National Standard (CNS) A4 specification (210X297 mm) 564548 A8 B8 C8 -------- —__ D8___ 6. Scope of patent application The layered and the aforementioned control gate. 5. The semiconductor device according to item 4 of the scope of patent application, wherein the inter-gate insulating film is a laminated film of a silicon oxide film, a silicon nitride film, and a silicon oxide film. 6. The semiconductor device according to the first item of the patent application scope, wherein the gate insulating film is one of a silicon oxide film and a nitrogen oxide compound film. 7. The semiconductor device according to item 丨 of the patent application range, wherein the impurity concentration distribution in the channel region along the direction of the source region, the channel region, and the non-electrode region is based on the impurities in the region directly below the connection portion. The maximum concentration. 8. The semiconductor device according to item 2 of the scope of patent application, wherein the high-concentration channel region is provided in the semiconductor substrate, and it is provided in a region containing at least the gate impurity film in which the second impurity is implanted. The area directly below. 9. A semiconductor device, comprising: a semiconductor substrate; a memory cell crystal provided on the semiconductor substrate; and a selection transistor provided on the semiconductor substrate, and the memory cell crystal is contained on the semiconductor substrate A first source / drain region formed in the semiconductor substrate and containing a first conductivity type first impurity; a second conductivity type second semiconductor layer formed in the semiconductor substrate between the first source and drain regions and containing an i-th impurity concentration 2 impurity 1st channel region; -52- Sighing about the first gate insulating film on the first channel region; P about the first charge storage layer on the first gate insulating film; and about the first gate on the first charge storage layer The inter-electrode insulation film; and the first control gate electrode on the first inter-gate insulation film, and the selection transistor contains: ^ formed in the semiconductor substrate and contains a first conductivity type third impurity A second source-drain region; a second conductivity-type fourth impurity formed on the semiconductor substrate between the second source-drain region and containing a second impurity concentration higher than the second impurity concentration A second channel region; a second gate insulating film provided on the second channel region and at least a part of which contains the fourth impurity; a second charge accumulation layer formed on the second gate insulating film ; And a second control gate provided on the second charge storage layer, and the second control gate and the second charge storage layer are electrically connected to each other by a connection portion provided on the second charge storage layer; Connection, at least part of the area of the second charge accumulation layer is located in the second gate Immediately above said fourth impurity region of the front-containing insulating film. 10. The conductor device according to item 9 of the scope of the patent application, wherein the second channel region contains a high-concentration channel region and is provided around the high-concentration channel region. Its impurity concentration is lower than that of the high-concentration channel region. Low concentration channel area. 11. The semiconductor device according to item 9 of the scope of the patent application, wherein the aforementioned first and second gate insulating films and the aforementioned first and second charge accumulations -53- This paper standard is applicable to China National Standards (CNS) A4 specifications ( 210X297 mm) 564548 And the aforementioned section! The second control electrode has substantially the same film, respectively. 12. For the semiconductor device in the ninth scope of the patent application, the channel length of the second channel region is greater than the channel length of the aforementioned channel region. 13. The semiconductor device according to item 9 of the scope of patent application, wherein the second charge accumulation layer is a floating gate. 14. The semiconductor device according to item 9 of the scope of patent application, wherein the second inter-gate insulation film is provided on the second charge storage layer and is connected in a region other than the region where the connection portion is provided. The second charge storage layer and the second control gate. 15. The semiconductor device according to item 9 of the patent application scope, wherein the channel length dependency of the threshold voltage of the transistor is different from the channel length dependency of the threshold voltage of the memory cell. 16. The semiconductor device according to item 14 of the scope of patent application, wherein the first and second inter-gate insulating films are laminated films of silicon oxide film, silicon nitride film, and silicon oxide film. ~ 17. The semiconductor device according to item 9 of the scope of patent application, wherein the first and second gate insulating films are one of a silicon oxide film and a nitrogen oxide film. 18. The semiconductor device according to item 9 of the scope of patent application, wherein the impurity concentration distribution in the second channel region along the direction of the second source region, the second channel region, and the second drain region is taken from -54- This paper size applies the Chinese National Standard (CNS) A4 specification (210X297). 564548 6. The scope of patent application: The maximum impurity concentration in the area directly below the connection section. 19. For a semiconductor device in the scope of claim 10 of the patent, the above-mentioned concentration channel region is provided in the aforementioned semiconductor substrate and is of the same type. A region immediately below the region containing the fourth impurity is implanted in at least the second gate insulating film. 20. A method for manufacturing a semiconductor device, comprising: implanting an i-th conductive impurity of the i-th concentration on the surface of a semiconductor substrate; forming a gate insulating film on the surface of the aforementioned semiconductor substrate; ~ forming a charge on the aforementioned gate insulating film An accumulating layer; forming an element isolation region in the semiconductor substrate and the gate insulating film; forming an inter-gate insulating film on the element isolating region and the charge accumulating layer; forming, on the inter-gate insulating film, at least A masking material that exposes the openings on the surface of the inter-gate insulation film; _ through the openings of the masking material, the first conductive impurity is implanted in the semiconductor substrate, the concentration of which is higher than the first concentration A second concentration; a control gate is formed on the inter-gate insulation layer, and the control gate is connected to the charge storage layer through a region where the inter-gate insulation film has been removed; and the charge storage layer and the gate are connected An inter-electrode insulating film and the patterning of the control gate to form a laminated gate; and in the semiconductor substrate around the gate Planting the second conductive type -55- This paper size is suitable for towel family standard (CNS) A4 (210X 297) Patent application The impurity 'forms a source-drain region. 21 · If = Please request a method for manufacturing a semiconductor device in the 2G item of the patent, wherein the second step: forming the aforementioned masking material on the inter-phase insulating film includes forming the aforementioned masking material on the inter-gate insulating film; The aforementioned opening is formed in the mask material. 22 · A method for manufacturing a semiconductor device, characterized in that: a surface of a conductor substrate is implanted with an i-th concentration of a phantom conductive impurity, and a gate insulating film is formed on the surface of the semiconductor substrate; a charge accumulation is formed on the gate insulating film; Layer j, forming an element isolation region in the semiconductor substrate and the gate insulating film; forming a closed-electrode insulating film on the 7C element ㉟g region and the charge accumulation layer; and, on the first and second transistors A masking material is formed on the aforementioned inter-gate insulating film in the predetermined formation region, and the masking material has an opening portion, and at least a part of the surface of the inter-gate marginal film in the aforementioned predetermined region of the transistor is exposed from this opening ; Through the opening portion of the masking material, the first conductive type impurity in the semiconductor substrate has a concentration higher than the second concentration of the first concentration; except for the gate electrode exposed by the opening portion of the masking material Inter-insulation film; a control gate is formed on the inter-gate insulation film, and the control gate passes through the region where the inter-gate insulation film has been removed and the charge accumulation Coupled; '56 - This applies China National Standard Paper Scale (CNS) A4 size [21〇 > < 297 with a well-564548 A8 B8 C8 The charge accumulation layer, the inter-gate insulation film, and the gate core are patterned to form a layer of the first and second transistors and to implant a second guide in the semiconductor substrate around the gate. The impurities form the source and non-electrode regions of the i-th, thorium-second transistors. k 23. The method of manufacturing a semiconductor device according to item 22 of the patent application, wherein forming the aforementioned masking material on the inter-gate insulating film includes forming the aforementioned masking material on the inter-gate insulating film; and The aforementioned opening is formed in the mask material. 24. A semiconductor device, characterized in that: an electrical isolation is performed by an element isolation region, and an active region group including a plurality of active regions arranged along a first direction; " an electrical isolation is performed by an element isolation region And contains a second active group of a plurality of the aforementioned active regions arranged in a vertical direction ordered along the i-th direction; and Mos transistors provided in the foregoing active regions, respectively. The Mos transistors have a plurality of gates connected together among the aforementioned first active region groups, a control gate connected to a memory cell, and a selection of a transistor. The gate is the first impurity diffusion layer and the second miscellaneous diffusion layer that withstands the voltage provided by the column decoder. The above-mentioned% pseudo-transistor connected to the gate is selected only at the end in the second active region group. The width of the element isolation region between the first active region group containing the Mos transistor connected to this selection gate and the adjacent first active region aa group within the aforementioned active 2 region is larger than only Contains 57- 564548 A8 B8 The width of the element isolation region between the aforementioned flexible region groups of the electric signal. • The semiconductor device in Item 24 of the Indian Patent Park, where the gate of the MOS private crystal is shared by the MOS transistors in the same column of each i-th active area group. 26. If the semiconductor device of the item% of the scope of the patent application, the second active area group series is the core part, which is the core part and the decoder selects the gate line or control of the NAND-connected memory cells. The gate line provides switching function when voltage is applied. 27. A semiconductor device, characterized in that: the element isolation region is electrically isolated, and an i-th active region group including a plurality of active regions arranged along the first direction; and the element isolation region is electrically isolated, and A second active region group including a plurality of the aforementioned active regions arranged in a vertical direction along the first direction;-Mos transistors respectively disposed in the aforementioned active regions, and this MOS transistor crystal is implemented in units of the aforementioned active regions The isolation gate, the control gate connected to the memory cell and the selection gate of the selection transistor are the i-th impurity diffusion layer, and the second impurity diffusion layer withstands the voltage provided by the column decoder; covering 纟!] An interlayer insulating film of the M 0 S transistor; and the gate electrode in the active region contained in each of the plurality of the i-th active region groups, which is provided on the interlayer insulating film, and is the gate electrode of the plurality of gate electrodes. Commonly connected wiring layers. 28. If the semiconductor device under the scope of patent application No. 27, -58- This paper size applies to the Chinese National Standard (CNS) A4 specification (210X297 mm; Γ 548548 A8 B8 C8 The aforementioned device isolation region is located between the adjacent active region groups along the first direction, and has an analog gate that is electrically isolated from the gate electrode. A voltage is applied to the analog gate to separate the element isolation region. The gate is in the off state. 'The parasitic MOS transistor with the gate and the insulating film of the analog gate is applied. 29. For a semiconductor device with the scope of patent application No. 27, the gate is covered on the active area along the longitudinal direction, and the two The end portions respectively extend to a part of the aforementioned component isolation region. 30. The semiconductor device according to item 27 of the patent application scope, wherein the aforementioned second active area group series is the core part, and the core part has a selection gate line or a control gate line of a column decoder for a NAND-linked memory cell. Switching function when the line provides voltage. 31. A semiconductor device, characterized in that: a plurality of active regions arranged in a matrix and electrically isolated from each other; and each active region is provided with a MOS transistor, and the gates of the MOS transistors are common when they are in the same column. Connection, each of the MOS transistors has a source-drain region side connected to a column decoder, and a source-animated region side of one of a control gate connected to a memory cell and a selection gate of a selection transistor The MOS transistor connected to the selection gate is only arranged in the same row at the end of the matrix. The inter-row distance of this adjacent active area contains the inter-row distance connected to the active area of the selection gate. Controls the inter-row distance of the active area of the gate. 32. A type of semiconductor device, characterized in that it contains -59- This paper size is applicable to China National Standard (CNS) A4 specification (210X297 mm) 564548 A8 B8 C8 D8 Patent application Matrix configuration, electrically isolated from each other Multiple active regions; each active region is provided with a MOS transistor, each of which has a source-drain region side connected to a column decoder, and a control gate and a selection transistor connected to a memory pack One of the gates is selected from one of the source and the non-electrode region side; and a wiring layer provided at a level different from that of the gates and electrically connected to the gates located in different rows. -60- This paper size applies to China National Standard (CNS) A4 (210 X 297 mm)