CN108695331B - Memory, programming method, erasing method, reading method and electronic device thereof - Google Patents
Memory, programming method, erasing method, reading method and electronic device thereof Download PDFInfo
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- CN108695331B CN108695331B CN201710217698.6A CN201710217698A CN108695331B CN 108695331 B CN108695331 B CN 108695331B CN 201710217698 A CN201710217698 A CN 201710217698A CN 108695331 B CN108695331 B CN 108695331B
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
- H10B41/30—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the memory core region
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C16/00—Erasable programmable read-only memories
- G11C16/02—Erasable programmable read-only memories electrically programmable
- G11C16/04—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS
- G11C16/0408—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS comprising cells containing floating gate transistors
Abstract
The invention provides a memory, a programming method, an erasing method, a reading method and an electronic device thereof, wherein the memory comprises: a semiconductor substrate; a floating gate disposed on the semiconductor substrate; the tunneling oxide layer is arranged on the side wall of the floating gate; the first selection gate and the second selection gate are arranged on two sides of the floating gate in parallel, and the first selection gate and the floating gate and the second selection gate and the floating gate are isolated through the tunneling oxide layer. The memory has small memory unit area, free data writing and erasing speed selection, stable data storage and long service life.
Description
Technical Field
The invention relates to the technical field of semiconductors, in particular to a memory, a programming method, an erasing method, a reading method and an electronic device thereof.
Background
An Electrically Erasable Programmable Read-Only Memory (EEPROM) is a Memory chip with no data loss after power failure, and it can erase existing information on a computer or a dedicated device and reprogram. The EEPROM is a nonvolatile memory, and flash EEPROM among them is rapidly developed. EEPROM is more complex than DRAM, and thus integration of EEPROM is difficult to improve.
The data writing and erasing of the traditional EEPROM are realized by a tunnel oxide window (tunnel oxide) below a Floating gate (Floating gate), and the data writing and erasing speed is limited due to the limited area of the window.
The conventional Flash memory (Flash) etox (eprom Tunnel oxide) technology uses the principle that charges in a floating gate directly Tunnel through a tunneling oxide layer to write and erase data. Because the contact area of the floating gate and the tunneling oxide layer is large, the speed of erasing and writing data in the Flash ETOX storage unit is high. However, the damage of the tunneling oxide layer due to direct tunneling is large, and after multiple times of erasing and writing, the charges stored in the floating gate are easy to be gradually lost through the damaged part, so that the stored data is finally invalid, and the EEPROM also has similar defects.
Therefore, it is necessary to provide a new memory to solve the above technical problems.
Disclosure of Invention
In this summary, concepts in a simplified form are introduced that are further described in the detailed description. This summary of the invention is not intended to identify key features or essential features of the claimed subject matter, nor is it intended to be used as an aid in determining the scope of the claimed subject matter.
In view of the shortcomings of the prior art, one aspect of the present invention provides a memory, comprising:
a semiconductor substrate;
a floating gate disposed on the semiconductor substrate;
the tunneling oxide layer is arranged on the side wall of the floating gate;
the first selection gate and the second selection gate are arranged on two sides of the floating gate in parallel, and the first selection gate and the floating gate and the second selection gate and the floating gate are isolated through the tunneling oxide layer.
Further, the area of the surface of the first selection gate facing the side wall is smaller than or equal to the area of the side wall.
Further, the area of the surface of the second select gate facing the sidewall is less than or equal to the area of the sidewall.
Further, the first selection gate is formed by at least two sub-selection gates which are positioned on the side wall of the floating gate and are arranged at intervals, and/or the second selection gate is formed by at least two sub-selection gates which are positioned on the side wall of the floating gate and are arranged at intervals.
The floating gate, the first selection gate, the second selection gate and the tunneling oxide layer are arranged on the surface of the semiconductor substrate, and the tunneling oxide layer is arranged on the surface of the semiconductor substrate.
Further, a programming operation is performed from the tunneling oxide layer on the side of the first selection gate, and an erasing operation is performed from the tunneling oxide layer on the side of the second selection gate.
Further, still include:
an inter-gate dielectric layer disposed on a surface of the floating gate;
and the control gate is arranged on the surface of the inter-gate dielectric layer.
Further, still include:
and the source electrode and the drain electrode are respectively arranged in the semiconductor substrate at two sides of the floating gate, wherein the source electrode and the drain electrode are both of the first conduction type.
Further, a well region of a second conductivity type is also disposed in the semiconductor substrate, and the source and the drain are disposed in the well region.
In another aspect of the present invention, a method for programming the memory includes:
applying a first voltage to one of the first select gate and the second select gate;
and applying a second voltage to the other of the first selection gate and the second selection gate, wherein a potential difference exists between the first voltage and the second voltage, and electrons are injected into the floating gate from the lower end of the first voltage and the second voltage to realize the programming.
Further, the first voltage ranges from 6V to 12V, and the second voltage ranges from 2V to 5V.
Further, the control gate, the drain and the source are all floated.
In another aspect, the present invention provides an erasing method for a memory, including:
applying a third voltage to one of the first select gate and the second select gate;
and applying a fourth voltage to the other of the first selection gate and the second selection gate, wherein a potential difference exists between the third voltage and the fourth voltage to move electrons stored in the floating gate out of the end with the higher potential of the third voltage and the fourth voltage, so that the erasing is realized.
Further, the third voltage is higher than the fourth voltage, the numerical range of the third voltage is 6V-12V, and the fourth voltage is 0V or negative voltage.
Further, the control gate, the drain, and the source are all floating.
In another aspect, the present invention provides a method for reading a memory, where the memory includes a control gate disposed on the floating gate, and a source and a drain respectively disposed in a semiconductor substrate on two sides of the floating gate, the method includes:
applying an on voltage to the control gate, applying 0V or a negative voltage to the source, and applying a fifth voltage to the drain, wherein the on voltage and the fifth voltage are positive voltages, and the fifth voltage is lower than the on voltage, to achieve the reading.
Further, the first select gate and the second select gate are both floating.
In another aspect of the present invention, an electronic device is further provided, and the electronic device includes the foregoing memory.
According to the memory, the first selection gate and the second selection gate are arranged on two sides of the floating gate in parallel, and the floating gate and the selection gate are separated by the tunneling oxide layer arranged on the side wall of the floating gate, so that compared with the traditional EEPROM, the area of a storage unit is effectively reduced, the window area of the parallel selection gates can be adjusted according to needs, and the data writing and erasing speed is freely selected; the ground of the two selective gates is equivalent, writing can be performed from the tunneling oxide layer of the selective gate on one side, and erasing can be performed from the tunneling oxide layer of the selective gate on the other side, so that repeated writing and erasing of the same tunneling oxide layer are avoided, the damaged rate of the tunneling oxide layer is reduced, and the effective service life of the memory is prolonged; therefore, the memory unit of the invention has small area, can freely select data writing and erasing speeds, and has stable data storage and long service life.
Drawings
The following drawings of the invention are included to provide a further understanding of the invention. The drawings illustrate embodiments of the invention and, together with the description, serve to explain the principles of the invention.
In the drawings:
FIG. 1 illustrates a cross-sectional view of an EEPROM memory of one embodiment of the prior art;
FIG. 2 is a cross-sectional view of a Flash unit architecture of one embodiment of the prior art;
FIG. 3A illustrates a top view of a memory according to one embodiment of the present invention;
FIG. 3B shows a cross-sectional view of a reservoir of one embodiment of the invention, wherein FIG. 3B is a cross-sectional view taken along section AA' in FIG. 3A;
FIG. 4A illustrates a cross-sectional view of a memory device being programmed, in accordance with one embodiment of the present invention;
FIG. 4B shows a cross-sectional view of a memory according to one embodiment of the present invention as it is being erased;
FIG. 5 shows a graph of IV curves when reading memory cell data according to one embodiment of the invention;
fig. 6 shows a schematic diagram of an electronic device in an embodiment of the invention.
Detailed Description
In the following description, numerous specific details are set forth in order to provide a more thorough understanding of the present invention. It will be apparent, however, to one skilled in the art, that the present invention may be practiced without one or more of these specific details. In other instances, well-known features have not been described in order to avoid obscuring the invention.
It is to be understood that the present invention may be embodied in many different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the invention to those skilled in the art. In the drawings, the size and relative sizes of layers and regions may be exaggerated for clarity. Like reference numerals refer to like elements throughout.
It will be understood that when an element or layer is referred to as being "on," "adjacent to," "connected to," or "coupled to" other elements or layers, it can be directly on, adjacent to, connected or coupled to the other elements or layers or intervening elements or layers may be present. In contrast, when an element is referred to as being "directly on," "directly adjacent to," "directly connected to" or "directly coupled to" other elements or layers, there are no intervening elements or layers present. It will be understood that, although the terms first, second, third, etc. may be used to describe various elements, components, regions, layers and/or sections, these elements, components, regions, layers and/or sections should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer or section from another element, component, region, layer or section. Thus, a first element, component, region, layer or section discussed below could be termed a second element, component, region, layer or section without departing from the teachings of the present invention.
Spatial relational terms such as "under," "below," "under," "above," "over," and the like may be used herein for convenience in describing the relationship of one element or feature to another element or feature as illustrated in the figures. It will be understood that the spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. For example, if the device in the figures is turned over, then elements or features described as "below" or "beneath" other elements or features would then be oriented "above" the other elements or features. Thus, the exemplary terms "under" and "under" can encompass both an orientation of above and below. The device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatial descriptors used herein interpreted accordingly.
The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention. As used herein, the singular forms "a", "an" and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms "comprises" and/or "comprising," when used in this specification, specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof. As used herein, the term "and/or" includes any and all combinations of the associated listed items.
Embodiments of the invention are described herein with reference to cross-sectional illustrations that are schematic illustrations of idealized embodiments (and intermediate structures) of the invention. As such, variations from the shapes of the illustrations as a result, for example, of manufacturing techniques and/or tolerances, are to be expected. Thus, embodiments of the invention should not be limited to the particular shapes of regions illustrated herein but are to include deviations in shapes that result, for example, from manufacturing. For example, an implanted region shown as a rectangle will typically have rounded or curved features and/or implant concentration gradients at its edges rather than a binary change from implanted to non-implanted region. Also, a buried region formed by implantation may result in some implantation in the region between the buried region and the surface through which the implantation is performed. Thus, the regions illustrated in the figures are schematic in nature and their shapes are not intended to illustrate the actual shape of a region of a device and are not intended to limit the scope of the present invention.
In order to provide a thorough understanding of the present invention, a detailed structure will be set forth in the following description in order to explain the present invention. The following detailed description of the preferred embodiments of the invention, however, the invention is capable of other embodiments in addition to those detailed.
FIG. 1 illustrates a cross-sectional view of an EEPROM memory of one embodiment of the prior art; fig. 2 is a sectional view showing a Flash unit structure according to an embodiment of the related art.
Among them, the conventional EEPROM as shown in fig. 1 includes: the semiconductor device comprises a tunneling oxide layer formed on a semiconductor substrate, wherein the tunneling oxide layer comprises a thin tunneling oxide layer window 101, a floating gate 102 is arranged on the tunneling oxide layer, a control gate 104 is arranged on the floating gate 102, an inter-gate dielectric layer 103 is arranged between the control gate 104 and the floating gate 102, the inter-gate dielectric layer 103 can be an ONO (oxide-nitride-oxide) dielectric layer, a selection gate 105 is further arranged on the semiconductor substrate outside the floating gate, and a gap exists between the selection gate and the floating gate. The data writing and erasing of the traditional EEPROM are realized by a tunnel oxide window (tunnel oxide) below a Floating gate (Floating gate), and the data writing and erasing speed is limited due to the limited area of the window. After the tunneling oxide layer window is subjected to write-in and erase operations for a long time, the tunneling oxide layer window is damaged (damage), charges stored in the floating gate are easy to be gradually lost through the damaged part, and finally storage data failure is caused.
The conventional flash memory shown in fig. 2 includes: a gate dielectric layer 201 disposed on a semiconductor substrate, a floating gate 202 disposed on the gate dielectric layer 201, an intergate dielectric layer 203 disposed on the floating gate 202, and a control gate 204 disposed on the intergate dielectric layer 203. The conventional Flash memory (Flash) etox (eprom Tunnel oxide) technology uses the principle that charges in a floating gate directly Tunnel through a tunneling oxide layer to write and erase data. Because the contact area of the floating gate and the tunneling oxide layer is large, the speed of erasing and writing data in the Flash ETOX storage unit is high. However, the damage of the tunneling oxide layer due to direct tunneling is large, and after multiple times of erasing and writing, the charges stored in the floating gate are easy to be gradually lost through the damaged part, and finally the stored data is invalid.
Example one
In order to solve the foregoing technical problem, an embodiment of the present invention provides a memory, where the memory mainly includes:
a semiconductor substrate;
a floating gate disposed on the semiconductor substrate;
the tunneling oxide layer is arranged on the side wall of the floating gate;
the first selection gate and the second selection gate are arranged on two sides of the floating gate in parallel, and the first selection gate and the floating gate and the second selection gate and the floating gate are isolated through the tunneling oxide layer.
According to the memory, the first selection gate and the second selection gate are arranged on two sides of the floating gate in parallel, and the floating gate and the selection gate are separated by the tunneling oxide layer arranged on the side wall of the floating gate, so that compared with the traditional EEPROM, the area of a storage unit is effectively reduced, the window area of the parallel selection gates can be adjusted according to needs, and the data writing and erasing speed is freely selected; the ground of the two selective gates is equivalent, writing can be performed from the tunneling oxide layer of the selective gate on one side, and erasing can be performed from the tunneling oxide layer of the selective gate on the other side, so that repeated writing and erasing of the same tunneling oxide layer are avoided, the damaged rate of the tunneling oxide layer is reduced, and the effective service life of the memory is prolonged; therefore, the memory unit of the invention has small area, can freely select data writing and erasing speeds, and has stable data storage and long service life.
In particular, the memory structure of the present invention is described in detail below with reference to fig. 3A-3B, wherein fig. 3A shows a top view of the memory of one embodiment of the present invention; FIG. 3B shows a cross-sectional view of a reservoir of one embodiment of the invention.
As an example, the memory of the present invention may be a non-volatile memory (NVM), and in particular, the memory of the present invention is an EEPROM, including: a semiconductor substrate 300, and a floating gate 302 disposed on the semiconductor substrate 300.
The semiconductor substrate 300 may be at least one of the following materials: silicon, silicon-on-insulator (SOI), silicon-on-insulator (SSOI), silicon-on-insulator-silicon-germanium (S-SiGeOI), silicon-on-insulator-silicon-germanium (SiGeOI), and germanium-on-insulator (GeOI), among others. As an example, in the present embodiment, the constituent material of the semiconductor substrate 300 is single crystal silicon.
In one example, a floating gate 302 is further disposed on the semiconductor substrate 300, and the floating gate 302 covers a portion of the semiconductor substrate 300.
The material of the floating gate 302 may be any suitable material known to those skilled in the art, such as a semiconductor material, and preferably, the material of the floating gate 302 includes polysilicon or doped polysilicon.
In one example, as shown in fig. 3B, a gate dielectric layer 301 is disposed on the surface of the semiconductor substrate below the floating gate 302.
Alternatively, the gate dielectric layer 301 may be an ONO (oxide-nitride-oxide) dielectric layer. Specifically, the gate dielectric layer 301 may be an ONO sandwich structure with three layers of oxide-nitride-oxide, and it should be understood by those skilled in the art that the gate dielectric layer 301 may also be an insulating structure formed by a nitride layer, an oxide layer, or an oxide layer on a nitride layer. The thickness of the gate dielectric layer 301 may be set reasonably according to actual device requirements, and is not limited herein.
In one example, a tunnel oxide layer 303 is disposed on a sidewall of the floating gate, wherein the tunnel oxide layer 303 is on two opposite sidewalls of the floating gate.
In one example, the memory of the present invention further comprises: the first select gate 3041 and the second select gate 3042 are disposed at two sides of the floating gate in parallel, and the first select gate 3041 is separated from the floating gate 302 and the second select gate 3042 is separated from the floating gate 302 by the tunnel oxide layer 303, that is, the first select gate and the second select gate are disposed on the side surfaces of the tunnel oxide layer 303 at two sides of the floating gate respectively.
Further, the areas of the first select gate 3041 and the second select gate 3042 on the sidewalls of the floating gates may be adjusted according to actual needs.
In one example, the surface area of the sidewall of the first select gate 3041 facing the floating gate 302 is smaller than or equal to the area of the sidewall, for example, the top surface of the first select gate 3041 may be lower than the top surface of the floating gate, so the area of the first select gate 3041 is smaller than the area of the sidewall of the floating gate 302 adjacent to the first select gate, or the length of the first select gate 3041 may be smaller than the length of the floating gate, so the area of the first select gate 3041 is smaller than the area of the sidewall of the floating gate 302 adjacent to the first select gate.
In one example, the surface of the sidewall of the second select gate 3041 facing the floating gate 302 has an area smaller than or equal to the area of the sidewall, for example, the top surface of the second select gate 3042 may be lower than the top surface of the floating gate, so that the area of the second select gate 3042 is smaller than the area of the sidewall of the floating gate 302 adjacent to the top surface, or the length of the second select gate 3042 may be smaller than the length of the floating gate, so that the area of the second select gate 3042 is smaller than the area of the sidewall of the floating gate 302 adjacent to the top surface.
For example, the first select gate and the second select gate may cover the entire sidewall of the floating gate, or may cover only a portion of the sidewall of the floating gate, where when adjusting the areas of the first select gate and the second select gate, the areas of the tunnel oxide layers in contact with the two select gates may also change correspondingly, so as to adjust the area of the tunnel oxide layer window, that is, the tunnel oxide layer in contact with the select gate may be defined as a tunnel oxide layer window.
In one example, the first select gate and the second select gate may be symmetrically disposed, or the areas of the first select gate and the second select gate on two sides of the floating gate may be different, for example, the area of one select gate is larger than the area of the other select gate.
In one example, the first selection gate is formed by at least two sub-selection gates which are arranged on the side wall of the floating gate at intervals, and/or the second selection gate is formed by at least two sub-selection gates which are arranged on the side wall of the floating gate at intervals.
Specifically, the material of the first select gate 3041 and the second select gate 3042 may use any suitable material known to those skilled in the art, such as polysilicon or doped polysilicon, or other materials suitable for use as select gates, and in this embodiment, the material of the first select gate 3041 and the second select gate 3042 includes polysilicon.
In one example, the gate dielectric layer 301 further extends to the lower portions of the first select gate 3041 and the second select gate 3042 on both sides of the floating gate, that is, the gate dielectric layer 301 is disposed between the floating gate 302, the first select gate 3041, the second select gate 3042, and the tunnel oxide layer 303 and the surface of the semiconductor substrate 300.
Further, as shown in fig. 3A and 3B, the memory device of the present invention further includes a source 3071 and a drain 3072, the source 3071 and the drain 3072 are respectively disposed in the semiconductor substrate 300 at two sides of the floating gate 302, the source and the drain both have the first conductivity type, for example, the first conductivity type is N-type, and preferably, the source 3071 and the drain 3072 are source and drain heavily doped with N-type impurities.
In one example, the outer end of the source 3071 extends into the semiconductor substrate 300 outside the first select gate 3041, and the extension of the drain 3072 extends into the semiconductor substrate 300 outside the second select gate 3042.
In one example, a well region of a second conductivity type, for example, a P-type well region, is further disposed in the semiconductor substrate 300, the source 3071 and the drain 3072 are disposed in the well region, and the second conductivity type and the first conductivity type are opposite conductivity types, for example, if the first conductivity type is an N-type, the second conductivity type is a P-type, or the first conductivity type is a P-type and the second conductivity type is an N-type. In this embodiment, the invention will be mainly explained in the case where the first conductivity type is an N-type, and the second conductivity type is a P-type.
Further, the memory of the present invention further includes an inter-gate dielectric layer 305, where the inter-gate dielectric layer 305 is disposed on the surface of the floating gate 302, and further, the inter-gate dielectric layer extends to the surface of the tunnel oxide layer 303 toward both sides of the floating gate 302.
Alternatively, the inter-gate dielectric layer 305 may be an ONO (oxide-nitride-oxide) dielectric layer. Specifically, the intergate dielectric layer 305 may be an oxide-nitride-oxide (ONO) sandwich structure with three layers, and it should be understood by those skilled in the art that the intergate dielectric layer 305 may also be an insulating structure such as a nitride layer, an oxide layer, or an oxide layer formed on a nitride layer. The thickness of the inter-gate dielectric layer 305 may be set reasonably according to actual device requirements, and is not limited herein.
Further, the memory of the present invention further includes a control gate 306, and the control gate 306 is disposed on the surface of the inter-gate dielectric layer 305.
Wherein the control gate 306 covers the surface of the inter-gate dielectric layer 305 below it corresponding to the floating gate 302.
In one example, an extending direction of a connecting line between the source and the drain is defined as a first direction, a direction perpendicular to the first direction in a plane of the semiconductor substrate is defined as a second direction, and the control gate extends along the second direction and crosses the floating gate.
Here, "crossing" means that the control gate is formed on both the surface of the intergate dielectric layer 305 on the floating gate 302 and the sidewalls of the floating gate where the first and second select gates are not formed.
The material of the control gate illustratively comprises polysilicon, but may also comprise any conductive or semiconductive material, including, for example, a metallic material.
The tunneling oxide layer of the memory is arranged on the side wall of the floating gate, the control gate is only used for reading data, and the applied voltage is small, so that the damage to the gate dielectric layer at the bottom of the floating gate is small, and the effective service life of the hot carrier injection effect (HCI) and the Negative Bias Temperature Instability (NBTI) of the memory is greatly prolonged.
Illustratively, various contact structures (not shown) are further formed on the control gate, the select gate, the source electrode, and the drain electrode, respectively, so as to lead out the control gate, the select gate, the source electrode, the drain electrode, and the like, and realize electrical connection with an external power supply or an external circuit.
The description of the key components of the memory structure of the present invention is completed so far, and the complete memory structure may further include other parts, which are not described in detail herein.
In summary, according to the memory of the invention, the first select gate and the second select gate are arranged in parallel on two sides of the floating gate, and the floating gate and the select gate are isolated by the tunneling oxide layer arranged on the side wall of the floating gate, compared with the conventional EEPROM, the area of the memory cell is effectively reduced, and the window area of the parallel select gates can be adjusted as required, so that the data writing and erasing speed can be freely selected; the ground of the two selective gates is equivalent, writing can be performed from the tunneling oxide layer of the selective gate on one side, and erasing can be performed from the tunneling oxide layer of the selective gate on the other side, so that repeated writing and erasing of the same tunneling oxide layer are avoided, the damaged rate of the tunneling oxide layer is reduced, and the effective service life of the memory is prolonged; therefore, the memory unit of the invention has small area, can freely select data writing and erasing speeds, and has stable data storage and long service life.
Example two
The invention also provides a programming method, an erasing method and a reading method of the memory as described in the first embodiment. Next, a programming method, an erasing method, and a reading method of the memory are explained and explained with reference to fig. 4A to 4B and fig. 5, in which fig. 4A shows a cross-sectional view when the memory according to one embodiment of the present invention is programmed; FIG. 4B shows a cross-sectional view of a memory according to one embodiment of the present invention as it is being erased; FIG. 5 shows a graph of IV curves when reading memory cell data according to one embodiment of the invention;
the memory of the invention may in particular be a non-volatile memory (NVM), in particular an EEPROM.
As an example, a programming method of a memory of the present invention includes:
applying a first voltage to one of the first select gate and the second select gate;
and applying a second voltage to the other of the first selection gate and the second selection gate, wherein a potential difference exists between the first voltage and the second voltage, electrons are injected into the floating gate from the end with the lower potential of the first voltage and the second voltage, and the electrons are stored in the floating gate to realize the programming.
In one example, the first voltage may have a voltage value greater than the second voltage, the first voltage may have a value ranging from 6V to 12V, such as 6V, 7V, 8V, 9V, 10V, 11V, 12V, etc., the second voltage may have a value ranging from 2V to 5V, such as 2V, 3V, 4V, 5V, etc., and the above value ranges are merely examples, and other suitable voltages may be applied to the present invention.
Further, when a program operation is performed, the control gate, the drain, and the source are all floated (floating).
In this embodiment, as shown in fig. 4A, a low voltage, for example, 5V, is applied to the first select gate 3041, a high voltage, for example, 12V, is applied to the second select gate 3042, the control gate, the drain, and the source are all floated, electrons are injected into the floating gate 302 from the side of the first select gate 3041 through the tunnel oxide layer 303 on the side, and the electrons are stored in the floating gate, so as to implement a programming operation.
As an example, the present invention further provides an erasing method of a memory according to the first embodiment, including:
applying a third voltage to one of the first select gate and the second select gate;
and applying a fourth voltage to the other of the first selection gate and the second selection gate, wherein a potential difference exists between the third voltage and the fourth voltage to move electrons stored in the floating gate out of the end with the higher potential of the third voltage and the fourth voltage, so that the erasing is realized.
Further, the third voltage is higher than the fourth voltage, the third voltage has a value ranging from 6V to 12V, for example, 6V, 7V, 8V, 9V, 10V, 11V, 12V, etc., and the fourth voltage is 0V or a negative voltage.
Further, the control gate, the drain, and the source are all floating.
Specifically, in this embodiment, as shown in fig. 4B, a low voltage of, for example, 0V is applied to the first select gate, and a high voltage of, for example, 12V is applied to the second select gate, where a potential difference exists between the low voltage of 0V and the high voltage of 12V, so as to move electrons stored in the floating gate 302 by programming out of the second select gate 3042, and thus, an erase operation is implemented.
The first selection gate and the second selection gate are arranged in parallel, the selection gates on two sides are equivalent in status, writing (programming) can be performed from the tunneling oxide layer of the selection gate on one side (for example, the tunneling oxide layer on the side of the first selection gate), and erasing can be performed from the tunneling oxide layer of the selection gate on the other side (for example, the tunneling oxide layer on the side of the second selection gate), so that repeated writing and erasing of the same tunneling oxide layer are avoided, the damage rate of the tunneling oxide layer is reduced, and the effective life of the memory is prolonged.
As an example, the reading method of the memory according to the first embodiment of the present invention includes a control gate disposed on the floating gate, and a source and a drain respectively disposed in the semiconductor substrate on both sides of the floating gate, and includes:
applying an on voltage to the control gate, 0V or a negative voltage to the source, and a fifth voltage to the drain, the fifth voltage being lower than the on voltage, wherein the on voltage and the fifth voltage are positive voltages, and the fifth voltage is lower than the on voltage, to enable the reading.
The turn-on voltage is a voltage that can turn on the memory.
Further, the first select gate and the second select gate are both floating.
In this embodiment, the starting voltage may be any voltage value capable of starting the memory, and may be selected reasonably according to the actual condition of the memory.
Further, the value of the fifth voltage may be set according to a turn-on voltage of the memory, and the fifth voltage is lower than the turn-on voltage.
By the reading method, the reading operation of the memory can be normally carried out.
Further, fig. 5 shows a graph of IV curve when reading data of a memory cell according to an embodiment of the present invention, wherein the ordinate in fig. 5 is a value of Ids (source-drain current), and the abscissa indicates a voltage, wherein Vsens in the abscissa indicates a turn-on voltage in a read operation, VT0 indicates a threshold voltage after erasing, VT indicates a threshold voltage after programming, Vcs indicates a gate-source voltage, and it can be seen from the graph that Vsens has an intersection with a curve indicating that an erased memory cell can be turned on and read the current Ids, and then the state of the memory cell is "1"; and the programmed memory cell is not turned on because Vsens is smaller than VT, and the Ids current is very small at the moment, so that the state of the memory cell is 0.
In summary, the method according to the present invention can easily implement the program operation, the erase operation and the read operation of the memory.
EXAMPLE III
The invention also provides an electronic device comprising the memory of the first embodiment.
The electronic device of this embodiment may be any electronic product or device, such as a mobile phone, a tablet computer, a notebook computer, a netbook, a game console, a television, a VCD, a DVD, a navigator, a digital photo frame, a camera, a video camera, a recording pen, an MP3, an MP4, a PSP, and the like, and may also be any intermediate product including a circuit. The electronic device of the embodiment of the invention has better performance due to the use of the memory.
Wherein figure 6 shows an example of a mobile telephone handset. The mobile phone handset 500 is provided with a display portion 502, operation buttons 503, an external connection port 504, a speaker 505, a microphone 506, and the like, which are included in a housing 501.
Wherein the mobile phone handset comprises the memory of embodiment one, the memory comprising:
a semiconductor substrate;
a floating gate disposed on the semiconductor substrate;
the tunneling oxide layer is arranged on the side wall of the floating gate;
the first selection gate and the second selection gate are arranged on two sides of the floating gate in parallel, and the first selection gate and the floating gate and the second selection gate and the floating gate are isolated through the tunneling oxide layer.
The present invention has been illustrated by the above embodiments, but it should be understood that the above embodiments are for illustrative and descriptive purposes only and are not intended to limit the invention to the scope of the described embodiments. Furthermore, it will be understood by those skilled in the art that the present invention is not limited to the embodiments described above, and that many variations and modifications may be made in accordance with the teachings of the present invention, which variations and modifications are within the scope of the present invention as claimed. The scope of the invention is defined by the appended claims and equivalents thereof.
Claims (13)
1. A memory, comprising:
a semiconductor substrate;
a floating gate disposed on the semiconductor substrate;
the tunneling oxide layer is arranged on the side wall of the floating gate;
the source electrode and the drain electrode are respectively arranged in the semiconductor substrate at two sides of the floating gate;
the first selection gate and the second selection gate are arranged on two sides of the floating gate in parallel, and the first selection gate and the floating gate and the second selection gate and the floating gate are isolated by the tunneling oxide layer, wherein the programming operation is performed from the tunneling oxide layer on the side of the first selection gate, and the erasing operation is performed from the tunneling oxide layer on the side of the second selection gate;
and the grid dielectric layer is arranged among the floating grid, the first selection grid, the second selection grid, the tunneling oxide layer and the surface of the semiconductor substrate.
2. The memory of claim 1, wherein an area of a surface of the first select gate facing the sidewall is less than or equal to an area of the sidewall.
3. The memory of claim 1 or 2, wherein an area of a surface of the second select gate facing the sidewall is less than or equal to an area of the sidewall.
4. The memory of claim 1, wherein the first select gate is comprised of at least two spaced apart sub-select gates on sidewalls of the floating gate, and/or wherein the second select gate is comprised of at least two spaced apart sub-select gates on sidewalls of the floating gate.
5. The memory of claim 1, further comprising:
an inter-gate dielectric layer disposed on a surface of the floating gate;
and the control gate is arranged on the surface of the inter-gate dielectric layer.
6. The memory of claim 1, further comprising:
the source and the drain both have a first conductivity type.
7. The memory of claim 6, wherein a well region of a second conductivity type is further disposed in the semiconductor substrate, the source and the drain being disposed in the well region.
8. A method of programming a memory as claimed in any one of claims 1 to 7, comprising:
floating the control gate, the drain and the source;
applying a first voltage to one of the first select gate and the second select gate;
and applying a second voltage to the other of the first selection gate and the second selection gate, wherein a potential difference exists between the first voltage and the second voltage, and electrons are injected into the floating gate from the lower end of the first voltage and the second voltage to realize the programming.
9. The programming method of claim 8, wherein the first voltage has a value ranging from 6V to 12V, and the second voltage has a value ranging from 2V to 5V.
10. An erasing method of a memory according to any one of claims 1 to 7, comprising:
floating the control gate, the drain and the source;
applying a third voltage to one of the first select gate and the second select gate;
and applying a fourth voltage to the other of the first selection gate and the second selection gate, wherein a potential difference exists between the third voltage and the fourth voltage to move electrons stored in the floating gate out of the end with the higher potential of the third voltage and the fourth voltage, so that the erasing is realized.
11. The erasing method of claim 10, wherein the third voltage is higher than the fourth voltage, the third voltage has a value ranging from 6V to 12V, and the fourth voltage is 0V or a negative voltage.
12. A reading method of the memory according to any one of claims 1 to 4, the memory including a control gate provided on the floating gate, and a source and a drain provided in the semiconductor substrate on both sides of the floating gate, respectively, the reading method comprising:
applying an on voltage to the control gate, applying 0V or a negative voltage to the source, and applying a fifth voltage to the drain, wherein the first select gate and the second select gate are both floating, the on voltage and the fifth voltage are positive voltages, and the fifth voltage is lower than the on voltage to enable the reading.
13. An electronic device, characterized in that the electronic device comprises a memory according to one of claims 1 to 7.
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| GB2292008A (en) * | 1994-07-28 | 1996-02-07 | Hyundai Electronics Ind | A split gate type flash eeprom cell |
| US5780341A (en) * | 1996-12-06 | 1998-07-14 | Halo Lsi Design & Device Technology, Inc. | Low voltage EEPROM/NVRAM transistors and making method |
| US5918124A (en) * | 1997-10-06 | 1999-06-29 | Vanguard International Semiconductor Corporation | Fabrication process for a novel multi-storage EEPROM cell |
| US20090039410A1 (en) * | 2007-08-06 | 2009-02-12 | Xian Liu | Split Gate Non-Volatile Flash Memory Cell Having A Floating Gate, Control Gate, Select Gate And An Erase Gate With An Overhang Over The Floating Gate, Array And Method Of Manufacturing |
| CN101800226B (en) * | 2010-03-12 | 2014-02-19 | 上海宏力半导体制造有限公司 | Polysilicon storage unit |
| US8669607B1 (en) * | 2012-11-01 | 2014-03-11 | Taiwan Semiconductor Manufacturing Company, Ltd. | Methods and apparatus for non-volatile memory cells with increased programming efficiency |
| CN105448842B (en) * | 2014-08-29 | 2018-07-10 | 中芯国际集成电路制造(上海)有限公司 | The production method of semiconductor devices |
| US9343468B1 (en) * | 2015-03-26 | 2016-05-17 | Texas Instruments Incorporated | Feed-forward bidirectional implanted split-gate flash memory cell |
| US9917165B2 (en) * | 2015-05-15 | 2018-03-13 | Taiwan Semiconductor Manufacturing Co., Ltd. | Memory cell structure for improving erase speed |
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